CN113095015B - SFQ time sequence circuit comprehensive calculation method, system and terminal - Google Patents
SFQ time sequence circuit comprehensive calculation method, system and terminal Download PDFInfo
- Publication number
- CN113095015B CN113095015B CN202110500919.7A CN202110500919A CN113095015B CN 113095015 B CN113095015 B CN 113095015B CN 202110500919 A CN202110500919 A CN 202110500919A CN 113095015 B CN113095015 B CN 113095015B
- Authority
- CN
- China
- Prior art keywords
- sfq
- sub
- state
- state machine
- set information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004364 calculation method Methods 0.000 title claims description 13
- 230000007704 transition Effects 0.000 claims abstract description 106
- 238000013507 mapping Methods 0.000 claims abstract description 83
- 238000000034 method Methods 0.000 claims abstract description 20
- 238000000354 decomposition reaction Methods 0.000 claims description 27
- 230000015654 memory Effects 0.000 claims description 15
- 238000010586 diagram Methods 0.000 claims description 14
- 238000004422 calculation algorithm Methods 0.000 claims description 9
- 238000004590 computer program Methods 0.000 claims description 5
- 230000008521 reorganization Effects 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 10
- 238000003786 synthesis reaction Methods 0.000 abstract description 10
- 238000013461 design Methods 0.000 abstract description 8
- 238000012545 processing Methods 0.000 description 12
- 230000004907 flux Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 238000004458 analytical method Methods 0.000 description 3
- 238000001308 synthesis method Methods 0.000 description 3
- 230000006399 behavior Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000003631 expected effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/10—Processors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention relates to a method, a system and a terminal for comprehensively calculating an SFQ sequential circuit, which respectively interpret and compile state machine descriptions of SFQ logic gate state machines to obtain state transition set information of the state machines, decompose the state transition set information into one or more sub-state machines, map each sub-state machine with each unit gate in an SFQ logic unit library, and recombine each sub-state machine based on the mapping result of each sub-state machine to obtain the SFQ sequential logic circuit structure. The invention utilizes the self advantages of the SFQ logic gate to directly complete the logic mapping from the SFQ logic gate state machine to the SFQ time sequence circuit, reduces two-step operation of simulating the CMOS logic gate in the middle and forming the CMOS time sequence state machine, improves the logic synthesis success rate of the SFQ time sequence circuit and the utilization rate of the SFQ unit library, ensures that the large-scale automatic design of the SFQ time sequence circuit is more efficient, and solves the problems in the prior art.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a method, a system, and a terminal for comprehensive computation of SFQ sequential circuits.
Background
Superconducting integrated circuits refer to integrated circuits based on josephson junctions and superconducting materials, including Single-Flux-QuanTum (SFQ) circuits, among other applications. The SFQ circuit is a comparatively special superconducting integrated circuit, which is mainly composed of josephson junctions, and digital logic "0" and "1" are represented by the presence or absence of magnetic flux quanta Φ0. The tiny and quantized nature of the flux quanta significantly reduces the effects of crosstalk and power consumption compared to conventional semiconductor CMOS (Complementary Metal Oxide Semiconductor) circuits, and the narrow voltage pulses generated in the junction as the flux quanta enter and exit the loop also allow them to achieve extremely high frequencies. The circuit has the advantages of ultra-high working speed and extremely low power consumption, and has remarkable prospect in the application of ultra-wide bandwidth Analog-to-Digital Converter (ADC), superconducting computers and the like.
Since the SFQ logic determines "0" and "1" by the presence or absence of flux quanta, it is necessary to clock the addition clock terminal of the basic cell gate, nor gate, or the like. For SFQ AND NOT AND other logic gates, the behavior of the CMOS logic gate is generally simulated in the form of a state transition diagram, so that the CMOS logic synthesis algorithm can be directly applied to realize the rapid automatic design of the combinational logic. However, in the synthesis of sequential logic, if the conventional CMOS digital circuit synthesis algorithm is used to synthesize the SFQ sequential logic, an algorithm flow of SFQ logic gate state machine, simulating CMOS logic gate behavior, composing CMOS sequential state machine, replacing SFQ sequential state machine is formed, wherein two links of simulating CMOS logic gate and composing CMOS sequential state machine are redundant operations in the SFQ sequential circuit synthesis, and the practical application finds that the flow has the problems that the SFQ cell library cannot be utilized maximally, and the SFQ cells cannot be matched correctly to realize the design expected effect.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention is directed to a method, a system and a terminal for comprehensive computation of SFQ sequential circuits, which are used for solving the problems of logic mismatch, unreasonable circuit overhead, low cell library utilization and the like in the case of adopting a conventional CMOS digital circuit comprehensive algorithm to synthesize SFQ sequential logic.
To achieve the above and other related objects, the present invention provides a method for comprehensively calculating an SFQ sequential circuit, including: interpreting and compiling state machine descriptions of the SFQ logic gate state machine respectively, and obtaining compiling results; acquiring state transition set information corresponding to the SFQ logic gate state machine according to the compiling result; decomposing the state transition set information to obtain sub-state transition set information corresponding to one or more sub-state machines respectively; mapping the sub-state transition set information of each sub-state machine based on the unit gate information of the SFQ logic unit library, and obtaining a mapping result corresponding to each sub-state machine; and recombining each sub-state machine based on the mapping result of each corresponding sub-state machine to obtain the SFQ sequential logic circuit structure.
In an embodiment of the present invention, the interpreting and compiling the state machine descriptions of the SFQ logic gate state machine respectively, and obtaining the compiling result includes: based on a preset SFQ logic customization algorithm, state machine description of an SFQ logic gate state machine is respectively interpreted and compiled, and a compiling result conforming to the SFQ logic is obtained.
In an embodiment of the present invention, the decomposing the state transition set information to obtain sub-state transition set information corresponding to one or more sub-state machines respectively includes: and respectively carrying out one or more iterative decomposition on the state transition set information based on decomposition rules related to the unit gate information of the SFQ logic unit library until one or more sub-state transition set information which cannot be decomposed any more is obtained.
In an embodiment of the present invention, performing one or more iterative decompositions on the state transition set information based on the decomposition rules related to the types of the cell gates in the SFQ logic cell library, until obtaining one or more sub-state transition set information that is not resolvable includes: grouping each state in the state transition set information to obtain one or more state groups with state continuity relation; each state in each state group is allocated to each sub-state machine in turn based on the lowest state number obtained by the cell gate information of the SFQ logic cell library, and one or more sub-state transition set information is obtained which is not resolvable.
In an embodiment of the present invention, the mapping the sub-state transition set information of each sub-state machine based on the element gate information of the SFQ logic element library, and obtaining the mapping result of each corresponding sub-state machine includes: mapping the sub-state transition set information of each sub-state machine with each unit gate in the SFQ logic unit library based on the unit gate information of the SFQ logic unit library, and obtaining a mapping result of each corresponding sub-state machine; wherein the mapping result includes: and a successful mapping result corresponding to the complete mapping success of the sub-state machines and/or a failure mapping result corresponding to the mapping failure of the sub-state machines.
In an embodiment of the present invention, the reorganizing each sub-state machine based on the mapping result of each corresponding sub-state machine to obtain the SFQ sequential logic circuit structure includes: obtaining unit gates mapped by each state machine corresponding to successful mapping results; and connecting the unit gates to obtain the SFQ sequential logic circuit structure.
In an embodiment of the present invention, the state transition set information includes: state transition diagrams and/or state transition tables.
In one embodiment of the invention, the state machine description is in Verilog language.
To achieve the above and other related objects, the present invention provides an SFQ sequential circuit integrated computing system, the system comprising: the compiling module is used for respectively interpreting and compiling the state machine description of the SFQ logic gate state machine and obtaining a compiling result; the state transition set information acquisition module is connected with the compiling module and is used for acquiring state transition set information corresponding to the SFQ logic gate state machine according to the compiling result; the decomposition module is connected with the state transition set information acquisition module and is used for decomposing the state transition set information to obtain sub-state transition set information corresponding to one or more sub-state machines respectively; the mapping module is connected with the decomposition module and is used for mapping the sub-state transition set information of each sub-state machine based on the unit gate information of the SFQ logic unit library and obtaining the mapping result of each corresponding sub-state machine; and the reorganization module is connected with the mapping module and used for reorganizing each sub-state machine based on the mapping result corresponding to each sub-state machine so as to obtain the SFQ sequential logic circuit structure.
To achieve the above and other related objects, the present invention provides an SFQ sequential circuit integrated computing terminal, comprising: a memory for storing a computer program; and the processor is used for executing the SFQ sequential circuit comprehensive calculation method.
As described above, the SFQ sequential circuit comprehensive calculation method, the SFQ sequential circuit comprehensive calculation system and the SFQ sequential circuit terminal have the following beneficial effects: the invention respectively interprets and compiles the state machine description of the SFQ logic gate state machine to obtain state transition set information of the state machine, decomposes the state transition set information into one or more sub-state machines, maps each sub-state machine with each unit gate in the SFQ logic unit library, and recombines each sub-state machine based on the mapping result of each sub-state machine to obtain the SFQ sequential logic circuit structure. The invention directly completes logic mapping from the SFQ logic gate state machine to the SFQ time sequence circuit by utilizing the self advantages of the SFQ logic gate, reduces two-step operation of simulating the CMOS logic gate in the middle and forming the CMOS time sequence state machine, improves the logic synthesis success rate of the SFQ time sequence circuit and the utilization rate of the SFQ unit library, and ensures that the large-scale automatic design of the SFQ time sequence circuit is more efficient.
Drawings
Fig. 1 is a flowchart illustrating an SFQ timing circuit integrated computation method according to an embodiment of the invention.
FIG. 2 is a diagram illustrating the state transition set information decomposition according to an embodiment of the present invention.
FIG. 3 is a schematic diagram of an SFQ timing circuit integrated computing system in accordance with an embodiment of the present invention.
FIG. 4 is a diagram illustrating mapping of sub-state machines according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating the rearrangement of the sub-state machines according to one embodiment of the present invention.
Fig. 6 is a schematic diagram of an SFQ sequential circuit integrated computing terminal according to an embodiment of the invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
In the following description, reference is made to the accompanying drawings, which illustrate several embodiments of the invention. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present invention. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Spatially relative terms, such as "upper," "lower," "left," "right," "lower," "below," "lower," "above," "upper," and the like, may be used herein to facilitate a description of one element or feature as illustrated in the figures relative to another element or feature.
Throughout the specification, when a portion is said to be "connected" to another portion, this includes not only the case of "direct connection" but also the case of "indirect connection" with other elements interposed therebetween. In addition, when a certain component is said to be "included" in a certain section, unless otherwise stated, other components are not excluded, but it is meant that other components may be included.
The first, second, and third terms are used herein to describe various portions, components, regions, layers and/or sections, but are not limited thereto. These terms are only used to distinguish one portion, component, region, layer or section from another portion, component, region, layer or section. Thus, a first portion, component, region, layer or section discussed below could be termed a second portion, component, region, layer or section without departing from the scope of the present invention.
Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" specify the presence of stated features, operations, elements, components, items, categories, and/or groups, but do not preclude the presence, presence or addition of one or more other features, operations, elements, components, items, categories, and/or groups. The terms "or" and/or "as used herein are to be construed as inclusive, or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; A. b and C). An exception to this definition will occur only when a combination of elements, functions or operations are in some way inherently mutually exclusive.
The embodiment of the invention provides an SFQ sequential circuit comprehensive calculation method, which respectively interprets and compiles state machine descriptions of SFQ logic gate state machines to obtain state transition set information of the state machines, decomposes the state transition set information into one or more sub-state machines, maps each sub-state machine with each unit gate in an SFQ logic unit library, and recombines each sub-state machine based on the mapping result of each sub-state machine to obtain an SFQ sequential logic circuit structure. The invention utilizes the self advantages of the SFQ logic gate to directly complete the logic mapping from the SFQ logic gate state machine to the SFQ time sequence circuit, reduces two-step operation of simulating the CMOS logic gate in the middle and forming the CMOS time sequence state machine, improves the logic synthesis success rate of the SFQ time sequence circuit and the utilization rate of the SFQ unit library, ensures that the large-scale automatic design of the SFQ time sequence circuit is more efficient, and solves the problems in the prior art.
The embodiments of the present invention will be described in detail below with reference to the attached drawings so that those skilled in the art to which the present invention pertains can easily implement the present invention. This invention may be embodied in many different forms and is not limited to the embodiments described herein.
As shown in fig. 1, a flow chart of an SFQ sequential circuit comprehensive calculation method in an embodiment of the invention is shown.
The method comprises the following steps:
step S11: and respectively interpreting and compiling state machine descriptions of the SFQ logic gate state machine, and obtaining compiling results.
Optionally, based on a preset customization algorithm of the SFQ logic, the state machine description of the SFQ logic gate state machine is respectively interpreted and compiled, and a compiling result conforming to the SFQ logic is obtained. Specifically, based on the synthesizable statement of the SFQ logic required by the preset SFQ sequential logic circuit, the state machine description of the SFQ logic gate state machine is respectively interpreted and compiled, and a compiling result is obtained; if the state machine description which does not accord with the SFQ logic appears, the exception is thrown in the semantic analysis stage, and the compiling program is terminated. Preferably, a custom compiler is adopted to respectively interpret and compile the state machine description of the SFQ logic gate state machine, and a compiling result is obtained. Wherein the custom compiler needs to specify synthesizable statements for SFQ timing circuits.
Alternatively, the state machine description of the SFQ logic gate state machine may be interpreted and compiled using MVEL or QLExpress, respectively, and the compilation result obtained.
Alternatively, the state machine description may employ Verilog language to enable adaptation to other logic blocks in terms of emulation functions and invoke a portion of the IEEE standard.
Step S12: and obtaining state transition set information corresponding to the SFQ logic gate state machine according to the compiling result.
Alternatively, for SFQ circuits, it is necessary to output the compiled result as state transition set information after interpretation and compilation, instead of standard boolean logic and timing components, due to the differences from CMOS circuits. The state transition set information includes: state transition information corresponding to each state.
Optionally, the state transition set information includes: state transition diagrams and/or state transition tables. Specifically, after interpretation and compiling, the compiling result is output as a state transition diagram and/or a state transition table.
Step S13: and decomposing the state transition set information to obtain sub-state transition set information respectively corresponding to one or more sub-state machines.
Optionally, performing one or more iterative decompositions on the state transition set information respectively based on a decomposition rule related to the unit gate information of the SFQ logic unit library until one or more sub-state transition set information which can not be decomposed any more is obtained; specifically, since the same state machine may have multiple combination conditions, a random variable needs to be introduced when the SFQ logic gate state machine is decomposed, one or more times of iterative decomposition is performed on the state transition set information based on a decomposition rule related to the unit gate information of the SFQ logic unit library, and sub-state transition set information of each decomposed sub-state machine is written into a list for storage until all the sub-state machines are not subdivided, so as to obtain one or more sub-state transition set information corresponding to each sub-state machine.
Optionally, the performing one or more iterative decomposition on the state transition set information based on a decomposition rule related to the type of the cell gate in the SFQ logic cell library until obtaining one or more sub-state transition set information that cannot be decomposed again includes; grouping the states in the state transition set information according to the state continuity thereof to obtain one or more state groups with state continuity relation; based on the lowest state number obtained by the cell gate information of the SFQ logic cell library, each state in each state group is sequentially distributed into each sub-state machine, and one or more sub-state transition set information which can not be decomposed is obtained, so that the situation that an error state cannot jump out is avoided.
It should be noted that, based on the type (state minimum requirement) of each cell gate in the cell gate information of the SFQ logic cell library as the minimum state number, each state in each state group is sequentially allocated to each sub-state machine, and one or more sub-state machines which ensure the minimum state number and maximum decomposition are obtained; for example, the minimum requirement for satisfying the cell state machines in the SFQ cell library is that the state number is equal to 2, i.e. the obtained sub-state machines at least include 2 states S0 and S1, as shown in fig. 2.
Step S14: and mapping the sub-state transition set information of each sub-state machine based on the unit gate information of the SFQ logic unit library, and obtaining the mapping result of each corresponding sub-state machine.
Optionally, mapping the sub-state transition set information of each sub-state machine with each unit gate in the SFQ logic unit library based on the unit gate information of the SFQ logic unit library, and obtaining a mapping result corresponding to each sub-state machine; wherein the mapping result includes: and a successful mapping result corresponding to the complete mapping success of the sub-state machines and/or a failure mapping result corresponding to the mapping failure of the sub-state machines.
Specifically, based on the information of each unit gate in the unit gate information of the SFQ logic unit library, sub-state transition set information of each sub-state machine is respectively matched with the information of each unit gate in the SFQ logic unit library, when a sub-state machine which cannot be successfully matched is generated, a failure mapping result corresponding to the mapping failure of the sub-state machine is obtained, an exception is required to be thrown out by a program, state machine transition information which cannot be matched is output, and matching is continued; and if all the matching is completed, obtaining a successful mapping result corresponding to all the mapping success of the sub-state machine, namely, performing the next step. For the last cell gate with incomplete matching, the user can design a new SFQ cell gate or modify the sequential circuit design according to the output failure mapping result.
Therefore, compared with the traditional synthesis method, the method can solve the problem that the traditional synthesis method can not realize complete matching of SFQ sequential logic to the unit gate, and the generated sequential circuit has a large number of loops and can not meet the normal working requirement after being converted into the SFQ circuit.
The application has obvious advantages in the aspect of the utilization rate of the SFQ logic unit library, the traditional method can not call special SFQ logic gates such as ndro, rs1n, jandf and the like, and can not realize the maximum utilization of the unit library, and the theoretical maximum utilization rate is 62.1 percent according to the analysis of the number of the logic gates of the existing unit library (29 unit gates in total and 11 unit gates can not be called by the traditional comprehensive algorithm); by adopting the SFQ sequential circuit comprehensive calculation method, the theoretical maximum utilization rate can be improved to 100%.
Optionally, for the existing SFQ unit gate, a designer needs to manually enter corresponding state transition information to form state transition set information, and store the state transition set information as a dedicated library file for the SFQ sequential logic circuit synthesis.
Step S15: and recombining each sub-state machine based on the mapping result of each corresponding sub-state machine to obtain the SFQ sequential logic circuit structure.
Optionally, the reorganizing each sub-state machine based on the mapping result corresponding to each sub-state machine to obtain the SFQ sequential logic circuit structure includes: obtaining unit gates mapped by each state machine corresponding to successful mapping results; and connecting the unit gates to obtain the SFQ sequential logic circuit structure. Specifically, based on successful mapping results of the state machines corresponding to the sub-state machines, unit gates mapped by the state machines corresponding to the successful mapping results are obtained; connecting the unit gates, recombining the unit gates into an SFQ sequential logic circuit, and obtaining a structure reflecting the SFQ sequential logic circuit; preferably, the structure is represented in a Verilog netlist.
Similar to the principles of the embodiments described above, the present invention provides an SFQ sequential circuit integrated computing system.
Specific embodiments are provided below with reference to the accompanying drawings:
FIG. 3 shows a schematic diagram of an SFQ sequential circuit integrated computing system in accordance with an embodiment of the present invention.
The system comprises:
the compiling module 31 is configured to interpret and compile state machine descriptions of the SFQ logic gate state machine, respectively, and obtain compiling results;
A state transition set information obtaining module 32, connected to the compiling module 31, for obtaining state transition set information corresponding to the SFQ logic gate state machine according to the compiling result;
The decomposition module 33 is connected with the state transition set information acquisition module 32 and is used for decomposing the state transition set information to obtain sub-state transition set information corresponding to one or more sub-state machines respectively;
The mapping module 34 is connected with the decomposition module 33, and is used for mapping the sub-state transition set information of each sub-state machine based on the unit gate information of the SFQ logic unit library and obtaining the mapping result of each corresponding sub-state machine;
And the reorganizing module 35 is connected to the mapping module 34, and is configured to reorganize each sub-state machine based on the mapping result corresponding to each sub-state machine, so as to obtain an SFQ sequential logic circuit structure.
It should be noted that, it should be understood that the division of the modules in the embodiment of the system of fig. 3 is merely a division of logic functions, and may be fully or partially integrated into a physical entity or may be physically separated. And these modules may all be implemented in software in the form of calls by the processing element; or can be realized in hardware; the method can also be realized in a mode that a part of modules are called by processing elements and software, and the part of modules are realized in a hardware mode;
For example, each module may be one or more integrated circuits configured to implement the above methods, e.g.: one or more Application SPECIFIC INTEGRATED Circuits (ASIC), or one or more microprocessors (DIGITAL SIGNAL processor, DSP), or one or more field programmable gate arrays (Field Programmable GATE ARRAY, FPGA), etc. For another example, when a module above is implemented in the form of a processing element scheduler code, the processing element may be a general-purpose processor, such as a central processing unit (Central Processing Unit, CPU) or other processor that may invoke the program code. For another example, the modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
Optionally, the compiling module 31 respectively interprets and compiles the state machine descriptions of the SFQ logic gate state machines based on a preset customization algorithm of the SFQ logic, and obtains a compiling result conforming to the SFQ logic. Specifically, the compiling module 31 respectively interprets and compiles the state machine description of the SFQ logic gate state machine based on the synthesizable statement of the SFQ logic required by the preset SFQ sequential logic circuit, and obtains the compiling result; if a state machine description which does not conform to the SFQ logic occurs, the compiling module 31 throws an exception at the semantic analysis stage and terminates the compiling program. Preferably, the compiling module 31 includes: and the custom compiler is used for respectively interpreting and compiling the state machine description of the SFQ logic gate state machine and obtaining a compiling result. Wherein the custom compiler needs to specify synthesizable statements for SFQ timing circuits.
Alternatively, the compiling module 31 may respectively interpret and compile the state machine descriptions of the SFQ logic gate state machine by using MVEL or QLExpress, and obtain the compiling result.
Optionally, the state transition set information obtaining module 32 needs to output the compiling result as state transition set information after interpretation and compiling. The state transition set information includes: state transition information corresponding to each state.
Optionally, the state transition set information includes: state transition diagrams and/or state transition tables. Specifically, the state transition set information obtaining module 32 is configured to output the compiling result as a state transition diagram and/or a state transition table after interpretation and compiling.
Optionally, the decomposing module 33 is configured to perform one or more iterative decompositions on the state transition set information respectively based on a decomposition rule related to the unit gate information of the SFQ logic unit library, until one or more sub-state transition set information that cannot be decomposed any more is obtained. Preferably, the decomposition module 33 is configured to group each state in the state transition set information according to its state continuity, so as to obtain one or more state groups with a state continuity relationship; based on the lowest state number obtained by the cell gate information of the SFQ logic cell library, each state in each state group is sequentially distributed into each sub-state machine, and one or more sub-state transition set information which can not be decomposed is obtained, so that the situation that an error state cannot jump out is avoided. Note that, the type (state minimum requirement) of each cell gate in the cell gate information of the SFQ logic cell library is taken as the minimum state number, and the decomposition module 33 sequentially allocates each state in each state group into each sub-state machine, and obtains one or more sub-state machines that guarantee the minimum state number and the maximum decomposition.
Optionally, the mapping module 34 is configured to map the sub-state transition set information of each sub-state machine with each cell gate in the SFQ logic cell library based on the cell gate information of the SFQ logic cell library, and obtain a mapping result corresponding to each sub-state machine; wherein the mapping result includes: and a successful mapping result corresponding to the complete mapping success of the sub-state machines and/or a failure mapping result corresponding to the mapping failure of the sub-state machines. For example, as shown in fig. 4, the mapping module invokes the logic unit gate DFFR and/or NDRO to implement the matching of the sub-state transition set information (including S0 and S1 states) of each sub-state machine with the information of each unit gate in the SFQ logic unit library based on the information of each unit gate in the unit gate information of the SFQ logic unit library, and when the matching fails, the program is required to throw out an exception, output a state machine transition table that cannot be matched, and continue the matching.
Optionally, the reorganizing module 35 is configured to obtain the unit gates mapped by each state machine corresponding to the successful mapping result, and connect each unit gate to obtain the SFQ sequential logic circuit structure. Specifically, the reorganization module 35 is configured to obtain, based on the successful mapping result of each sub-state machine, the cell gate mapped by each state machine corresponding to the successful mapping result; connecting the unit gates, recombining the unit gates into an SFQ sequential logic circuit, and obtaining a structure reflecting the SFQ sequential logic circuit; preferably, the structure is represented in a Verilog netlist.
In terms of circuit overhead, the conventional synthesis method cannot identify specific logic gates of SFQ, but cannot call the logic gates and map the logic gates into sequential logic, and only basic AND-NOR logic gates and triggers can be used for forming the sequential circuit, so that the area of a synthesis result can be increased; as shown in FIG. 5, the invention can invoke the SFQ specific logic gates DFFR and NDRO to optimize the circuit area.
Fig. 6 shows a schematic diagram of the structure of the SFQ sequential circuit general calculation terminal 60 in the embodiment of the present invention.
The SFQ sequential circuit integrated computation terminal 60 includes: a memory 61 and a processor 62, the memory 61 for storing a computer program; the processor 62 runs a computer program to implement the SFQ sequential circuit comprehensive calculation method as described in fig. 1.
Alternatively, the number of the memories 61 may be one or more, and the number of the processors 62 may be one or more, and one is taken as an example in fig. 6.
Optionally, the processor 62 in the SFQ timing circuit integrated computing terminal 60 loads one or more instructions corresponding to the process of the application program into the memory 61 according to the steps as described in fig. 1, and the processor 62 executes the application program stored in the first memory 61, thereby implementing various functions in the SFQ timing circuit integrated computing method as described in fig. 1.
Optionally, the memory 61 may include, but is not limited to, high speed random access memory, nonvolatile memory. Such as one or more disk storage devices, flash memory devices, or other non-volatile solid-state storage devices; the processor 62 may include, but is not limited to, a central processing unit (Central Processing Unit, CPU for short), a network processor (Network Processor, NP for short), etc.; but may also be a digital signal processor (DIGITAL SIGNAL Processing, DSP), application Specific Integrated Circuit (ASIC), field-Programmable gate array (FPGA) or other Programmable logic device, discrete gate or transistor logic device, discrete hardware components.
Alternatively, the processor 62 may be a general-purpose processor, including a central processing unit (Central Processing Unit, abbreviated as CPU), a network processor (Network Processor, abbreviated as NP), and the like; but may also be a digital signal processor (DIGITAL SIGNAL Processing, DSP), application Specific Integrated Circuit (ASIC), field-Programmable gate array (FPGA) or other Programmable logic device, discrete gate or transistor logic device, discrete hardware components.
The invention also provides a computer readable storage medium storing a computer program which when run implements the SFQ sequential circuit comprehensive calculation method as shown in figure 1. The computer-readable storage medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs (compact disk-read only memories), magneto-optical disks, ROMs (read-only memories), RAMs (random access memories), EPROMs (erasable programmable read only memories), EEPROMs (electrically erasable programmable read only memories), magnetic or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing machine-executable instructions. The computer readable storage medium may be an article of manufacture that is not accessed by a computer device or may be a component used by an accessed computer device.
In summary, the method, system and terminal for comprehensive computation of SFQ sequential circuit of the present invention are used for respectively explaining and compiling state machine descriptions of SFQ logic gate state machines to obtain state transition set information of the state machines, decomposing the state transition set information into one or more sub-state machines, mapping each sub-state machine with each unit gate in SFQ logic unit library, and recombining each sub-state machine based on mapping result of each sub-state machine to obtain SFQ sequential logic circuit structure. The invention utilizes the self advantages of the SFQ logic gate to directly complete the logic mapping from the SFQ logic gate state machine to the SFQ time sequence circuit, reduces two-step operation of simulating the CMOS logic gate in the middle and forming the CMOS time sequence state machine, improves the logic synthesis success rate of the SFQ time sequence circuit and the utilization rate of the SFQ unit library, ensures that the large-scale automatic design of the SFQ time sequence circuit is more efficient, and solves the problems in the prior art. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. It is therefore intended that all equivalent modifications and changes made by those skilled in the art without departing from the spirit and technical spirit of the present invention shall be covered by the appended claims.
Claims (10)
1. An SFQ sequential circuit comprehensive calculation method, comprising:
Interpreting and compiling state machine descriptions of the SFQ logic gate state machine respectively, and obtaining compiling results;
acquiring state transition set information corresponding to the SFQ logic gate state machine according to the compiling result;
Decomposing the state transition set information to obtain sub-state transition set information corresponding to one or more sub-state machines respectively;
Mapping the sub-state transition set information of each sub-state machine based on the unit gate information of the SFQ logic unit library, and obtaining a mapping result corresponding to each sub-state machine;
and recombining each sub-state machine based on the mapping result of each corresponding sub-state machine to obtain the SFQ sequential logic circuit structure.
2. The method of claim 1, wherein the interpreting and compiling the state machine descriptions of the SFQ logic gate state machines, respectively, and obtaining the compiling result comprises:
Based on a preset SFQ logic customization algorithm, state machine description of an SFQ logic gate state machine is respectively interpreted and compiled, and a compiling result conforming to the SFQ logic is obtained.
3. The method of claim 1, wherein decomposing the state transition set information to obtain sub-state transition set information corresponding to one or more sub-state machines respectively comprises:
And respectively carrying out one or more iterative decomposition on the state transition set information based on decomposition rules related to the unit gate information of the SFQ logic unit library until one or more sub-state transition set information which cannot be decomposed any more is obtained.
4. The SFQ sequential circuit comprehensive computation method of claim 3, wherein said performing one or more iterative decompositions on said state transition set information based on decomposition rules related to types of cell gates in the SFQ logic cell library, respectively, until obtaining one or more sub-state transition set information that is not resolvable comprises:
grouping each state in the state transition set information to obtain one or more state groups with state continuity relation;
Each state in each state group is allocated to each sub-state machine in turn based on the lowest state number obtained by the cell gate information of the SFQ logic cell library, and one or more sub-state transition set information is obtained which is not resolvable.
5. The method of claim 1, wherein the mapping the sub-state transition set information of each sub-state machine based on the cell gate information of the SFQ logic cell library, and obtaining the mapping result of each sub-state machine comprises:
Mapping the sub-state transition set information of each sub-state machine with each unit gate in the SFQ logic unit library based on the unit gate information of the SFQ logic unit library, and obtaining a mapping result of each corresponding sub-state machine; wherein the mapping result includes: and a successful mapping result corresponding to the complete mapping success of the sub-state machines and/or a failure mapping result corresponding to the mapping failure of the sub-state machines.
6. The method of claim 5, wherein reorganizing each sub-state machine based on the mapping result of each corresponding sub-state machine to obtain the SFQ sequential logic circuit structure comprises:
obtaining unit gates mapped by each state machine corresponding to successful mapping results;
And connecting the unit gates to obtain the SFQ sequential logic circuit structure.
7. The SFQ sequential circuit comprehensive computation method of claim 1, wherein said state transition set information comprises: state transition diagrams and/or state transition tables.
8. The method of integrated computation of SFQ timing circuits of claim 1, wherein said state machine description is in Verilog language.
9. An SFQ sequential circuit comprehensive computing system, the system comprising:
The compiling module is used for respectively interpreting and compiling the state machine description of the SFQ logic gate state machine and obtaining a compiling result;
the state transition set information acquisition module is connected with the compiling module and is used for acquiring state transition set information corresponding to the SFQ logic gate state machine according to the compiling result;
The decomposition module is connected with the state transition set information acquisition module and is used for decomposing the state transition set information to obtain sub-state transition set information corresponding to one or more sub-state machines respectively;
the mapping module is connected with the decomposition module and is used for mapping the sub-state transition set information of each sub-state machine based on the unit gate information of the SFQ logic unit library and obtaining the mapping result of each corresponding sub-state machine;
And the reorganization module is connected with the mapping module and used for reorganizing each sub-state machine based on the mapping result corresponding to each sub-state machine so as to obtain the SFQ sequential logic circuit structure.
10. An SFQ sequential circuit complex computing terminal, comprising:
A memory for storing a computer program;
a processor for performing the SFQ sequential circuit complex computation method of any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110500919.7A CN113095015B (en) | 2021-05-08 | 2021-05-08 | SFQ time sequence circuit comprehensive calculation method, system and terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110500919.7A CN113095015B (en) | 2021-05-08 | 2021-05-08 | SFQ time sequence circuit comprehensive calculation method, system and terminal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113095015A CN113095015A (en) | 2021-07-09 |
| CN113095015B true CN113095015B (en) | 2024-05-24 |
Family
ID=76664650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110500919.7A Active CN113095015B (en) | 2021-05-08 | 2021-05-08 | SFQ time sequence circuit comprehensive calculation method, system and terminal |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113095015B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113627120B (en) * | 2021-09-17 | 2023-09-12 | 中国科学院上海微系统与信息技术研究所 | Superconducting integrated circuit layout optimization method and device, storage medium and terminal |
| CN113779924B (en) * | 2021-09-17 | 2023-09-12 | 中国科学院上海微系统与信息技术研究所 | Wiring optimizing method and device for superconducting integrated circuit, storage medium and terminal |
| CN118070719A (en) * | 2024-04-10 | 2024-05-24 | 中国人民解放军国防科技大学 | Memory logic comprehensive mapping method and system based on multiple memristive state logic gates |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1133534A (en) * | 1994-03-24 | 1996-10-16 | Dva公司 | Detector for initial code |
| JP2004070658A (en) * | 2002-08-06 | 2004-03-04 | Fujitsu Peripherals Ltd | Logic circuit simulation method and computer-readable storage medium |
| CN1985256A (en) * | 2004-06-30 | 2007-06-20 | 相干逻辑公司 | Execution of hardware description language (HDL) programs |
| CN110121747A (en) * | 2016-10-28 | 2019-08-13 | 伊鲁米那股份有限公司 | For executing the bioinformatics system, apparatus and method of second level and/or tertiary treatment |
| CN110268382A (en) * | 2017-02-06 | 2019-09-20 | 微软技术许可有限责任公司 | With the superconductive device for strengthening directionality |
| CN112561057A (en) * | 2020-12-09 | 2021-03-26 | 清华大学 | State control method and device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6904576B2 (en) * | 2002-08-09 | 2005-06-07 | Synplicity, Inc. | Method and system for debugging using replicated logic |
| US9552862B2 (en) * | 2014-07-29 | 2017-01-24 | Raytheon Bbn Technologies Corp. | Magnetic ram array architecture |
-
2021
- 2021-05-08 CN CN202110500919.7A patent/CN113095015B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1133534A (en) * | 1994-03-24 | 1996-10-16 | Dva公司 | Detector for initial code |
| JP2004070658A (en) * | 2002-08-06 | 2004-03-04 | Fujitsu Peripherals Ltd | Logic circuit simulation method and computer-readable storage medium |
| CN1985256A (en) * | 2004-06-30 | 2007-06-20 | 相干逻辑公司 | Execution of hardware description language (HDL) programs |
| CN110121747A (en) * | 2016-10-28 | 2019-08-13 | 伊鲁米那股份有限公司 | For executing the bioinformatics system, apparatus and method of second level and/or tertiary treatment |
| CN110268382A (en) * | 2017-02-06 | 2019-09-20 | 微软技术许可有限责任公司 | With the superconductive device for strengthening directionality |
| CN112561057A (en) * | 2020-12-09 | 2021-03-26 | 清华大学 | State control method and device |
Non-Patent Citations (3)
| Title |
|---|
| Automated State Machine and Timing Characteristic Extraction for RSFQ Circuits;Louis C.muller et al.;《IEEE Transactions on Applied Superconductivity》;20140228;第24卷(第1期);1-10 * |
| 可综合的基于Verilog语言的有限状态机的设计;刘德贵 等;《现代电子技术》;20051001(第10期);124-126 * |
| 超导约瑟夫逊传输线初步研究;张建 等;《低温与超导》;20011123(第04期);18-23 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113095015A (en) | 2021-07-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113095015B (en) | SFQ time sequence circuit comprehensive calculation method, system and terminal | |
| Hur et al. | SIMPLE MAGIC: Synthesis and in-memory mapping of logic execution for memristor-aided logic | |
| Mailhot et al. | Algorithms for technology mapping based on binary decision diagrams and on Boolean operations | |
| US5956257A (en) | Automated optimization of hierarchical netlists | |
| CN113705135B (en) | Circuit structure optimization method and system based on FPGA carry chain | |
| Burns | Automated compilation of concurrent programs into self-timed circuits | |
| Chou et al. | Circuit partitioning for huge logic emulation systems | |
| Zhong et al. | Using reconfigurable computing techniques to accelerate problems in the CAD domain: a case study with Boolean satisfiability | |
| Hulgaard et al. | Equivalence checking of combinational circuits using boolean expression diagrams | |
| CN113779924A (en) | Method and apparatus for optimizing wiring of superconducting integrated circuit, storage medium, and terminal | |
| CN105447285B (en) | A method of improving OpenCL hardware execution efficiency | |
| CN111858463B (en) | Optimal reconfiguration method based on DVFS | |
| Ishida | An optimization algorithm for production systems | |
| Cheng et al. | Circuit partitioning with logic perturbation | |
| Aravena | Recursive moving window DFT algorithm | |
| Bolchini et al. | A novel methodology for designing TSC networks based on the parity bit code | |
| Cai et al. | IDE development, logic synthesis and buffer/splitter insertion framework for adiabatic quantum-flux-parametron superconducting circuits | |
| Ma et al. | Parallel exact inference on multicore using mapreduce | |
| Hudson et al. | Spatiotemporal partitioning of computational structures onto configurable computing machines | |
| CN100428161C (en) | Automatic layout method for storage sub-system internal storage of embedded microprocessor | |
| Nam et al. | A boolean satisfiability-based incremental rerouting approach with application to FPGAs | |
| Chen et al. | JRouter: A multi-terminal hierarchical length-matching router under planar Manhattan routing model for RSFQ circuits | |
| JP2009544091A (en) | Electronic circuit synthesis | |
| De Micheli | Technology mapping of digital circuits | |
| US20050039150A1 (en) | Process and device for circuit design by means of high-level synthesis |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |