CN115048892A - IO module layout method based on module connection relation of FPGA - Google Patents

Abstract

The present application discloses an IO module layout method based on a module connection relationship of an FPGA, which relates to the technical field of FPGA. The integrated circuit performance of each group of signal connection relationships between each predetermined functional module connected to it is optimal, and the method starts from the perspective of optimizing the performance of the integrated circuit, by inputting the connection information of the functional module provided by the user in the netlist, and The pre-fixed layout positions of the predetermined function modules are used to assist the layout, which can avoid the problems caused by the conventional random layout, thereby making the subsequent global layout quality better.

Description

IO module layout method based on module connection relationship in FPGA

technical field

The present application relates to the technical field of FPGA, in particular to an IO module layout method based on a module connection relationship of an FPGA.

Background technique

Field-Programmable Gate Array (FPGA) is a chip that is widely used in household appliances, large machinery and even aerospace. The use of FPGA chips is inseparable from Electronic Design Automation (EDA) tools. Layout is an important part of the EDA tool, which has a great impact on the running speed of the EDA tool itself and the final quality of the circuit processed. In recent years, the circuit scale of FPGA chips has grown rapidly, making them more powerful, but at the same time, it has also brought challenges to the corresponding EDA tools.

The main function of the layout is to map the instances in the user netlist to the layout positions of the FPGA chip with actual physical coordinates under the optimization goal. The analytical layout algorithm can quickly obtain the global optimal solution using mathematical methods. It has become one of the mainstream directions of today's layout algorithms.

In the force-directed analytical layout algorithm, the traditional method is to layout the IO module first, and then use the fixed IO as the traction point to expand other modules on the FPGA chip. The layout position of the IO module has a great influence on the subsequent layout quality and timing. However, there are many IO modules in the FPGA, and it is difficult for the user to specify the layout position of all the IO modules. A small part of the IO modules are laid out by the user, and the rest of the IO modules are automatically laid out by the development software. Generally, the IO modules are randomly laid out to random positions according to a certain capacity rule, but this random layout method is very difficult. It is difficult to guarantee the quality of the layout.

Application content

Aiming at the problem that the existing random layout method of the IO module in the FPGA is difficult to guarantee the layout quality, the applicant proposes an IO module layout method based on the module connection relationship in the FPGA. The technical solution of the application is as follows:

An IO module layout method based on a module connection relationship of an FPGA, the method comprising:

Obtain the user input netlist corresponding to the FPGA chip, and determine the layout positions of several predetermined function modules in the user input netlist;

Determine the IO modules to be distributed that are connected to the predetermined function modules and are not laid out in the user input netlist;

For each IO module to be deployed, the IO layout position of the IO module to be deployed is determined based on the layout position of each predetermined function module connected to the IO module to be deployed, and the IO module to be deployed is connected to each predetermined IO layout position when the IO module to be deployed is determined. The comprehensive circuit performance of each group of signal connection relationships between functional modules is optimal;

Complete the placement of the remaining IO blocks that are not placed in the user input netlist.

Its further technical scheme is that the FPGA chip includes several banks, and each bank includes several IO layout positions; then the IO layout positions of the IO modules to be distributed are determined based on the layout positions of the respective predetermined function modules connected to the IO modules to be distributed. ,include:

One bank in the FPGA chip is determined as the target bank based on the layout position of each predetermined function module connected to the IO module to be deployed. The performance of the integrated circuit is the best;

According to the resource constraints in the target bank, an IO layout position is selected as the IO layout position of the IO module to be deployed.

Its further technical solution is that the method for determining the target BANK includes:

The BANK with the largest number of reference functional modules contained in the corresponding layout area in the FPGA chip is taken as the target BANK, and the reference functional module is a predetermined functional module that has a direct signal connection relationship with the IO module to be deployed.

Its further technical solution is that the method for determining the target BANK includes:

The BANK with the highest timing criticality of the corresponding region in the FPGA chip is used as the target bank; among them, the regional timing criticality corresponding to a BANK is the optimal path timing criticality of all predetermined functional modules whose layout positions are in the layout region corresponding to the BANK. value, or the timing score value obtained according to the timing scoring method according to the path timing criticality corresponding to all predetermined functional modules;

The timing criticality of the path of each predetermined functional module is the timing criticality of the timing path where the signal connection relationship between the predetermined functional module and the IO module to be deployed is located.

Its further technical solution is that the method for determining the target BANK includes:

According to the path timing criticality of all predetermined functional modules contained in the layout area corresponding to a BANK, the timing score value of the BANK is obtained according to the timing scoring method; The number of predetermined functional modules of the direct signal connection relationship obtains the connectivity score of BANK;

Use the BANK with the highest total score based on the timing score and the connectivity score as the target BANK;

The timing criticality of the path corresponding to each predetermined functional module is the timing criticality of the timing path where the signal connection relationship between the predetermined functional module and the IO module to be deployed is located.

Its further technical solution is that the time series scoring method includes:

For each predetermined function module included in the layout area corresponding to a bank, if the path timing criticality of the predetermined function module reaches the criticality threshold, the time sequence score value of the predetermined score is accumulated for the bank, and the accumulated predetermined score value for each time are equal or there are at least two accumulated predetermined scores that differ.

Its further technical solution is that when the path timing criticality reaches the criticality threshold, the predetermined score to be accumulated this time is determined according to the path timing criticality of the predetermined functional module. The higher the score.

A further technical solution is that the total score value of a bank is obtained by weighting the corresponding time series score value and the connectivity score value, and the weights of the time series score value and the connectivity score value are equal or unequal.

A further technical solution thereof is that when the total score is obtained by weighting, the weight of the time series score is higher than the weight of the connectivity score.

Its further technical solution is to complete the layout of the remaining IO modules that are not laid out in the user input netlist, including:

Based on the pulling action of all IO modules whose IO layout positions have been determined and the predetermined function modules whose layout positions have been determined, perform force-oriented analytical layout on the FPGA chip according to the user input netlist to obtain the initial layout result;

For each remaining IO module, the IO layout position of the remaining IO module is determined based on the layout position of each functional module connected to the remaining IO module in the initial layout result, and the remaining IO modules are connected to each function when the obtained IO layout position is determined. The comprehensive circuit performance of each group of signal connection relationships between modules is optimal.

A further technical solution is that the number of predetermined function modules included in the user input netlist does not exceed a first number threshold, and the number of deployable positions of each predetermined function module on the FPGA chip does not exceed a second number threshold.

Its further technical solution is that the predetermined functional module includes at least one of IO module, IOLGIC module, IODELAY module, GTH module, CMT module, BUFG module, MMCM module, DPLL module, XPLL module, PCIE module and EMAC module.

The beneficial technical effects of the present application are:

The present application discloses an IO module layout method based on a module connection relationship in an FPGA. From the perspective of optimizing the performance of the integrated circuit, the method is based on the connection information of the functional modules provided by the user input netlist, and the pre-fixed predetermined functions. The layout position of the module is used to assist in deriving the IO layout position of the IO module and complete the layout of the IO module. Since the comprehensive circuit performance is considered during the layout of the IO module, the problems caused by the conventional random layout can be avoided, so that the quality of the subsequent global layout is better.

In the process of IO module layout considering the comprehensive circuit performance, the connectivity performance and/or timing performance can be considered according to the actual situation, and the weights of these two performances can be set according to the situation, so that a certain performance can be emphasized. , which can meet the circuit performance requirements in different scenarios.

Description of drawings

FIG. 1 is a schematic flowchart of an IO module layout method in one embodiment.

FIG. 2 is a schematic flowchart of an IO module layout method in another embodiment.

FIG. 3 is a schematic flowchart of an IO module layout method in yet another embodiment.

Detailed ways

The specific embodiments of the present application will be further described below with reference to the accompanying drawings.

The present application discloses an IO module layout method based on a module connection relationship of an FPGA. The method includes the following steps, please refer to the flowchart shown in FIG. 1 :

Step 100: Obtain a user input netlist corresponding to the FPGA chip, and determine the layout positions of several predetermined function modules in the user input netlist.

Theoretically, the predetermined function module can be any function module in the user input netlist, and the layout position of these predetermined function modules can be determined by user designation. However, in fact, if the predetermined function modules are some too conventional function modules, such as CLB modules, because of the large number of these function modules and the large number of positions that can be placed on the FPGA chip, it is difficult for users to specify their layout positions. The layout position specified by the user may not be the preferred layout result. The module connection relationship of these functional modules may not guide the layout of the IO module well in the future, which may lead to the final layout quality cannot be guaranteed.

Therefore, in one embodiment, the number of predetermined function modules included in the user input netlist does not exceed the first number threshold, and the number of deployable positions of each predetermined function module on the FPGA chip does not exceed the second number threshold. That is to say, the predetermined function modules are usually some special function modules in the user input netlist that are small in number and can be placed in fewer positions. The number of these predetermined function modules will not be too large, so the difficulty and workload of determining their layout positions will not be too large, and the operability is high. In addition, the arrangable positions of these predetermined functional modules are relatively limited, and some predetermined functional modules may have and only one arrangable position. Therefore, it is relatively difficult to determine the layout positions of these predetermined functional modules, and generally the determined layout positions are all The layout position that is more in line with the final layout result. In addition, many special functional modules exist in the form of IP, so they also have peripheral logic. When the software supports IP, the IP is generally mapped to the FPGA chip first, and the appropriate layout area is determined. The layout position of the predetermined functional module is can be determined.

Based on this principle, in one embodiment, the predetermined functional modules include at least one of an IO module, an IOLGIC module, an IODELAY module, a GTH module, a CMT module, a BUFG module, an MMCM module, a DPLL module, an XPLL module, a PCIE module, and an EMAC module. A sort of. The IO module here refers to some IO modules arranged by the user.

For each predetermined function module, when determining the layout position of the predetermined function module, there are mainly two methods: one method is to use the layout position specified by the user as the layout position of the predetermined function module. Another method is to determine the layout positions of other predetermined function modules based on the predetermined function modules whose layout positions have been determined. For example, the user first specifies the layout positions of some IO modules, and then uses other predetermined function modules to communicate with these already laid out IO modules. The connection relationship between them is used to lay out other predetermined function modules. In practice these two methods can be mixed.

Step 200: Determine the IO modules to be deployed that are connected to the predetermined function modules and are not laid out in the user input netlist. That is, the connection ports of each predetermined function module are traversed in a loop, and the IO modules that are connected to them and not laid out are found as the IO modules to be deployed.

Step 300, for each IO module to be deployed, determine the IO layout position of the IO module to be deployed based on the layout positions of each predetermined function module connected to the IO module to be deployed. When the IO module to be deployed is determined at the obtained IO layout position, the comprehensive circuit performance of each group of signal connection relationships between each predetermined function module connected to it is optimal.

Step 400: Complete the layout of the remaining IO modules that are not laid out in the user input netlist.

In the above step 300, since the IO modules are too small, numerous in number and complicated in connection relationship, it is difficult and computationally expensive to directly determine the IO layout position that optimizes the performance of the integrated circuit. Considering that a large number of IO layout positions in FPGA chips often exist in the form of banks, each bank includes several IO layout positions, and each bank determines IO characteristics such as voltage, single and dual ports, and high and low speeds. Therefore, in one embodiment, the above step 300 determines the final IO layout position through two-layer progressive operations, please refer to the flowchart shown in FIG. 2:

Step 310: Determine a BANK in the FPGA chip as a target BANK based on the layout positions of each predetermined function module connected to the IO module to be deployed.

It is determined that when the obtained IO module to be deployed is in the target bank, the comprehensive circuit performance of each group of signal connection relationships between each predetermined function module connected to it is optimal, that is, the first layer of operation is firstly based on the bank, and the first layer operation starts from numerous Filter out the target bank where the IO layout position of the IO module to be deployed is located.

The comprehensive circuit performance needs to be considered when selecting the target bank. The comprehensive circuit performance can be various important performances in the field of FPGA design. In this application, the two most commonly considered performances in the FPGA design process are mainly considered: connectivity performance and / or timing performance, there are three main ways to determine the target BANK:

(1) The first case: only the connectivity performance is considered.

In this case, the BANK with the largest number of reference function modules contained in the corresponding layout area in the FPGA chip is used as the target BANK. The reference function module is a predetermined function module that has a direct signal connection relationship with the IO module to be deployed. That is to say, priority is given to BANKs with more direct connections that make the connectivity performance the best.

For each IO module to be deployed, it may be connected to one predetermined function module, or may be connected to multiple predetermined function modules. The to-be-distributed IO module may be directly connected to each predetermined function module to which it is connected, or may be indirectly connected. In this embodiment, the predetermined function module directly connected to the to-be-distributed IO module is defined as a reference function module.

There are multiple different layout regions (Regions) in the FPGA chip. After the layout positions of the predetermined function modules are determined, the layout regions where each predetermined function module is located can be determined. Each layout area has a corresponding bank, and the corresponding relationship is predetermined and fixed. It is common that a layout area may correspond to a bank. Therefore, after obtaining the layout positions of each predetermined function module, the number of the predetermined function modules contained in each layout area can be obtained by statistics. For a to-be-distributed IO module, the number of reference function modules corresponding to the to-be-distributed IO module contained in each layout area can also be obtained by statistics, that is, the number of reference function modules contained in the layout areas corresponding to different banks can be determined. , the BANK with the largest number of reference function modules contained therein is used as the target BANK. If the layout areas corresponding to multiple banks contain the largest and equal number of reference function modules, select one of them as the target bank.

For example, in an example, an IO module to be deployed is connected to 6 predetermined function modules, which are respectively recorded as A, B, C, D, E, and F. Among them, F is not directly connected to the IO module to be deployed, and the other 5 predetermined function modules are The reference function modules formed by being directly connected with the IO modules to be distributed. A, B, and C are located in layout area 1, and D and E are located in layout area 2. Layout area 1 corresponds to BANK1, and layout area 2 corresponds to BANK2. In this example, BANK1 is finally selected as the target BANK.

(2) The second case: only the timing performance is considered.

In this case, the BANK with the highest timing criticality in the corresponding region in the FPGA chip is used as the target BANK, that is, the BANK that makes the timing optimal is given priority. The correspondence between the predetermined function module, the bank, and the layout area is as described in the first case above, which is not repeated in this embodiment.

The timing criticality of a region corresponding to a bank is determined based on the timing criticality of a path of a predetermined function module whose layout position is in the layout region corresponding to the bank. The timing criticality of the path corresponding to each predetermined functional module is the timing criticality of the timing path where the signal connection relationship between the predetermined functional module and the IO module to be deployed is located. The timing criticality of the timing path can be measured by the slack value.

Based on the path timing criticality of a predetermined functional module whose layout position is in a layout area, there are many situations in which the corresponding regional timing criticality of the bank is determined: (1) The path timing criticality corresponding to all predetermined functional modules in the layout area The optimal value is directly used as the regional timing criticality of BANK. (2) According to the timing criticality of the paths corresponding to all the predetermined functional modules, the timing scoring value is obtained according to the timing scoring method, and the obtained timing scoring value is used as the regional timing criticality of the BANK.

In one embodiment, the timing scoring method is: for each predetermined functional module included in the layout area corresponding to a BANK, if the path timing criticality of the predetermined functional module reaches a criticality threshold, then add a predetermined score to the BANK The time-series score value is equal, the predetermined score value accumulated each time is the same, or there are at least two accumulated predetermined score values that are different.

For example, in an example, the predetermined score accumulated each time is equal to 2 as an example, it is assumed that the layout area corresponding to a bank contains three predetermined function modules, and the path timing criticality corresponding to the two predetermined function modules is equal to If the criticality threshold is reached, but the timing criticality of the path corresponding to another predetermined functional module does not reach the criticality threshold, the timing score of the BANK is obtained by two accumulations of 4 points.

If there are at least two different accumulated predetermined scores, then one situation is: (1) Determine the current accumulated predetermined score according to the module type of the predetermined function module, and the different types of predetermined function modules also reach the path timing criticality. In the case of the criticality threshold, the accumulated predetermined scores are different, and the specific corresponding relationship can be correspondingly configured in advance. Another situation is: (2) Determine the accumulated predetermined score this time according to the path timing criticality of the predetermined functional module, the higher the path timing criticality of the predetermined functional module, the greater the accumulated predetermined score.

(3) The third case: consider both timing performance and connectivity performance.

According to the path timing criticality of all predetermined functional modules contained in the layout area corresponding to a BANK, the timing score value of the BANK is obtained according to the timing scoring method; The number of predetermined functional modules with direct signal connection relationship obtains the connectivity score of BANK.

In the third case, the method for obtaining the timing score value is similar to the above-mentioned second case, and there are various implementation manners, which will not be described in detail in this embodiment. The part that obtains the score value of connectivity is to determine the predetermined functional modules included in the layout area corresponding to each bank that have a direct signal connection relationship with the IO modules to be deployed, that is, the method of referring to the number of functional modules is the same as the above-mentioned first method. The situation is similar, except that in this embodiment, instead of directly taking the BANK with the largest number of reference functional modules as in the first case, the connectivity score of each BANK is obtained according to the number of reference functional modules, and the result is The specific method of the connectivity score is the same as the sequence score, and there are multiple scoring methods. This embodiment provides the following methods: (1) The connectivity score of a BANK and the layout area corresponding to the BANK contain The number of reference functional modules is positively correlated, and the connectivity score is obtained by accumulating the score of each reference functional module. The more the number of reference functional modules included, the greater the connectivity score of the BANK. Similar to the timing score, the score for each reference functional block can be the same or different. An implementation manner is that the scores of two reference function modules with different module types are different and can be preset. Certainly. In this scoring method, an example is used to illustrate that, assuming that the score of each reference function module is the same as 2 points, then when a layout area corresponding to the bank contains 4 reference function modules, the bank's The connectivity score is 8 points. (2) When the number of reference function modules contained in the layout area corresponding to BANK exceeds the predetermined number threshold, record the pre-set connectivity score for BANK; In this way, all BANKs whose number of included reference functional modules exceeds the predetermined number threshold have the same connectivity score. For example, the connectivity score of a bank with more than 2 reference functional modules contained in the corresponding layout area is 1 point, and the connectivity score of a bank with no more than 2 is recorded as 0 score.

The BANK with the highest total score based on the time series score and the connectivity score is used as the target BANK. The total score value of a BANK is obtained by weighting the corresponding time series score value and connectivity score value, and the weights of the time series score value and the connectivity score value are equal or unequal. More commonly, considering that timing is more important to the FPGA layout, when the total score is obtained by weighting, the weight of the timing score is higher than the weight of the connectivity score.

Step 320, select an IO layout position as the IO layout position of the IO module to be deployed according to the resource constraints in the target bank, that is, after obtaining the target bank, perform the second layer operation and finally filter out the final IO layout position. The IO module to be deployed has its own characteristic requirements, such as the characteristic requirements for voltage, high and low speed, and the type of signal transmitted by the IO module to be deployed also determines its characteristic requirements. Each BANK also has its own resource constraints. The total number of IO layout locations contained in a BANK is limited, and the number of IO layout locations that meet the corresponding feature requirements is even less. For example, there are only a few specific IO layouts in a BANK. The position can be used to place the IO modules coming in with clock signals. Once these IO layout positions are occupied, IO modules with incoming clock signals cannot be placed. Therefore, the final IO layout position needs to be determined according to the resource constraints in the target bank.

When there is at least one IO layout position in the target bank that meets the characteristic requirements of the IO module to be deployed, select one of them as the IO layout position of the IO module to be deployed. When there is no IO layout position in the target bank that meets the characteristic requirements of the IO modules to be deployed, return to step 310, and re-determine the target bank in the order that the performance of the integrated circuit is from best to lowest, that is, in the second loop, make The BANK with the sub-optimal performance of the integrated circuit is used as the target BANK until the IO layout position of the IO module to be distributed is finally obtained.

In the above step 400, for the remaining IO modules, one method is to randomly arrange the remaining IO modules on the vacant IO layout positions on the FPGA chip. However, the placement of the IO modules has a great impact on the subsequent layout quality and timing, and random layout should be avoided as much as possible. Therefore, in one embodiment, the layout method for the remaining IO modules includes the following steps, please refer to Figure 3:

Step 410: Based on the pulling action of all the IO modules whose IO layout positions have been determined and the predetermined function modules whose layout positions have been determined, perform a force-oriented analytical layout on the FPGA chip according to the user-input netlist to obtain an initial layout result. In this step, you can: The force-directed analytical layout is iteratively solved several times according to actual needs.

Step 420, for each remaining IO module, determine the IO layout position of the remaining IO modules based on the layout positions of the respective functional modules connected to the remaining IO modules in the initial layout result, so that the remaining IO modules can match the IO layout position obtained when the remaining IO modules are determined. The comprehensive circuit performance of each group of signal connection relationships between the connected functional modules is optimal. The specific implementation of this step is similar to the layout method for determining the IO layout position of the IO module to be deployed in the above step 300, and details are not repeated in this embodiment.

Claims (12)

1. An IO module layout method based on module connection relation of FPGA is characterized by comprising the following steps:

acquiring a user input netlist corresponding to an FPGA chip, and determining the layout positions of a plurality of preset functional modules in the user input netlist;

determining an IO module to be distributed which is connected with a preset function module and is not distributed in the user input netlist;

for each IO module to be distributed, determining the IO layout position of each preset function module connected with the IO module to be distributed based on the layout position of each preset function module connected with the IO module to be distributed, wherein the comprehensive circuit performance of each group of signal connection relations between the IO module to be distributed and each preset function module connected with the IO module to be distributed is optimal when the IO module to be distributed is at the determined IO layout position;

and finishing layout on the residual IO modules which are not laid out in the user input netlist.

2. The method of claim 1, wherein the FPGA chip includes a plurality of BANKs, each BANK including a plurality of IO layout locations therein; determining the IO layout position of the IO module to be distributed based on the layout positions of the predetermined function modules connected to the IO module to be distributed, including:

determining one BANK in the FPGA chip as a target BANK based on the layout position of each preset functional module connected with the IO module to be distributed, wherein the comprehensive circuit performance of each group of signal connection relations between the IO module to be distributed and each preset functional module connected with the IO module to be distributed is optimal when the IO module to be distributed is in the target BANK;

and selecting an IO layout position from the target BANK as the IO layout position of the IO module to be distributed according to the resource constraint condition.

3. The method of claim 2, wherein determining the target BANK comprises:

and taking the BANK with the largest number of reference functional modules contained in the corresponding layout area in the FPGA chip as the target BANK, wherein the reference functional module is a preset functional module which has a direct signal connection relation with the IO module to be distributed.

4. The method of claim 2, wherein determining the target BANK comprises:

taking the BANK with the highest corresponding regional time sequence criticality in the FPGA chip as the target BANK; the method comprises the following steps that a regional time sequence criticality corresponding to a BANK is the optimal value of the path time sequence criticality of all preset functional modules of which the layout positions are in a layout region corresponding to the BANK, or a time sequence scoring value obtained according to the path time sequence criticality corresponding to all the preset functional modules and a time sequence scoring method;

the route time sequence criticality of each preset function module is the time sequence criticality of a time sequence route where the signal connection relation between the preset function module and the IO module to be distributed is located.

5. The method of claim 2, wherein determining the target BANK comprises:

obtaining a timing sequence scoring value of a BANK according to a timing sequence scoring method according to the path timing sequence criticality of all preset functional modules contained in a layout area corresponding to the BANK; obtaining the connection degree score of the BANK according to the number of preset functional modules which are contained in a layout area corresponding to the BANK and have direct signal connection relation with the IO modules to be distributed;

taking the BANK with the highest total score obtained based on the time sequence score and the connection score as the target BANK;

the route time sequence criticality corresponding to each preset function module is the time sequence criticality of a time sequence route where the signal connection relation between the preset function module and the IO module to be distributed is located.

6. The method of claim 4 or 5, wherein the time sequence scoring method comprises:

for each preset functional module contained in a layout area corresponding to a BANK, if the path time sequence criticality of the preset functional module reaches a criticality threshold, accumulating time sequence scores of preset scores for the BANK, wherein the preset scores accumulated each time are equal or the preset scores accumulated at least twice are different.

7. The method according to claim 6, wherein when the path timing criticality reaches a criticality threshold, the predetermined score accumulated this time is determined according to the path timing criticality of the predetermined functional module, and the higher the path timing criticality of the predetermined functional module is, the larger the accumulated predetermined score is.

8. The method of claim 5, wherein the total score of a BANK is weighted by the corresponding time series score and the connectivities score, and the time series score and the connectivities score are weighted equally or unequally.

9. The method of claim 8, wherein the time-series score value is weighted higher than the connection score value when the total score value is weighted.

10. The method of claim 1, wherein said completing placement of remaining IO modules not placed in said user input netlist comprises:

based on the traction action of all IO modules with determined IO layout positions and predetermined function modules with determined layout positions, performing force-oriented analytical layout on the FPGA chip according to the user input netlist to obtain an initial layout result;

and for each residual IO module, determining the IO layout position of the residual IO module based on the layout position of each functional module connected with the residual IO module in the initial layout result, wherein the comprehensive circuit performance of each group of signal connection relations between the residual IO module and each functional module connected with the residual IO module is optimal when the residual IO module is at the determined IO layout position.

11. The method of claim 1, wherein the number of predetermined functional modules included in the user input netlist does not exceed a first number threshold, and the number of routable locations of each predetermined functional module on the FPGA chip does not exceed a second number threshold.

12. The method of claim 11, wherein the predetermined function module comprises at least one of an IO module, an IOLGIC module, an IODELAY module, a GTH module, a CMT module, a BUFG module, an MMCM module, a DPLL module, an XPLL module, a PCIE module, and an EMAC module.

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