CN115048892A - IO module layout method based on module connection relation of FPGA - Google Patents

IO module layout method based on module connection relation of FPGA Download PDF

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CN115048892A
CN115048892A CN202210723992.5A CN202210723992A CN115048892A CN 115048892 A CN115048892 A CN 115048892A CN 202210723992 A CN202210723992 A CN 202210723992A CN 115048892 A CN115048892 A CN 115048892A
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module
layout
bank
distributed
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单悦尔
惠锋
张艳飞
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Wuxi Zhongwei Yixin Co Ltd
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Wuxi Zhongwei Yixin Co Ltd
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    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/347—Physical level, e.g. placement or routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

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Abstract

The utility model discloses an FPGA IO module layout method based on module connection relation, which relates to the FPGA technical field, and the method determines the IO layout position of the IO module to be distributed based on the layout position of each preset function module connected with the IO module to be distributed, so that the comprehensive circuit performance of each group of signal connection relation between each preset function module connected with the IO module to be distributed is optimal.

Description

IO module layout method based on module connection relation of FPGA
Technical Field
The application relates to the technical field of FPGA, in particular to an IO module layout method based on module connection relation of FPGA.
Background
A Field-Programmable Gate Array (FPGA) is a chip widely used in household appliances, large machinery and even aerospace. The use of FPGA chips does not require Electronic Design Automation (EDA) tools. Layout is an important ring in EDA tools, which has a large impact on the speed of operation of the EDA tool itself, and the ultimate quality of the processed circuit. In recent years, the circuit scale of FPGA chips has rapidly increased to make them more powerful, but at the same time, it has also presented challenges to the corresponding EDA tools.
The main function of the layout is to map the instances in the user netlist to the layout positions of the FPGA chip with actual physical coordinates one by one under the optimization target, and the analytic layout algorithm becomes one of the mainstream directions of the current layout algorithm due to the characteristic that the analytic layout algorithm can quickly obtain the global optimal solution by using a mathematical method.
In the force-oriented analytical layout algorithm, an IO module is laid out first, and then other modules are spread on an FPGA chip by using a fixed IO as a pulling point. The layout positions of the IO modules have a great influence on subsequent layout quality and time sequence, but the number and types of the IO modules in the FPGA are large, and it is difficult for a user to specify the layout positions of all the IO modules, so at present, the layout positions are generally specified by the user for a small part of the IO modules, and the rest of the IO modules are automatically laid out by development software, and the IO modules are generally randomly laid out to random positions according to a certain capacity rule, but the layout quality is difficult to be ensured by the random layout method.
Content of application
The applicant provides an IO module layout method based on module connection relation for FPGA aiming at the problem that the layout quality is difficult to ensure by the existing random layout method of IO modules in FPGA, and the technical scheme of the method is as follows:
an IO module layout method based on module connection relation of FPGA comprises:
acquiring a user input netlist corresponding to the FPGA chip, and determining the layout positions of a plurality of preset functional modules in the user input netlist;
determining an IO module to be distributed which is connected with a preset function module and is not distributed in a user input netlist;
for each IO module to be distributed, determining the IO layout position of the IO module to be distributed based on the layout position of each preset function module connected with the IO module to be distributed, wherein the comprehensive circuit performance of each group of signal connection relations between the IO module to be distributed and each preset function module connected with the IO module to be distributed is optimal when the IO module to be distributed is at the determined IO layout position;
and finishing the layout of the residual IO modules which are not laid out in the user input netlist.
The FPGA chip comprises a plurality of BANKs, and each BANK comprises a plurality of IO layout positions; determining the IO layout position of the IO module to be distributed based on the layout positions of all the preset functional modules connected with the IO module to be distributed, including:
determining one BANK in the FPGA chip as a target BANK based on the layout position of each preset functional module connected with the IO module to be distributed, wherein the comprehensive circuit performance of each group of signal connection relations between the IO module to be distributed and each preset functional module connected with the IO module to be distributed is optimal when the IO module to be distributed is in the target BANK;
and selecting one IO layout position from the target BANK as the IO layout position of the IO module to be distributed according to the resource constraint condition.
The further technical scheme is that the method for determining the target BANK comprises the following steps:
and taking the BANK with the largest number of reference functional modules contained in the corresponding layout area in the FPGA chip as a target BANK, wherein the reference functional module is a preset functional module which has a direct signal connection relationship with the IO module to be distributed.
The further technical scheme is that the method for determining the target BANK comprises the following steps:
taking the BANK with the highest regional time sequence key degree in the FPGA chip as a target BANK; the regional time sequence criticality corresponding to one BANK is the optimal value of the path time sequence criticality of all the preset function modules of which the layout positions are in the layout region corresponding to the BANK, or the time sequence scoring value obtained according to the path time sequence criticality corresponding to all the preset function modules and a time sequence scoring method;
the route time sequence criticality of each preset function module is the time sequence criticality of a time sequence route where the signal connection relation between the preset function module and the IO module to be distributed is located.
The further technical scheme is that the method for determining the target BANK comprises the following steps:
obtaining a time sequence scoring value of the BANK according to a time sequence scoring method according to the path time sequence criticality of all the preset function modules contained in a layout area corresponding to the BANK; obtaining the connection degree score of the BANK according to the number of preset functional modules which are contained in a layout area corresponding to the BANK and have direct signal connection relation with the IO modules to be distributed;
taking the BANK with the highest total score obtained based on the time sequence score and the connection score as a target BANK;
the route time sequence criticality corresponding to each preset function module is the time sequence criticality of a time sequence route where the signal connection relation between the preset function module and the IO module to be distributed is located.
The further technical scheme is that the time sequence scoring method comprises the following steps:
for each preset function module contained in a layout area corresponding to the BANK, if the path time sequence criticality of the preset function module reaches a criticality threshold value, accumulating time sequence scores of preset scores for the BANK, wherein the preset scores accumulated each time are equal or the preset scores accumulated at least twice are different.
The method comprises the following step of determining the preset score accumulated this time according to the path time sequence criticality of a preset function module when the path time sequence criticality reaches a criticality threshold, wherein the higher the path time sequence criticality of the preset function module is, the larger the accumulated preset score is.
The further technical scheme is that the total score of one BANK is obtained by weighting the corresponding time sequence score and the corresponding connection score, and the weights of the time sequence score and the connection score are equal or unequal.
The further technical scheme is that when the total score is obtained through weighting, the weight of the time sequence score is higher than that of the connection score.
The further technical scheme is that the layout of the residual IO modules which are not laid out in the user input netlist is completed, and the method comprises the following steps:
based on the traction action of all IO modules with determined IO layout positions and predetermined function modules with determined layout positions, performing force-oriented analytical layout on the FPGA chip according to a user input netlist to obtain an initial layout result;
and for each residual IO module, determining the IO layout position of the residual IO module based on the layout position of each functional module connected with the residual IO module in the initial layout result, wherein the comprehensive circuit performance of each group of signal connection relations between the residual IO module and each functional module connected with the residual IO module is optimal when the residual IO module is at the determined IO layout position.
The further technical scheme is that the number of the preset functional modules contained in the user input netlist does not exceed a first number threshold, and the number of the distributable positions of each preset functional module on the FPGA chip does not exceed a second number threshold.
The further technical scheme is that the predetermined function module comprises at least one of an IO module, an IOLGIC module, an IODELAY module, a GTH module, a CMT module, a BUFG module, an MMCM module, a DPLL module, an XPLL module, a PCIE module and an EMAC module.
The beneficial technical effect of this application is:
the application discloses an FPGA IO module layout method based on module connection relation, which is used for assisting in deducing IO layout positions of IO modules based on connection information of the functional modules provided by a user input netlist and the layout positions of preset functional modules from the perspective of enabling comprehensive circuit performance to be optimal, and completing the layout of the IO modules. Due to the fact that the performance of the integrated circuit is considered in the process of layout of the IO module, the problems caused by conventional random layout can be avoided, and therefore the quality of subsequent overall layout is better.
In the process of considering the layout of the IO module by the comprehensive circuit performance, the connectivity performance and/or the time sequence performance can be considered according to the actual situation, and the weights of the two performances can be set according to the situation, so that the bias weight is carried out on a certain performance, and the circuit performance requirements under different scenes can be met.
Drawings
FIG. 1 is a flowchart illustrating an IO module layout method according to an embodiment.
Fig. 2 is a flowchart illustrating an IO module layout method according to another embodiment.
Fig. 3 is a flowchart illustrating an IO module layout method according to another embodiment.
Detailed Description
The following description of the embodiments of the present application will be made with reference to the accompanying drawings.
The application discloses an IO module layout method based on module connection relation of FPGA, which includes the following steps, please refer to the flow chart shown in FIG. 1:
step 100, obtaining a user input netlist corresponding to the FPGA chip, and determining layout positions of a plurality of predetermined functional modules in the user input netlist.
In theory, the predetermined function module may be any function module in the netlist input by the user, and the layout position of the predetermined function module can be determined by the user specification. However, in practice, if the predetermined functional modules are some too conventional functional modules, such as CLB modules, because the number of the functional modules is large and the number of the distributable positions on the FPGA chip is large, the difficulty of specifying the layout positions by the user is large, the layout positions specified by the user are not necessarily the preferred layout result, and the module connection relationships of the functional modules may not well guide the layout of the IO module in the following process, which may result in that the final layout quality may not be ensured.
Thus, in one embodiment, the number of predetermined functional modules included in the user input netlist does not exceed the first number threshold, and the number of deployable locations of each of the predetermined functional modules on the FPGA chip does not exceed the second number threshold. That is, the predetermined functional modules are usually some special functional modules with a small number and a small number of arrangeable positions in the user input netlist. The number of these predetermined function modules is not so large that the difficulty and the workload of determining their layout positions are not excessive and the operability is high. In addition, the distributable positions of the predetermined function modules are limited, and some predetermined function modules may have only 1 distributable position, so that the difficulty of determining the layout positions of the predetermined function modules is low, and generally, the determined layout positions are all the layout positions which are more consistent with the final layout result. In addition, since many special functional modules exist in the IP format, peripheral logic is also attached thereto, and when software supports IP, it is common to map IP onto an FPGA chip and determine an appropriate layout area, so that the layout position of a predetermined functional module can be determined.
Based on this principle, in one embodiment, the predetermined function module includes at least one of an IO module, an IOLGIC module, an IODELAY module, a GTH module, a CMT module, a BUFG module, an MMCM module, a DPLL module, an XPLL module, a PCIE module, and an EMAC module. The IO module herein refers to an IO module that some users specify to arrange.
For each predetermined function module, there are mainly two methods in determining the layout position of the predetermined function module: one method is to take the layout position designated by the user as the layout position of the predetermined function module. Another method is to determine the layout positions of other predetermined functional modules based on the predetermined functional modules whose layout positions have been determined, for example, a user first specifies the layout positions of some IO modules, and then lays out the other predetermined functional modules according to the connection relationships between the other predetermined functional modules and the IO modules that have been laid out. In practice, these two methods may be used in combination.
Step 200, determining an IO module to be laid, which is connected with a predetermined function module and is not laid out, in the user input netlist. Namely, the connection ports of the preset function modules are traversed circularly, and the IO modules which are connected with the preset function modules and are not laid out are found out to be used as the IO modules to be laid.
Step 300, for each IO module to be distributed, determining the IO layout position of the IO module to be distributed based on the layout positions of the preset functional modules connected with the IO module to be distributed. And when the IO module to be distributed is at the determined IO layout position, the comprehensive circuit performance of each group of signal connection relations between the IO module to be distributed and each preset functional module connected with the IO module to be distributed is optimal.
And step 400, completing layout of the remaining IO modules which are not laid out in the user input netlist.
In the step 300, since the IO modules are too small, numerous, and complex in connection relationship, the difficulty and the calculation amount for directly determining the IO layout position where the performance of the integrated circuit is optimal are large. Considering that a large number of IO layout positions in an FPGA chip often exist in a BANK form, each BANK comprises a plurality of IO layout positions, and each BANK determines IO characteristics such as voltage, single/double-port, high/low speed and the like. Thus, in one embodiment, the step 300 determines the final IO layout position through two layers of progressive operations, please refer to the flowchart shown in fig. 2:
and step 310, determining one BANK in the FPGA chip as a target BANK based on the layout position of each preset functional module connected with the IO module to be distributed.
And determining that the obtained comprehensive circuit performance of each group of signal connection relations between the IO module to be distributed and each preset function module connected with the IO module to be distributed is optimal when the IO module to be distributed is in the target BANK, namely firstly taking the BANK as a unit, and firstly screening the target BANK where the IO layout position of the IO module to be distributed is located from a plurality of blocks by a first layer of operation.
When a target BANK is selected, the performance of an integrated circuit needs to be considered, the performance of the integrated circuit can be various important performances in the field of FPGA design, and in the application, two types of performances which are most frequently considered in the FPGA design process are mainly considered: there are three main cases of connectivity performance and/or timing performance, and thus the method of determining the target BANK:
(1) in the first case: only connectivity performance is considered.
In this case, the BANK having the largest number of reference functional blocks included in the corresponding layout region in the FPGA chip is taken as the target BANK. The reference function module is a preset function module which has direct signal connection relation with the IO module to be distributed. I.e. giving priority to BANK with more direct connections so that connectivity performance is optimal.
For each IO module to be distributed, it may be connected to one predetermined functional module or may be connected to a plurality of predetermined functional modules. Each predetermined functional module to which the IO module to be distributed is connected may be directly connected or indirectly connected, and the predetermined functional module directly connected to the IO module to be distributed is defined as a reference functional module in this embodiment.
The FPGA chip is provided with a plurality of different layout areas (regions), and after the layout position of the preset function module is determined, the layout area where each preset function module is located can be determined. Each layout area has a corresponding BANK, the corresponding relationship is predetermined and fixed, and one layout area may correspond to one BANK. Therefore, after the layout positions of the predetermined function modules are obtained, the number of the predetermined function modules included in each layout area can be obtained through statistics. For one IO module to be distributed, the number of reference function modules corresponding to the IO module to be distributed included in each layout region may also be obtained through statistics, that is, the number of reference function modules included in different layout regions corresponding to different BANKs may also be determined, and the BANK with the largest number of reference function modules included therein is taken as the target BANK. And if the number of the reference functional modules contained in the layout regions corresponding to the plurality of BANKs is the largest and equal, selecting one of the reference functional modules as the target BANK.
For example, in one example, one to-be-distributed IO module is connected with 6 predetermined functional modules, which are respectively denoted as A, B, C, D, E, F, where F is not directly connected with the to-be-distributed IO module, and the other 5 predetermined functional modules are all directly connected with the to-be-distributed IO module to form a reference functional module. A. B, C are located in layout area 1 and D and E are located in layout area 2. Layout area 1 corresponds to BANK1 and layout area 2 corresponds to BANK2, then in this example, BANK1 is finally selected as the target BANK.
(2) In the second case: only timing performance is considered.
In this case, the BANK with the highest criticality of the timing of the corresponding region in the FPGA chip is used as the target BANK, that is, the BANK with the optimal timing is considered preferentially. The correspondence among the predetermined functional module, BANK, and layout area is as described above in the first case, and this embodiment is not described again.
The regional timing criticality corresponding to one BANK is determined based on the path timing criticality of a predetermined functional module with a layout position in a layout region corresponding to the BANK. The timing sequence criticality of the path corresponding to each predetermined functional module is the timing sequence criticality of the timing sequence path where the signal connection relationship between the predetermined functional module and the IO module to be distributed is located, and the timing sequence criticality of the timing sequence path can be measured by using a slack value.
There are various conditions for determining the regional timing criticality of the corresponding BANK based on the path timing criticality of a predetermined functional module in a layout region at a layout position: (1) the optimal value of the path time sequence criticality corresponding to all the preset functional modules in the layout area is directly used as the area time sequence criticality of the BANK. (2) And obtaining a time sequence score value according to the route time sequence criticality corresponding to all the preset functional modules according to a time sequence scoring method, and taking the obtained time sequence score value as the regional time sequence criticality of the BANK.
In one embodiment, the timing scoring method is as follows: for each preset functional module contained in a layout area corresponding to a BANK, if the path time sequence criticality of the preset functional module reaches a criticality threshold, accumulating time sequence scores of preset scores for the BANK, wherein the preset scores accumulated each time are equal or the preset scores accumulated at least twice are different.
For example, in an example, taking the predetermined scores accumulated each time as 2 as an example, assuming that a layout area corresponding to a BANK includes three predetermined function modules, where the criticality of the path timing corresponding to two predetermined function modules reaches a criticality threshold, and the criticality of the path timing corresponding to another predetermined function module does not reach the criticality threshold, the timing score of the BANK is 4 by accumulating twice.
If there are at least two different predetermined points accumulated, one case is: (1) the preset score accumulated this time is determined according to the module type of the preset function module, the preset scores accumulated by the different types of the preset function modules are different under the condition that the path time sequence criticality also reaches the criticality threshold, and the specific corresponding relation can be configured correspondingly in advance. The other situation is that: (2) and determining the preset score accumulated this time according to the path time sequence criticality of the preset function module, wherein the higher the path time sequence criticality of the preset function module is, the larger the accumulated preset score is.
(3) In the third case: while timing performance and connectivity performance are considered.
Obtaining a timing sequence scoring value of the BANK according to the path timing sequence criticality of all the preset functional modules contained in a layout area corresponding to the BANK and a timing sequence scoring method; and obtaining the connection degree scores of the BANK according to the number of preset functional modules which are contained in the layout area corresponding to the BANK and have direct signal connection relation with the IO modules to be distributed.
In the third case, the method for obtaining the time sequence score value is similar to that in the second case, and there are a plurality of specific implementation manners, which will not be described in detail in this embodiment. The method for determining the number of the predetermined function modules, namely the reference function modules, which are included in the layout area corresponding to each BANK and have a direct signal connection relationship with the IO modules to be distributed, is similar to the first case, except that in this embodiment, unlike the first case, one BANK with the largest number of reference function modules is directly taken, but the connection score of each BANK is obtained according to the number of the reference function modules, and the specific method for obtaining the connection score also has a plurality of scoring modes as the time sequence score, and this embodiment provides the following modes: (1) the connection degree of the BANK is in positive correlation with the number of the reference functional modules contained in the layout area corresponding to the BANK, the connection degree is obtained by accumulating the number of the reference functional modules, and the more the number of the reference functional modules contained, the larger the connection degree of the BANK is. Similar to the time series score, the score of each reference function may be the same or different. In one implementation, the scores of two reference function modules with different module types are different and can be preset. And (4) determining. In this scoring manner, as an example, assuming that the score of each reference functional module is equal to 2, when 4 reference functional modules are included in a layout area corresponding to one BANK, the score of the connectivity of the BANK is 8. (2) When the number of the reference function modules contained in the layout area corresponding to the BANK exceeds a preset number threshold, a preset connection degree score is recorded for the BANK, otherwise, a connection degree score of 0 is recorded for the BANK, and in the mode, the connection degree scores of the BANKs with the number of all the contained reference function modules exceeding the preset number threshold are all equal. For example, the connection scores of BANKs having reference function blocks in the corresponding layout area, the number of which exceeds 2, are all 1, and the connection scores of BANKs having no more than 2 are all 0.
And taking the BANK with the highest total score based on the time sequence score and the connection score as the target BANK. The total score of one BANK is obtained by weighting the corresponding time sequence score and the corresponding connection score, and the weights of the time sequence score and the connection score are equal or unequal. More generally, the timing score value is weighted higher than the connectivity score value when the total score is weighted, considering that timing is more important to the FPGA layout.
And 320, selecting one IO layout position from the resource constraint conditions in the target BANK as the IO layout position of the IO module to be distributed, namely executing the second layer of operation to finally screen out the final IO layout position after the target BANK is obtained. The IO module to be distributed has its own characteristic requirements, for example, there are characteristic requirements for voltage, high speed and low speed, and for example, the type of signal transmitted by the IO module to be distributed also determines its characteristic requirements. And each BANK also has its own resource constraint condition, the total number of IO layout positions included in the BANK is limited, and the number of IO layout positions satisfying the corresponding characteristic requirements is smaller, for example, only certain IO layout positions in the BANK can be used for placing IO modules with incoming clock signals, and once the IO layout positions are occupied, the IO modules with incoming clock signals cannot be placed. Therefore, the final IO placement position needs to be determined according to the resource constraint condition in the target BANK.
And when at least one IO layout position meeting the characteristic requirements of the IO module to be distributed exists in the target BANK, selecting one IO layout position as the IO layout position of the IO module to be distributed. And when the IO layout position meeting the characteristic requirement of the IO module to be distributed does not exist in the target BANK, returning to step 310, and re-determining the target BANK according to the sequence from the optimal performance of the integrated circuit to the low performance, that is, in the second cycle, taking the BANK with the suboptimal performance of the integrated circuit as the target BANK until the IO layout position of the IO module to be distributed is finally obtained.
In step 400, for the remaining IO modules, one method is to perform random layout on the remaining IO modules on the FPGA chip at the spare IO layout positions. However, the placement position of the IO module has a great influence on the subsequent layout quality and timing, and random layout should be avoided as much as possible, so in an embodiment, the layout method for the remaining IO modules includes the following steps, please refer to fig. 3:
and step 410, based on the traction action of all IO modules at the determined IO layout positions and the predetermined function modules at the determined layout positions, performing force-oriented analytic layout on the FPGA chip according to the user input netlist to obtain an initial layout result, and in this step, performing iterative solution on the force-oriented analytic layout for a plurality of times according to actual needs.
And step 420, for each remaining IO module, determining an IO layout position of the remaining IO module based on the layout position of each functional module connected to the remaining IO module in the initial layout result, so that the comprehensive circuit performance of each group of signal connection relationships between the remaining IO module and each functional module connected to the remaining IO module is optimal when the remaining IO module is at the determined IO layout position. The specific implementation manner of this step is similar to the layout method for determining the IO layout position of the IO module to be laid in step 300, and details are not repeated in this embodiment.

Claims (12)

1. An IO module layout method based on module connection relation of FPGA is characterized by comprising the following steps:
acquiring a user input netlist corresponding to an FPGA chip, and determining the layout positions of a plurality of preset functional modules in the user input netlist;
determining an IO module to be distributed which is connected with a preset function module and is not distributed in the user input netlist;
for each IO module to be distributed, determining the IO layout position of each preset function module connected with the IO module to be distributed based on the layout position of each preset function module connected with the IO module to be distributed, wherein the comprehensive circuit performance of each group of signal connection relations between the IO module to be distributed and each preset function module connected with the IO module to be distributed is optimal when the IO module to be distributed is at the determined IO layout position;
and finishing layout on the residual IO modules which are not laid out in the user input netlist.
2. The method of claim 1, wherein the FPGA chip includes a plurality of BANKs, each BANK including a plurality of IO layout locations therein; determining the IO layout position of the IO module to be distributed based on the layout positions of the predetermined function modules connected to the IO module to be distributed, including:
determining one BANK in the FPGA chip as a target BANK based on the layout position of each preset functional module connected with the IO module to be distributed, wherein the comprehensive circuit performance of each group of signal connection relations between the IO module to be distributed and each preset functional module connected with the IO module to be distributed is optimal when the IO module to be distributed is in the target BANK;
and selecting an IO layout position from the target BANK as the IO layout position of the IO module to be distributed according to the resource constraint condition.
3. The method of claim 2, wherein determining the target BANK comprises:
and taking the BANK with the largest number of reference functional modules contained in the corresponding layout area in the FPGA chip as the target BANK, wherein the reference functional module is a preset functional module which has a direct signal connection relation with the IO module to be distributed.
4. The method of claim 2, wherein determining the target BANK comprises:
taking the BANK with the highest corresponding regional time sequence criticality in the FPGA chip as the target BANK; the method comprises the following steps that a regional time sequence criticality corresponding to a BANK is the optimal value of the path time sequence criticality of all preset functional modules of which the layout positions are in a layout region corresponding to the BANK, or a time sequence scoring value obtained according to the path time sequence criticality corresponding to all the preset functional modules and a time sequence scoring method;
the route time sequence criticality of each preset function module is the time sequence criticality of a time sequence route where the signal connection relation between the preset function module and the IO module to be distributed is located.
5. The method of claim 2, wherein determining the target BANK comprises:
obtaining a timing sequence scoring value of a BANK according to a timing sequence scoring method according to the path timing sequence criticality of all preset functional modules contained in a layout area corresponding to the BANK; obtaining the connection degree score of the BANK according to the number of preset functional modules which are contained in a layout area corresponding to the BANK and have direct signal connection relation with the IO modules to be distributed;
taking the BANK with the highest total score obtained based on the time sequence score and the connection score as the target BANK;
the route time sequence criticality corresponding to each preset function module is the time sequence criticality of a time sequence route where the signal connection relation between the preset function module and the IO module to be distributed is located.
6. The method of claim 4 or 5, wherein the time sequence scoring method comprises:
for each preset functional module contained in a layout area corresponding to a BANK, if the path time sequence criticality of the preset functional module reaches a criticality threshold, accumulating time sequence scores of preset scores for the BANK, wherein the preset scores accumulated each time are equal or the preset scores accumulated at least twice are different.
7. The method according to claim 6, wherein when the path timing criticality reaches a criticality threshold, the predetermined score accumulated this time is determined according to the path timing criticality of the predetermined functional module, and the higher the path timing criticality of the predetermined functional module is, the larger the accumulated predetermined score is.
8. The method of claim 5, wherein the total score of a BANK is weighted by the corresponding time series score and the connectivities score, and the time series score and the connectivities score are weighted equally or unequally.
9. The method of claim 8, wherein the time-series score value is weighted higher than the connection score value when the total score value is weighted.
10. The method of claim 1, wherein said completing placement of remaining IO modules not placed in said user input netlist comprises:
based on the traction action of all IO modules with determined IO layout positions and predetermined function modules with determined layout positions, performing force-oriented analytical layout on the FPGA chip according to the user input netlist to obtain an initial layout result;
and for each residual IO module, determining the IO layout position of the residual IO module based on the layout position of each functional module connected with the residual IO module in the initial layout result, wherein the comprehensive circuit performance of each group of signal connection relations between the residual IO module and each functional module connected with the residual IO module is optimal when the residual IO module is at the determined IO layout position.
11. The method of claim 1, wherein the number of predetermined functional modules included in the user input netlist does not exceed a first number threshold, and the number of routable locations of each predetermined functional module on the FPGA chip does not exceed a second number threshold.
12. The method of claim 11, wherein the predetermined function module comprises at least one of an IO module, an IOLGIC module, an IODELAY module, a GTH module, a CMT module, a BUFG module, an MMCM module, a DPLL module, an XPLL module, a PCIE module, and an EMAC module.
CN202210723992.5A 2022-06-24 2022-06-24 IO module layout method based on module connection relation of FPGA Pending CN115048892A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116306431A (en) * 2023-05-23 2023-06-23 中科亿海微电子科技（苏州）有限公司 FPGA layout method and device based on module and data flow

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116306431A (en) * 2023-05-23 2023-06-23 中科亿海微电子科技（苏州）有限公司 FPGA layout method and device based on module and data flow
CN116306431B (en) * 2023-05-23 2023-09-12 中科亿海微电子科技（苏州）有限公司 FPGA layout method and device based on module and data flow

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