CN107563095A - A kind of non-linear layout method of large scale integrated circuit - Google Patents
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Abstract
The invention discloses a kind of non-linear layout method of large scale integrated circuit, including：Plane net gauge pressure is condensed to multi-level pattern, knot group is carried out for movable units therein, using each movable units as node when tying group, using the size of the potential value between each node and its all neighbor nodes as knot group's foundation, target knot group's area is as constraints；Global wiring is proceeded by from the superiors to the netlist after knot group, and solution group operatione is carried out after each layer of global wiring terminates, finally obtains the netlist of non-linear layout.This method carries out knot group as desired value using the ratio of the internal Connected degree of two movable units and external connection degree to unit, simultaneously increase it is area-constrained come balance knot group area, by in this non-linear layout device of knot group's algorithm embedded plane, run time and quality can be improved.
Description
Technical Field
The invention relates to the technical field of integrated circuit layout, in particular to a nonlinear layout method of a large-scale integrated circuit.
Background
The integrated circuit is a core technology for transforming and promoting the traditional information industry, is in the current society where the informatization industry is the main body, and is called as 'crude oil in the electronic information industry'. The integrated circuit industry is an industry integrating knowledge, technology, capital and labor intensity, is the industry with the largest investment amount in the current information product manufacturing industry, and is the most important in the development of national information. According to the statistics of the industry development organization of the united nations, 65% of the value added part of the total value of the national production of the world is related to the integrated circuit.
The rapid development of integrated circuit technology brings great innovation to human society, and promotes the transformation of the human society from industry to information society. As a backbone of the information industry, the design and fabrication of Very-Large-Scale-Integrated circuits (VLSI) is becoming the core and foundation of the development of the entire information industry. Therefore, the integrated circuit industry is vigorously developed, the integrated circuit design and the manufacturing technology thereof are deeply researched, the development of the information industry of China can be powerfully promoted, the development of national economy is greatly promoted, and the method has extremely important significance.
Electronic Design Automation (EDA), the most basic aid and tool for the Design and fabrication of integrated circuits, is an indispensable part of the integrated circuit industry. The rapid development of integrated circuits has benefited from the shrinking of feature sizes, the expansion of silicon chip areas, and the improvement of lithography instruments. But the advent of opportunities also presents EDA challenges: the design scale is larger and larger, and the problem is more and more complicated.
Integrated circuit design includes the processes of system design, logic design, circuit design, physical design, test and manufacturing, as shown in fig. 1. In the whole integrated circuit design process, physical design (also called layout design or layout design) is an important ring, and the layout of logic cells (such as gates, flip-flops, full adders and the like) in a logic diagram is placed on a proper position of a chip according to the connection information of the logic diagram of the integrated circuit, namely the layout; then, the units are interconnected according to logic signals, namely wiring; and compressing the redundant space under the condition of meeting the design rule to reduce the chip area, namely layout compression. The physical design is required to minimize the chip area while meeting the basic characteristics (e.g., logic function, static and dynamic electrical characteristics, power consumption, etc.) requirements and certain process conditions of the integrated circuit. The input of the physical design is the component description and the netlist of the circuit, and the output is the designed layout.
Layout is a very important step in physical design. Its performance largely determines the quality of the subsequent steps. A poor quality layout not only wastes chip area, but also directly affects the subsequent wiring design, making wiring difficult. Layout problems refer to placing components or modules in the proper locations on a chip and making them meet certain objective functions. The detailed meaning and goal of the layout problem varies from object to object. Generally, when the layout problem is processed, the chip area is always required to be minimum, the total length of the connecting wire is shortest, the electrical performance is optimal, and the wiring is easy. In a layout mode with pre-routing modules and pre-routing, the layout of the circuit elements is also kept away from these obstacles. The layout problem is an NP-hard problem. Modern layout tools typically divide the layout into two substeps, overall layout and detailed layout. In the overall layout, the circuit elements are optimally positioned to obtain a globally reasonable relative position. In a detailed layout, circuit elements are assigned to specific locations and meet the requirements of the layout pattern.
Existing analytical global placers achieve good results in the physical design of planar large-scale integrated circuits, but take a significant amount of runtime, especially as the size of the netlist increases dramatically. Moreover, some units with the same connection relationship have the same size, initial position and stress, and are overlapped together in later movement, so that the units cannot be easily separated. Circuit clustering is an effective way to reduce the scale of LSI layout problems without affecting the quality of the final layout.
Clustering is one method of constructing a multi-layer framework. The multi-level architecture (shown in fig. 2) is divided into a coarse layout phase, an initial layout phase, an inverse coarse layout phase, and an optimization phase. The rough partitioning transforms a graph with more nodes into a graph with less nodes by using a clustering method. The initial layout is the initial layout of the topmost layer determined in a certain way. The subsequent coarse drawing and optimization is to gradually restore the clustered small diagrams to the original graphs and simultaneously optimize by using a planar global layout method.
Through the clustering means, the closely connected units are combined together to participate in the layout as a whole, so that the problem solving space is reduced, and the speed and the quality of the layout can be effectively improved. If the bunching method is well designed, good wire length results are obtained, while the run time is much reduced compared to the planar mode. The clustering method is added into the flow of the nonlinear layout algorithm, so that the planar netlist is preprocessed to reduce the scale of the layout problem, the running time is reduced, and the final solving quality is guaranteed.
The clustering is to cluster given circuit units into a plurality of subsets from bottom to top under a certain objective function, then combine small clusters into a large cluster, and satisfy given constraint conditions. The objective function is typically the maximum connectivity, latency, etc. The constraints may be the size of the subset, fixed units, etc. The layout circuit is usually abstracted as a hypergraph G = (V, E). V is a set of nodes, each layout cell being represented as a node; e is the set of the super edges, and each net corresponds to one super edge. Each hyper-edge is effectively a subset of nodes.
The current common clustering scheme and its drawbacks are described below:
scheme 1: the FirstChoice algorithm accesses all the units in random sequence and combines the accessed units and the first neighbor node of the accessed units into a new node. As shown in fig. 3, assume a cluster granularity of 2 (up to two nodes are added to a cluster). The algorithm randomly traverses all cells, assuming that node (5) is first visited, its first neighbor node is (1), and then (1) (5) is clustered. If the first node visited is (1), it will cluster with its first neighbor node (2). However, this clustering method, while fast and concise, does not yield good results because it does not take into account the connection relationships between the units. The result is more random.
Scheme 2: the bestchchoice algorithm, as shown in fig. 4, considers the connection relationship between cells and the area of cells, and attaches a value to each potential junction group, and the junction group with the largest value is implemented. Depending on the number of modules (which may be single cells or sets of cells), an area factor is introduced at the same time to control the size of the clusters. Combining two factors, the value of the cluster between the two modules u, v can be expressed as:
wherein the weight w of e e Equal to 1/| e |, where | e | is the number of super edges, and a (u), a (v) are the areas of the modules u, v, respectively. (the area of the single cell is assumed to be 1 hereinafter).
And sorting the cluster values between every two modules calculated by the formula, combining the two units with the maximum cluster values into a whole, calculating the cluster values of the two units and re-sorting the cluster values of the two units, and so on until the number of the units is reduced to a preset value. Taking fig. 4 as an example, the values of the clusters of every two vertices are calculated, the maximum values are 1 and 2, and then they are combined into a unit, and then the values of (1, 2) and other nodes are recalculated, the maximum values are 3 and 4, and 3 4 are combined into a unit. In the three cases (a), (B) and (c) shown in fig. 5, since the AB has two super edges and the area is 1, the values of d (a, B) calculated by the bestchchoice algorithm are the same (all 1). In practice, the three situations are different, so that the BestChoice cannot well describe the connection relationship between the units.
Disclosure of Invention
The invention aims to provide a nonlinear layout method of a large-scale integrated circuit, which can improve the running time and quality and solve the problem of overlarge running time of the large-scale circuit.
The purpose of the invention is realized by the following technical scheme:
a nonlinear layout method of a large scale integrated circuit comprises the following steps:
compressing the planar netlist into a multi-level pattern, clustering movable units in the planar netlist, taking each movable unit as a node during clustering, taking the potential value between each node and all neighbor nodes of each node as a clustering basis, and taking the target clustering area as a constraint condition;
and carrying out global layout on the clustered netlist from the uppermost layer, and carrying out de-clustering operation after the global layout of each layer is finished to finally obtain the non-linear layout netlist.
According to the technical scheme provided by the invention, the ratio (potential value) of the internal connectivity to the external connectivity of the two movable units is taken as a target value to group the units, the area constraint is increased to balance the area of the group, and the group algorithm is embedded into the planar nonlinear layout device, so that the running time and the quality can be improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a circuit design flow chart provided in the background of the invention;
FIG. 2 is a schematic diagram of a multi-layer architecture provided in the background of the invention;
FIG. 3 is a schematic diagram of the FirstChoice algorithm provided in the background of the invention;
FIG. 4 is a schematic diagram of a BestChoice algorithm provided in the background art of the present invention;
FIG. 5 is a schematic diagram of the connectivity provided by the background of the invention;
FIG. 6 is a flowchart of a LSI nonlinear layout method according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating types of grouping units according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a binary node clustering algorithm provided in accordance with an embodiment of the present invention;
FIG. 9 is a flow chart of a conjugate gradient method provided by an embodiment of the present invention;
FIG. 10 is a schematic diagram of the diffusion of each layer of cells according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of the actual density variation provided by the embodiment of the present invention;
fig. 12 is a diagram illustrating the number of clusters per layer in ibm01 node groups according to an embodiment of the present invention;
fig. 13 is a schematic diagram illustrating a ratio of operation times of each layer when ibm01 junction groups are provided in an embodiment of the present invention;
FIG. 14 is a graph of the change in the half-circumference according to an embodiment of the present invention;
FIG. 15 is a graph of maximum density variation provided by an embodiment of the present invention;
fig. 16 is a screenshot of a layout result provided by an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a nonlinear layout method of a large-scale integrated circuit, which applies the binary group algorithm provided by the embodiment of the invention to the layout process of a very large-scale integrated circuit to accelerate the layout process and obtain a better layout result. As shown in fig. 6, after a planar netlist is obtained, a preprocessing step is performed to compress the netlist into a multi-level pattern, then the clustering process is performed based on a binary clustering algorithm, and then certain expansion is realized along with the cluster breaking display of the next layer of clusters, and the process is circulated until the initial planar netlist is well extended, so that effective non-overlapping positions are allocated to all movable elements. The following mainly aims at the details of the clustering, the de-clustering and the global layout.
1. Cluster part
Preprocessing the input netlist reduces the scale to only a few thousand clusters, tightly controls the cluster area, and uses slow update. The clustering is performed in a multi-level model, each node cluster layer is about 1/cluster ratio of the previous node cluster layer, the cluster ratio is a given value and represents the granularity of the node cluster, and a plurality of units are taken as a node cluster. The clustered cluster attribute settings are as in table 1:
| properties | Attribute value |
| Type (B) | Moveable |
| Area of | Sum of area of all units in cluster |
| Width (height) | Area square |
| Connected network | Network to which all units in cluster are connected |
Table 1cluster attribute
As shown in fig. 7, when grouping, only the movable units are grouped while omitting the fixed units. Specifically, the embodiment of the invention performs clustering based on a binary clustering algorithm, and the binary clustering algorithm is mainly based on the connection relation of the initial plane netlist. It groups modules (which may be single units or units of a set) according to their internal and external association values. To prevent some of the clusters from being excessively large, an area factor is usually introduced to control the size of the clusters.
Firstly, each movable unit is taken as a node, the potential value between each node and all the adjacent nodes is taken as a clustering basis, and the target clustering area is taken as a constraint condition.
In the embodiment of the invention, the ratio of the internal and external connectivity of two nodes is taken as a potential value, and the calculation formula is as follows:
wherein, I ij Representing the degree of connection between node i and node j, E i Representing the total degree of external connection of node i, E j Representing the total degree of external connectivity for node j.
Unlike the previous clustering algorithm (i.e., scheme 2 in the background art) which only considers the connections between the units, the binary clustering algorithm provided in the embodiment of the present invention also considers the connections between the units and the outside. As shown in fig. 5 (a), (B) and (c), two super edges exist between a and B, but the ratio of the internal and external connection degrees is very different because the connection degrees of a and B are different from those of other units. It can be seen that the ratio of the internal and external connectivity of A and B in (a) is 4/3 (2/3 + 2/3), (B) is 4 (2/1 + 2/1), (c) is ∞ (2/5 + 2/0) which is the maximum value, so A and B in (c) should be grouped together more.
In addition to considering the internal and external connectivity, attention should be paid to controlling the area difference between the clusters not too large so as to facilitate the shape matching between the modules, and the two factors are combined. Therefore, the binary clustering algorithm provided by the embodiment of the present invention clusters the units by using the ratio of the internal connectivity to the external connectivity of the two units as the target value, and increases the area constraint to balance the area of the clusters.
Taking the node group values of the two nodes as the total area after the nodes are combined, and the calculation formula is as follows:
wherein, f (a) i ) Is the area factor of node i, whose value is equal to the area a of node i i In inverse proportion; f (a) j ) Is the area factor of node j, its value and the area a of node j j In inverse proportion, it can control the binary group not to increase too early, making it more balanced.
The clustering is to combine cells into one cluster from bottom to top based on the connectivity between cells or other objective functions, and then combine small clusters into larger clusters. When the nodes are grouped, potential values of the nodes, neighbor nodes and the potential values are used as a triple ratio to be inserted into a priority queue which is arranged according to the descending order of the potential values; clustering nodes in the first element and neighbor nodes in the priority queue to serve as a new node, deleting the first element if the total area of the new node is larger than the area of the target cluster, and continuing clustering the next element; after obtaining a new node, calculating a potential value of the node and a neighbor node, inserting the new node, the neighbor node and the potential value of the node and the neighbor node as a triple ratio into a priority queue arranged in descending order according to the potential value, and repeating the clustering process until a target clustering number is reached; and finally, obtaining the clustered netlist.
For nodes 1-5, taking fig. 8 as an example, first, potential values of each node and its neighboring nodes are calculated respectively; then, the potential values of the node, the neighbor nodes and the two nodes are used as a triple ratio to be inserted into a priority queue which is arranged according to the descending order of the potential values, and the node and the neighbor nodes in the first element in the priority queue are clustered to be used as a new node. In this example, the potential values of node 1, node 5, and both are ∞ in the first element, so node 1, node 5 are merged into a new node 1,5; if the total area of the new nodes 1,5 is greater than the target cluster area, then this element is deleted, starting with the second element, i.e., nodes 3,4 are clustered; in this example, assume that the total area of the new nodes 1,5 is less than the target node group area. And then, continuing to calculate potential values of the new nodes 1 and 5 and the neighbor nodes thereof, and inserting the potential values of the new nodes, the neighbor nodes thereof and the two nodes into a priority queue arranged in descending order according to the potential values as a triple ratio, wherein at the moment, the first element in the priority queue is the node 3, the node 4 and the potential value 6 thereof, so that the node 3 and the node 4 are combined into a new node 3 and 4 (assuming that the total area of the new nodes 3 and 4 is smaller than the target group area), and so on until the target group number is reached.
The flow of the whole clustering algorithm can be shown in table 2:
TABLE 2 clustering algorithm procedure
In the embodiment of the present invention, wherein, the target number of clusters = current number of clusters/ratio of clusters; target cluster area =1.5 total cell area/number of target clusters.
In the algorithm implementation, a structural body is selected to represent the triples, and the PQ queue is selected from a linear linked list. Complexity analysis is carried out on the whole clustering algorithm, and the key points of the running time are found as follows: 1) Traversing all vertexes and all vertexes connected with the vertexes; 2) Recalculating the cluster values consumes a large amount of runtime and, as the clustering proceeds, the consumption becomes greater. But the time complexity is still polynomial level, which does not bring too much operation burden.
In the embodiment of the invention, the clustered netlist is subjected to global layout from the uppermost layer, and the de-clustering operation is performed after the global layout of each layer is finished, so that the netlist in the nonlinear layout is finally obtained.
2. Part of solution group
And triggering a solution algorithm after the global layout of each layer is finished, opening the group of the layer, replacing the elements of the layer by the elements of the next layer, and setting the initial coordinates as the positions of the central points of the elements of the layer. The algorithm flow is shown in table 3:
TABLE 3 solution group algorithm process
The above-mentioned de-clustering process can also be referred to as the right de-clustering process shown in fig. 2, i.e. starting from the top of the cluster, separating the units that are clustered together, where the initial position of each unit is the center point of the original cluster, then running the global layout, and after the dispersion, re-solving one layer until the original planar netlist.
3. Global layout
In the embodiment of the invention, the nonlinear optimization technology is used for optimizing the line length and effectively expanding the module, and the objective function is as follows:
minHPWL(x,y)；
s.t.Dg(x,y)＝Dg for each grid g；
where HPWL (x, y) is the total half perimeter of all cells (including both movable and fixed cells), (x, y) is the cell center coordinates, dg (x, y) is the density formula, dg is the average density in each cell that is desired, and g is the grid point;
the formulas for line length (half perimeter is the most common way to calculate line length) and density are both non-convex and non-differentiable, so smooth transitions are first made for these two functions.
The Log-sum-exp line length formula is used to approximate the half perimeter and is expressed as:
WL(e)＝a·(log(∑e x/a )+log(∑e -x/a ))+a·(log(∑e y/a )+log(∑e -y/a ))；
where e is a natural constant, a is a smoothing factor, and as a approaches zero, WL (e) approaches HPWL (x, y);
the bell-shaped formula is used to model the density fraction, expressed as:
wherein, w g Is the size of the grid, d comprises d x And d y The potential value formula of a cell c with a center point at (x, y) at grid point g = (GridX, gridY) is:
Potential(c,g)＝a(c)·p(|d x |)·p(|d y |)；
wherein p is a density function and d x ＝x–GridX，d y = y-GridY, a (c) is a normalization factor that makes the potential value of each cell equal to its own area:
wherein A is the area of unit c;
then the non-uniform cell dispersion formula is:
wherein ExpPotential (g) is the average density expected in each grid, i.e., dg as described above; gridg, cellc in the summation formula refer to grid point g, cell c, respectively.
The line length objective and density constraints are connected by a penalty function to obtain the following unconstrained optimization problem:
wherein, mu i A penalty factor for the ith cycle; for the next cycleThe penalty factors are all less than the penalty factor of the last cycle, i.e., μ 0 >μ 1 >μ 2 >…>μ k >μ k+1 >...
Finally, the above optimization problem is solved using the conjugate gradient method, as shown in fig. 9.
The minimum is found through a series of linear searches, and the result of each search is used as the initial value of the next search and is expressed as:
x k+1 ＝x k +α k d k
wherein k is the number of iterations, g k Is the gradient of the function at the k-th iteration, alpha k Is the step size of the linear search obtained at the k-th iteration, d k Is the conjugate direction at the kth iteration, i.e. the search direction; parameter beta k And (3) solving by adopting a PR method:
selecting an initial point x in the feasible region 0 Selecting a random direction which can reduce the objective function value most quickly as a search direction d 0 . From the initial point x 0 Starting at edge d 0 The direction is searched by a certain step length to obtain a new point x 1 New point x 1 The constraint condition is satisfied, and f (x) 1 )<f(x 0 ) Completing one iteration; with new point x 1 The above search process is repeated for the starting point until a stop condition is reached.
The stop conditions include: the value of the density function part is larger than that of the last cycle, so that oscillation can be avoided; or the average value of the deviation value of the actual density to the expected density in each grid is less than the preset value, so that the modules can be uniformly scattered. If exit with maximum density occurs where the rest has spread out, the process is limited to a grid of large density without stopping, which can affect the line length results and layout quality.
In order to illustrate the effects of the above-described scheme of the present invention, comparative experiments were also conducted with the prior art.
As shown in Table 4, the results of comparing the above-mentioned scheme with the conventional layout algorithm in planar mode (W-C Gao, Y-Q Lv, X.Qian, Q.Zhou, H-X Yan and X.Wu.A Nonlinear plan Technique for FPGA-Like uniformity scheme in Proc. Of ICCDA, V3 pages 441-444, june, 2010)
Table 4 comparison of layout algorithm of this scheme with planar mode
As can be seen from table 4, compared with the layout algorithm in the planar mode, the operation time of the present scheme is optimized by 40%, and the quality is improved by 12%, which also proves that the clustering algorithm provided by the embodiment of the present invention can help a large-scale circuit to solve the problem of excessive operation time.
In addition, the placers implemented based on the above-described scheme of the present invention and other placers currently using the knot grouping method (T. Chan, J.Cong, and K.Sze. Multilevel generated force-directed method for circuit placement. In Proc. Of ISPD, pages 185-192, april 2005), including Capo v9.0, fastPlace v1.0, fengshui v5.0 and mPL-fast, were also tested. The test case uses the example of IBM ISPD04 standard cell. The comparative results are shown in Table 5. The first column is the test case. The line length of our placer global placement, the line length of the detailed placement and the total run time are in the second to fourth columns of table 3. Capo v9.0 (a.e. caldwell, a.b. kahng, and i.l. markov. Can secure biological induction one product Routable Placement in proc. Design Automation con. Pp.477-482, 2000), fastPlace v1.0 (n.viswanathan and c.chu. FastPlace: effective Analytical plan Using Cell Shifting, effective Local replacement and a Hybrid Net model in Proc. International Symposium on Physical Design, pp.26-33, 2004), fengShui v5.0 (M.C.YIldiz and P.H.M.D. improved Current Sequences for partitionalized basic plan in Proc.ACM/IEE Design in Automation Conf.,2001, pp.776-779) and mPL-fast (T.Chan, J.Cong, and K.S.S.Multi-sized for-differentiated method for reliable plan in PD, ISPD, 185-192, results from sixth to eighth columns, pp.C.Y.Yildiz and P.H.M.M.E.G.I.M.C.A.C.D.A.C.C.for Partitioning and P.S.S.S.S.S.No. 92 PD, P.P.B.S.B.S.S.S.S.S.S.S.S.S.A. for detailed implementation in. Considering that the scheme provided by the invention uses nonlinear solution, the nonlinear solution is directly applied to actual projects, and the implementation platform is industrial OpenAccess, so that a certain sacrifice is caused in time, but the solution quality, namely the total line length, is reduced by about 7%,9%, 1% and 5% on average compared with that of Capo9.0, fastPlace1.0, fengshui5.0 and mPL5-fast respectively.
The second column is our overall layout result line length, the third column is the line length result from running our global layout with the details layout of fastplace3.0, and the fourth column is the result after the details layout of fastplace3.0 and its elapsed time. The results for FastPlace3.0 averaged about a 22% reduction in wire length.
Table 5 compares the results with other placers using the clustering method
Fig. 10 shows the diffusion of each layer unit in the multi-layer structure flow of the placer implemented by the above-mentioned solution of the invention. It can be clearly seen that as the grid of each layer becomes smaller, the number of grids becomes larger, and the cell diffusion becomes more and more uniform. This also verifies the correctness of the grid size setting of the present invention. At the beginning, the grid is large, and the clusters are relatively sparse; as the solution clustering progresses, the grid becomes smaller, the number of clusters becomes larger, and the cells are denser.
In the global layout, a Potential function Potential is used for smoothing the grid density, and the cells are moved from a grid with high density to a grid with low density, so that the cells in the whole layout area are uniformly distributed. Fig. 11 shows the variation of the actual density in each grid, and the z direction is the actual density value of each grid. The upper points (i.e., the more sparse points) represent the density of the top layer, while the bottom points (i.e., the more dense points) represent the actual density of the bottom layer. The z-direction coordinates of the upper points are all large and have large differences, which indicates that the density between grids is not uniform enough from beginning to end. With the smoothing process, the grid density becomes smaller and uniform, indicating that the cells are spread out. We can also see from the figure that the upper points are less than the bottom points, which also reflects our mesh strategy.
We specifically analyze the case ibm01, wherein 12506 units of ibm01 are shared, and the above-mentioned clustering algorithm is used to cluster three layers, and the number of cluster in each layer is shown in FIG. 12. The layout runtime ratio for each layer at the junction group is shown, for example, in fig. 13. The number of the first layer units is the largest, and the layout time is the longest.
To observe the line length and density variations in the global layout flow based on the cluster, we recorded the half-cycle value and the maximum density value after each conjugate gradient solution of example ibm01, and plotted the two curves of fig. 14 and 15.
From the figure, it can be seen that the line length is continuously increased and the maximum density value is continuously decreased in the whole process. This is consistent with the goal we set. During initialization, all cells are concentrated in the middle of the layout area, so that the overlapping is large, the line length is small, the overlapping is reduced along with the diffusion of the cells, and the line length is correspondingly increased. ibm01 has three layers, and the curve has three peaks, because the number of the units to be deblocked is doubled each time, the line length and the overlapping rate are increased.
We have selected the final run results screenshots of several examples in the ibm series, see fig. 16, where (a) - (d) correspond to ibm02, ibm12, ibm13, and ibm16 in order.
According to the scheme of the embodiment of the invention, the ratio of the internal connectivity to the external connectivity of the two movable units is used as a target value to group the units, the area constraint is increased to balance the area of the group, and the group algorithm is embedded into the planar nonlinear layout device, so that the operation time is reduced by 40% compared with the planar mode, and the quality is improved by 12%. The detailed layout result of the layout device is respectively optimized by 7%,9%,7% and 5% compared with the current popular layout devices Capo, fastPlace, fengshui and mPL5-fast algorithms which also adopt the clustering algorithm, and the effectiveness and the high efficiency of the algorithm are shown
Through the above description of the embodiments, it is clear to those skilled in the art that the above embodiments can be implemented by software, and can also be implemented by software plus a necessary general hardware platform. Based on such understanding, the technical solutions of the embodiments may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.), and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods according to the embodiments of the present invention.
The above description is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are also within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (7)
1. A LSI nonlinear layout method is characterized by comprising the following steps:
compressing the planar netlist into a multi-level pattern, clustering movable units in the planar netlist, taking each movable unit as a node during clustering, taking the potential value between each node and all neighbor nodes of each node as a clustering basis, and taking the target clustering area as a constraint condition;
and carrying out global layout on the clustered netlist from the uppermost layer, and carrying out de-clustering operation after the global layout of each layer is finished to finally obtain the non-linear layout netlist.
2. The nonlinear layout method of lsi of claim 1, wherein the ratio of the internal and external connectivity of two nodes is used as the potential value, and the calculation formula is:
wherein, I ij Representing the degree of connection between node i and node j, E i Representing the total degree of external connection of node i, E j Representing the total degree of external connectivity for node j.
3. The nonlinear layout method of LSI according to claim 1 or 2, wherein when grouping nodes, the potential values of the nodes, their neighboring nodes and both are inserted as a triple ratio into a priority queue arranged in descending order according to the potential values; clustering nodes and neighbor nodes in a first element in the priority queue, and using the nodes and the neighbor nodes as a new node, if the total area of the new node is larger than the area of a target cluster, deleting the first element, and continuing clustering of the next element until the target cluster number is reached; after obtaining a new node, calculating potential values of the new node and neighbor nodes thereof, inserting the potential values of the new node, the neighbor nodes thereof and the two nodes into a priority queue arranged in descending order according to the potential values as a triple ratio, and repeating the clustering process until the target clustering number is reached; and finally, obtaining the clustered netlist.
4. The LSI nonlinear layout method of claim 3, wherein the joint group value of two nodes is taken as the total area after the joint, and the calculation formula is:
wherein,I ij representing the degree of connection between node i and node j, E i Representing the total degree of external connection of node i, E j Representing the external total connectivity of the node j; f (a) i ) Is the area factor of node i, its value and the area a of node i i In inverse proportion; f (a) j ) Is the area factor of node j, its value and the area a of node j j In inverse proportion.
5. The LSI nonlinear layout method of claim 1, wherein the global layout step comprises:
the nonlinear optimization technology is used for optimizing the line length, meanwhile, the module can be effectively unfolded, and the objective function is as follows:
min HPWL(x,y)；
s.t.Dg(x,y)＝Dg for each grid g；
where HPWL (x, y) is the total half perimeter of all cells, (x, y) is the center coordinates of the cells, dg (x, y) is the density formula, dg is the average density in each grid that is desired;
the Log-sum-exp line length formula is used to approximate the half perimeter and is expressed as:
WL(e)＝a·(log(∑e xi/a )+log(∑e -xi/a ))+a·(log(∑e yi/a )+log(∑e -yi/a ))；
wherein e is a natural constant, a is a smoothing factor, and when a approaches zero, WL (e) approaches HPWL (x, y);
the bell-shaped formula is used to model the density fraction, expressed as:
wherein w g Is the size of the grid, d contains d x And d y The potential value formula of a cell c with a center point at (x, y) at grid point g = (GridX, gridY) is:
Potential(c,g)＝a(c)·p(|d x |)·p(|d y |)；
wherein p is secretDegree function, d x ＝x–GridX，d y = y-GridY, a (c) is a normalization factor that makes the potential value of each cell equal to its own area:
wherein A is the area of unit c;
the non-uniform cell dispersion formula is:
wherein ExpPotential (g) is the desired average density per mesh;
and connecting the line length target and the density constraint by using a penalty function so as to obtain the following unconstrained optimization problem:
wherein, mu i The penalty factors of the ith cycle are all smaller than the penalty factor of the last cycle;
finally, the optimization problem is solved by using a conjugate gradient method.
6. The LSI nonlinear layout method of claim 5, wherein the step of solving the optimization problem by conjugate gradient method comprises:
the minimum value is found through a series of linear searches, and the result of each search is used as the initial value of the next search and is expressed as:
x k+1 ＝x k +α k d k
where k is the number of iterations, g k Is the gradient of the function at the k-th iteration, alpha k Is the step size of the linear search obtained at the k-th iteration, d k Is the conjugate direction at the kth iteration, i.e. the search direction; parameter beta k And (3) solving by adopting a PR method:
selecting an initial point x in the feasible region 0 Selecting a random direction which can make the objective function value decrease the fastest as the searching direction d 0 From the initial point x 0 Starting at edge d 0 The direction is searched in a certain step length to obtain a new point x 1 New point x 1 Constraint conditions need to be met, and one iteration is completed at this time; at a new point x 1 The above search process is repeated for the starting point until a stop condition is reached.
7. The LSI nonlinear layout method of claim 6, wherein the stop condition comprises: the value of the density function part is larger than the value of the last cycle, or the average value of the deviation value of the actual density to the expected density in each grid is smaller than the preset value.
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| CN108763777A (en) * | 2018-05-30 | 2018-11-06 | 福州大学 | VLSI global wiring method for establishing model based on Poisson's equation explicit solution |
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| CN116822452A (en) * | 2023-08-23 | 2023-09-29 | 芯行纪科技有限公司 | Chip layout optimization method and related equipment |
| CN116822452B (en) * | 2023-08-23 | 2023-11-21 | 芯行纪科技有限公司 | Chip layout optimization method and related equipment |
| CN117725874A (en) * | 2023-11-30 | 2024-03-19 | 宁波齐芯半导体科技有限公司 | Integrated circuit capacitor layout method based on parallelization gene AI algorithm |
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