CN108763777B - Method for establishing VLSI global layout model based on Poisson equation explicit solution - Google Patents

Method for establishing VLSI global layout model based on Poisson equation explicit solution Download PDF

Info

Publication number
CN108763777B
CN108763777B CN201810543412.8A CN201810543412A CN108763777B CN 108763777 B CN108763777 B CN 108763777B CN 201810543412 A CN201810543412 A CN 201810543412A CN 108763777 B CN108763777 B CN 108763777B
Authority
CN
China
Prior art keywords
electric field
potential
module
equation
layout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810543412.8A
Other languages
Chinese (zh)
Other versions
CN108763777A (en
Inventor
朱文兴
陈建利
黄志鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuzhou University
Original Assignee
Fuzhou University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuzhou University filed Critical Fuzhou University
Priority to CN201810543412.8A priority Critical patent/CN108763777B/en
Publication of CN108763777A publication Critical patent/CN108763777A/en
Application granted granted Critical
Publication of CN108763777B publication Critical patent/CN108763777B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/10—Numerical modelling

Abstract

The invention relates to a method for establishing a VLSI global layout model based on the explicit solution of Poisson equation, which expresses a circuit as a hypergraph model; simulating a VLSI circuit layout model into a two-dimensional electrostatic system, and converting density constraint into constraint of total potential energy N (v) =0 of the electrostatic system; establishing a partial differential equation set based on the Poisson equation, the boundary condition and the compatibility condition; establishing an analytic expression of a density function, and substituting the analytic expression into a partial differential equation set; determining expressions of electric potential and electric field according to the density function; determining the convergence of the electric potential and electric field expression; obtaining a solving expression of electric potential and electric field according to the partial sum; and obtaining the potential and electric field value of each grid by a rapid calculation method, weighting to obtain the potential and electric field of the module, and completing the VLSI circuit layout model establishment under the action of electric field force. The invention can provide a high-efficiency and practical global layout result, and can meet the requirements of the current VLSI global layout stage particularly for large-scale examples.

Description

Method for establishing VLSI global layout model based on Poisson equation explicit solution
Technical Field
The invention relates to the technical field of Very Large Scale Integration (VLSI) physical design automation, in particular to a VLSI global layout model building method based on Poisson's equation explicit solution.
Background
As technology advances into the deep nanometer era of billion transistor integration, the performance of layout tools dominates the overall quality of EDA tools. Therefore, in the near term, many placers have been developed. There are three main layout algorithms: simulated annealing based methods, partitioning based methods and analysis based methods. Recent studies have shown that analytic-type placers are generally able to achieve better placement quality and have good scalability.
In an analysis-based layout, one key technique is to reduce the overlap between modules to achieve a uniformly dispersed layout. For analysis-based layouts, many documents propose methods of reducing overlap, such as partitioning, cell movement, frequency control, partitioning, bell-shaped density control, helmholtz density control, and poisson density control. In these methods, poisson density control is employed by some mainstream placers, such as FDP, kraft werk, mFAR, and ePlace.
In the global layout, ePlace adopts the poisson equation, and in all theoretical placers based on ISPD2005 and ISPD2006 test examples, the optimal line length is achieved. The ePlace first converts each module to a positive charge, converting the module density to a potential energy constraint for disposal. And then modeling through electric potential and electric field generated by given charge density, establishing a Poisson equation, and setting a Norefman boundary condition and a compatibility condition according to the characteristics of the layout. Poisson's equation is a Partial Differential Equation (PDE) that is solved spectrally, ePlace can quickly calculate a potential and electric field distribution, so it can minimize line length while spreading the module quickly.
Poisson's equation is commonly used in many fields such as electrostatics, computer science, mechanical engineering, theoretical physics, astronomy, chemistry, and the like. For example, poisson's equation may use a biquadratic hermitian function to create a system with finite elements in a rectangular domain. In particular, poisson's equation is often used to describe the potential field distribution resulting from a given charge or mass density.
Solutions of the poisson equation fall into two categories: analytical solutions and numerical solutions. The analytical solution is an accurate solution and is also an explicit solution of partial differential equations. The numerical solution is obtained by numerical methods such as finite element method, numerical approximation method, interpolation method, etc. Since the numerical solution can only approximate the solution of the PDE, the numerical solution inevitably produces some numerical errors. Taking the half-space problem of characteristic strain as an example, people do a lot of work to minimize numerical errors. Generally, if an explicit solution for a PDE can be found, it is inherently superior to a numerical solution.
In the existing placers based on poisson density control, a numerical solution is used for solving poisson equations. In Kraft werk, a geometric multi-grid solver DiMePACK is used to solve the Poisson equation; in ePlace, a Fast Fourier Transform (FFT) is utilized to calculate the potential and electric field distribution. However, the poisson equation for different boundary conditions has different characteristics, and thus its solution is also different. It is generally considered that obtaining an explicit solution to a PDE is very challenging, if not impossible. Such as the lorentz force expression, is suitable and accurate in finite element simulations, but is not suitable for calculations.
Disclosure of Invention
The invention aims to provide a method for establishing a VLSI global layout model based on the Poisson equation explicit solution, so as to overcome the defects in the prior art.
In order to achieve the purpose, the technical scheme of the invention is as follows: a VLSI global layout model establishing method based on Poisson equation explicit solution comprises the following steps:
step S1: representing the circuit as a hypergraph model H = { V, E };
step S2: simulating a VLSI circuit layout model into a two-dimensional electrostatic system, and converting density constraint into constraint of total potential energy N (v) =0 of the electrostatic system;
and step S3: establishing a partial differential equation set based on the Poisson equation, the boundary condition and the compatibility condition;
and step S4: establishing an analytical formula of a density function, and substituting the analytical formula into a partial differential equation set;
step S5: determining expressions of electric potential and electric field according to the density function;
step S6: determining the convergence of the electric potential and electric field expression;
step S7: obtaining a solving expression of electric potential and electric field according to the partial sum;
step S8: and obtaining the potential and electric field value of each grid by a rapid calculation method, weighting to obtain the potential and electric field of the module, and completing the VLSI circuit layout model establishment under the action of electric field force.
Compared with the prior art, the invention has the following beneficial effects:
(1) The distribution of the modules is simulated by using an accurate density function, and numerical errors cannot be generated;
(2) Directly solving the Poisson equation on the basis of the accurate density function to obtain an explicit solution, and proving the convergence of the solution; because the analytical solution is adopted, no numerical error is generated when the electrostatic system is solved;
(3) The method not only realizes the optimization of the line length, but also ensures the solving speed. In comparison with two mainstream placers ePlace and NTUplace3, the results of using ISPD2005 and ISPD2006 test sets show that the algorithm of the invention can make the line length smaller. The solution of the fast Poisson equation of the software is used for replacing the density control, and the experimental result of embedding into NTUplace3 shows that the algorithm can reduce the wire length by 11 percent and greatly improve the result.
Drawings
FIG. 1 is a flow chart of a VLSI global layout model building method based on the explicit solution of Poisson's equation in the present invention.
Detailed Description
The technical scheme of the invention is specifically explained in the following by combining the attached drawings.
The invention relates to a method for establishing a VLSI global layout model based on Poisson equation explicit solution, which comprises the following steps as shown in figure 1:
(1) Representing the circuit as a hypergraph H = { V, E };
(2) Simulating the layout problem into a two-dimensional electrostatic system, and converting the density constraint into the constraint of the total potential energy N (v) =0 of the electrostatic system;
(3) Establishing a partial differential equation set by utilizing a Poisson equation, a boundary condition and a compatibility condition;
(4) Giving an analytic expression of the density function, and substituting the analytic expression into a partial differential equation set;
(5) Determining accurate expressions of the electric potential and the electric field by using a density function;
(6) The convergence of the potential and electric field expressions is proved;
(7) And obtaining a solving expression of the electric potential and the electric field by using the partial sum.
(8) And obtaining the electric potential and the electric field value of each grid by a quick calculation method, weighting to obtain the electric potential and the electric field of the module, and finishing the layout under the action of the electric field force.
Further, in step (1), the given layout area is [0, W ]]×[0，H]The VLSI circuit layout problem can be modeled as a hypergraph G (V, E), with the module represented as a set of vertices V = { V = } 1 ,v 2 ,...,v n Represents the net as a super-edge set E = { E = } 1 ,e 2 ,...,e r H, module v i Is w and is high i And h i The coordinate of the center point is (x) i ,y i ). Wherein i =1, 2, ·, n. The VLSI layout problem is to determine the optimal position of each module without overlap between modules, and the bus length is optimal:
there is no overlap between min W (v) s.t. modules (1)
Wherein W (v) is the total line length, calculated by the half perimeter line length (HPWL).
Further, in step S2, the layout problem is simulated as a two-dimensional electrostatic system. Depending on the position of the module in the layout area, the electric potential φ (x, y) and the electric field ξ (x, y) can be determined, where ξ (x, y) = (ξ) x ,ξ y ) = phi (x, y). Module i is regarded as a positive charge i, area A i Is expressed as a charge amount q i . By phi i ＝φ(x i ,y i ) And xi i ＝ξ(x i ,y i ) Representing the potential and electric field at charge i. The charge i is then dependent on the electric force F i ＝q i ξ i The movement is performed. Thus, the system potential energy may be defined as
Figure BDA0001679194060000041
Wherein N is i ＝q i φ i Representing the potential energy of charge i. And finally, converting the density constraint into a constraint of total potential energy N (v) =0 of the electrostatic system.
Further, in step (3), a partial differential equation set is established using poisson's equation, boundary conditions and compatibility conditions. Based on Gauss law, a Poisson equation of the electrostatic system is constructed, and a partial differential equation is obtained while satisfying layout boundary conditions and compatibility conditions:
Figure BDA0001679194060000042
where equation (2 a) gives the poisson equation, where ρ (x, y) is a density function; equation (2 b) is a Nooedeman boundary condition for avoiding a module running out of the boundary of the layout, where R and
Figure BDA0001679194060000043
respectively representing the boundary and the outer normal vector of the layout region R; equation (2 c) is a compatibility condition, giving the system of equations a unique solution.
Further, in step (4), the density function of the module i in the x direction is defined as:
Figure BDA0001679194060000044
to be compared with vector (x, y) = (x) 1 ,y 1 ,...x i ,y i ) Making a distinction by
Figure BDA0001679194060000045
Representing a continuous variable. Likewise, the density function of module i in the y-direction can be defined as
Figure BDA0001679194060000046
The density function of module i is
Figure BDA0001679194060000047
The total density of all modules over the layout area is:
Figure BDA0001679194060000048
where n is the number of modules.
Further, in fig. 1, the "analytic solution" part is solved in the following specific manner:
redefining to satisfy equation (2 c)
Figure BDA0001679194060000051
Figure BDA0001679194060000052
Using the exact density function, poisson's equation, the relevant boundary conditions and compatibility conditions (2 a) - (2 c) become:
Figure BDA0001679194060000053
further, in step (5), by equations (6 a) and (6 b), their solutions can be obtained as follows:
Figure BDA0001679194060000054
wherein, a u,p Denotes the coefficient of each wave function, and u and p denote integer indices. To calculate the coefficient a u,p Substituting equation (7) into Poisson equation (6 a), and calculating
Figure BDA0001679194060000055
The density function can be obtained
Figure BDA0001679194060000056
Another expression form of (a):
Figure BDA0001679194060000057
multiplication on both the left and right sides of equation (8) simultaneously
Figure BDA0001679194060000058
And integrated to obtain
Figure BDA0001679194060000061
The integration region of equation (9) is R = (0, w) × (0, h). Thus, to the right of equation (9), the first term takes on non-zero values only at μ =0, p = η, the second term only at η =0 and u = μ, and the third term only at p = η and u = μ, according to the orthogonality of the trigonometric functions. Thus at μ ≧ 1 and η =0, equation (9) reduces to:
Figure BDA0001679194060000062
it is thus possible to obtain:
Figure BDA0001679194060000063
also, the coefficient a can be obtained 0,η And a μ,η In order to satisfy equation (6 c), let a be in equation (7) 0,0 =0, then:
Figure BDA0001679194060000064
when μ, η ≧ 1, the formula (5) is taken into the formula (12 d) to obtain:
Figure BDA0001679194060000071
the following are also available:
Figure BDA0001679194060000072
and
Figure BDA0001679194060000073
note that in VLSI layout problem, a u，p Is calculated from the integral of the exact density function (5) and is more accurate than the discrete calculation in ePlace.
Further, in fig. 1, the "potential gradient" part is solved in the following manner:
known from Gauss's law, the electric field
Figure BDA0001679194060000074
Equal to negative gradient of electric potential
Figure BDA0001679194060000075
Of formula (7)
Figure BDA0001679194060000076
Is provided with
Figure BDA0001679194060000077
Figure BDA0001679194060000078
Further, in step (6), because of equation (9)
Figure BDA0001679194060000079
Is an infinite series, and is thus to be proven
Figure BDA0001679194060000081
Is convergent.
And (5) leading to 1.
Infinite series of numbers
Figure BDA0001679194060000082
And
Figure BDA0001679194060000083
is convergent.
Theorem 1.
Infinite number of stages
Figure BDA0001679194060000084
Is absolutely convergent.
And (3) proving that:
note that:
Figure BDA0001679194060000085
for a u,p U, p ≧ 1, by equation (13):
Figure BDA0001679194060000086
for the other two cases u =0, p ≧ 1 and u ≧ 1, p =0, there are:
Figure BDA0001679194060000087
and
Figure BDA0001679194060000088
thus, it is possible to provide
Figure BDA0001679194060000091
By theory 1, the above three infinite series are convergent, so
Figure BDA0001679194060000092
There is an upper bound of convergence, therefore
Figure BDA0001679194060000093
Is absolutely convergent.
Further, in step (7), according to theorem 1, in practice, the measurement is carried outOnly need to calculate in the calculation
Figure BDA0001679194060000094
The sum of (1) and (b). In addition to this, the present invention is,
Figure BDA0001679194060000095
is that
Figure BDA0001679194060000096
The negative gradient of (2) can also be used
Figure BDA0001679194060000097
Is approximated by a partial sum of (c). Because u is contained in equation (17) 3 Or p 3 Thus, therefore, it is
Figure BDA0001679194060000098
The convergence is fast and a more accurate solution can be obtained by iterating the computation partial sums only K times.
Therefore, the layout area can be divided into m × m grids of the same specification, and each grid is written as: b lj Where l =0, 1, · m-1, j =0, 1, · m-1, and m-1 denote the labels of the grids, then grid b lj The density of (a) is then:
Figure BDA0001679194060000099
module i in grid b lj Is determined by the size of the module, and the distance from the center point of module i and grid b lj Is inversely proportional, similar to the local smoothing and density scaling technique in ePlace, and the following density function can be obtained
Figure BDA00016791940600000910
Wherein
Figure BDA0001679194060000101
Representation grid b lj Is used as the density function. Order (x) l ，y j ) Representation grid b lj Then the density function of all the grids approximated by equation (5) can be obtained as:
Figure BDA0001679194060000102
at the determined a u，p By substituting formula (18) into formulae (12 b), (12 c) and (12 d) at u =0 and p>In the case of = 1:
Figure BDA0001679194060000103
wherein x is l And y j Determined by the size and layout area of the grid, will
Figure BDA0001679194060000104
Substitution of formula (19) gives:
Figure BDA0001679194060000105
the remaining coefficients can also be obtained in the same manner. All coefficients a found u,p The following were used:
Figure BDA0001679194060000111
for each grid b lj A potential in the formula (7)
Figure BDA0001679194060000112
Can be recalculated using the following equation:
Figure BDA0001679194060000113
is determined byInfinite number of stages in theory 1
Figure BDA0001679194060000114
Is absolutely convergent, so the following approximation can be made:
Figure BDA0001679194060000115
electric field in formula (16)
Figure BDA0001679194060000116
Can be approximated as:
Figure BDA0001679194060000117
further, in step (8), the density of each mesh is calculated according to equation (18)
Figure BDA0001679194060000118
In equations (21 a) - (21 b), a coefficient matrix a 'of m × m can be calculated by ignoring the summation of coefficients' u,p ：
Figure BDA0001679194060000121
The coefficient matrix can be calculated by calling an FFT library once, and m is spent 2 Time to coefficient matrix a' u,p Is updated to a u,p Calculate all coefficients a u,p . After all the coefficients are calculated, phi (l, j) and xi (l, j) can be calculated by inverse fast Fourier transform, and the electric force F i ＝q i ξ i The module i is moved to complete the layout.
Further, in fig. 1, the "line length gradient" part is solved in the following specific manner:
in problem (1), W (v) is inconsequential, and direct optimization is difficult, so LSE line length is used to approximate HPWL. The LSE line length function in the x direction is:
Figure BDA0001679194060000122
wherein gamma is a smooth parameter, and the line length gradient can be obtained by solving the gradient of the function.
Further, the "module location optimization and parameter update" part in fig. 1 is implemented in the following specific manner:
in each iteration, a Nesterov method is adopted to solve the unconstrained minimization problem, and a new solution (x) is obtained through one iteration k+1 ，y k+1 ) The solution is the optimized module position, and then the penalty parameter λ is updated.
The above are preferred embodiments of the present invention, and all changes made according to the technical solutions of the present invention that produce functional effects do not exceed the scope of the technical solutions of the present invention belong to the protection scope of the present invention.

Claims (3)

1. A VLSI global layout model building method based on Poisson equation explicit solution is characterized by comprising the following steps:
step S1: representing the circuit as a hypergraph model G = { V, E }, wherein V is a vertex set, E is a hyperedge set, and a layout area is set to be [0, W ] × [0, H ];
step S2: simulating a VLSI circuit layout model into a two-dimensional electrostatic system, and converting density constraint into constraint of total potential energy N (v) =0 of the electrostatic system;
and step S3: establishing a partial differential equation set based on the Poisson equation, the boundary condition and the compatibility condition;
in step S3, based on gaussian law, a poisson equation of the electrostatic system is established, and partial differential equations are obtained while satisfying the layout boundary condition and the compatibility condition, where the partial differential equations are:
poisson equation, where ρ (x, y) is a density function:
Figure FDA0003849535620000011
where φ (x, y) represents the potential at charge;
noelman boundary condition for avoiding a module running out of a boundary of a layout, where R and
Figure FDA0003849535620000012
the boundary and the outer normal vector of the layout region R are respectively represented:
Figure FDA0003849535620000013
compatibility conditions, make the system of equations have a unique solution:
Figure FDA0003849535620000014
and step S4: establishing an analytic expression of a density function, and substituting the analytic expression into a partial differential equation set;
in step S4, the density function of the module i in the x direction is expressed as:
Figure FDA0003849535620000015
to be compared with vector (x, y) = (x) 1 ,y 1 ,...x i ,y i ) To distinguish by
Figure FDA0003849535620000021
Represents a continuous variable; define the density function of module i in the y-direction as
Figure FDA0003849535620000022
The density function of module i is
Figure FDA0003849535620000023
The total density of all modules over the layout area is:
Figure FDA0003849535620000024
wherein n is the number of modules;
redefining ρ (x, y):
Figure FDA0003849535620000025
wherein w i And h i Are respectively a module v i Width and height of (d);
from the density function, the poisson equation, boundary conditions and compatibility conditions become:
Figure FDA0003849535620000026
Figure FDA0003849535620000027
Figure FDA0003849535620000028
step S5: determining expressions of electric potential and electric field according to the density function;
step S6: determining the convergence of the electric potential and electric field expression;
step S7: obtaining a solving expression of electric potential and electric field according to the partial sum;
step S8: obtaining the potential and electric field value of each grid by a rapid calculation method, weighting to obtain the potential and electric field of the module, and completing the establishment of a VLSI circuit layout model under the action of electric field force;
in step S5, according to the poisson equation and the boundary condition obtained in step S4, the following solution is obtained:
Figure FDA0003849535620000029
wherein, a u,p Coefficients representing each wave function, u and p representing integer indices; to calculate the coefficient a u,p Substituting the solution into the Poisson equation obtained in step S4, and calculating
Figure FDA00038495356200000210
Obtaining a density function
Figure FDA00038495356200000211
Another expression of (a):
Figure FDA0003849535620000031
wherein the content of the first and second substances,
Figure FDA0003849535620000032
Figure FDA0003849535620000033
Figure FDA0003849535620000034
according to Gauss's law, electric field
Figure FDA0003849535620000035
Equal to electric potential
Figure FDA0003849535620000036
A negative gradient of (d); from the above solution
Figure FDA0003849535620000037
Is provided with
Figure FDA0003849535620000038
Figure FDA0003849535620000039
In the step S7, the layout area is divided into m × m grids of the same specification, and each grid is denoted as b lj Wherein l =0, 1, · m-1, j =0, 1, · m-1, and m-1 represent the labels of the grids, and let
Figure FDA00038495356200000310
Grid b lj Has a density of
Figure FDA00038495356200000311
The potential is then:
Figure FDA00038495356200000312
the electric field is:
Figure FDA00038495356200000313
wherein:
Figure FDA0003849535620000041
in the step S8, a coefficient matrix a 'of m × m is calculated' u,p ：
Figure FDA0003849535620000042
Calculating coefficient matrix by calling FFT library once and spending m 2 Time coefficient matrix a' u,p Is updated to a u,p Calculating all the coefficients a u,p (ii) a After all the coefficients are calculated, phi (l, j) and xi (l, j) are calculated by inverse fast Fourier transform, and the electric field force F i ＝q i ξ i And (5) moving the module i to complete the VLSI circuit layout model establishment.
2. The method for modeling a global layout of VLSI based on explicit poisson' S equation solution as claimed in claim 1, wherein in step S1, the layout area is [0,w ]]×[0,H]Given n modules and r nets, the VLSI circuit layout model is treated as a hypergraph G (V, E), and the modules are represented as a set of vertices V = { V = 1 ,v 2 ,...,v n Denoted as super-edge set E = { E 1 ,e 2 ,...,e r H, module v i Is w and is high i And h i The coordinate of the center point is (x) i ,y i ) I =1, 2, ·, n; the VLSI circuit layout model determines the optimal position of each module without overlap between modules and the bus length is optimal:
min W(v)
there is no overlap between s.t. modules
Wherein, W (v) is the total line length and is obtained by calculating the half perimeter line length.
3. A VLSI global layout model building method based on poisson' S equation explicit solution according to claim 2, characterized in that in step S2, according to the position of the module in the layout area, the electric potential Φ (x, y) and the electric field ξ (x, y) are determined, where ξ (x, y) = (ξ) x ,ξ y ) = - Δ φ (x, y); with module i as a positive charge i, area A i As quantity of electric charge q i By phi i ＝φ(x i ,y i ) And xi i ＝ξ(x i ,y i ) Are respectively shown inElectric potential and field at charge i, charge i being dependent on electric field force F i ＝q i ξ i Move with system potential energy of
Figure FDA0003849535620000051
Wherein N is i ＝q i φ i Represents the potential energy of charge i; the density constraint is translated into a constraint of the total potential energy N (v) =0 of the electrostatic system.
CN201810543412.8A 2018-05-30 2018-05-30 Method for establishing VLSI global layout model based on Poisson equation explicit solution Active CN108763777B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810543412.8A CN108763777B (en) 2018-05-30 2018-05-30 Method for establishing VLSI global layout model based on Poisson equation explicit solution

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810543412.8A CN108763777B (en) 2018-05-30 2018-05-30 Method for establishing VLSI global layout model based on Poisson equation explicit solution

Publications (2)

Publication Number Publication Date
CN108763777A CN108763777A (en) 2018-11-06
CN108763777B true CN108763777B (en) 2023-02-28

Family

ID=64004604

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810543412.8A Active CN108763777B (en) 2018-05-30 2018-05-30 Method for establishing VLSI global layout model based on Poisson equation explicit solution

Country Status (1)

Country Link
CN (1) CN108763777B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113139361A (en) * 2020-01-19 2021-07-20 上海复旦微电子集团股份有限公司 Global layout method for 2.5D packaged FPGA
CN111539167B (en) * 2020-04-23 2023-02-21 福州立芯科技有限公司 Layout method of ultra-large-scale integrated circuit considering atomization and proximity effect
CN114722670B (en) * 2022-04-02 2023-08-04 电子科技大学 Potential distribution finite difference solving method for two-dimensional electrostatic particle model

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101872377A (en) * 2010-06-12 2010-10-27 清华大学 Method for restraining integrated circuit electricity supply network noise by using decoupling capacitance
CN102323960A (en) * 2011-04-19 2012-01-18 清华大学 Layout module distribution density smoothing method considering degree of overlapping and wire length
CN106980730A (en) * 2017-03-31 2017-07-25 福州大学 VLSI standard cell placement methods based on direct solution technology
CN107526860A (en) * 2017-03-31 2017-12-29 福州大学 VLSI standard cell placement methods based on electric field energy modeling technique
CN107563095A (en) * 2017-09-22 2018-01-09 中国矿业大学(北京) A kind of non-linear layout method of large scale integrated circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014133867A1 (en) * 2013-02-27 2014-09-04 The Regents Of The University Of California Ic layout adjustment method and tool for improving dielectric reliability at interconnects

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101872377A (en) * 2010-06-12 2010-10-27 清华大学 Method for restraining integrated circuit electricity supply network noise by using decoupling capacitance
CN102323960A (en) * 2011-04-19 2012-01-18 清华大学 Layout module distribution density smoothing method considering degree of overlapping and wire length
CN106980730A (en) * 2017-03-31 2017-07-25 福州大学 VLSI standard cell placement methods based on direct solution technology
CN107526860A (en) * 2017-03-31 2017-12-29 福州大学 VLSI standard cell placement methods based on electric field energy modeling technique
CN107563095A (en) * 2017-09-22 2018-01-09 中国矿业大学(北京) A kind of non-linear layout method of large scale integrated circuit

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
An Analytical Placer for VLSI Standard Cell Placement;Jianli Chen 等;<IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS>;20120712;第31卷(第8期);第1208-1211页 *
ePlace: Electrostatics Based Placement Using Nesterov"s Method;Jingwei Lu 等;《2014 51st ACM/EDAC/IEEE Design Automation Conference》;20140821;第1-6页 *
VEAP:基于全局优化的有效VLSI布局算法;孔天明 等;《半导体学报》;19970908;第18卷(第9期);第692-700页 *
超大规模集成电路的布局算法研究;梁多勇;《中国优秀博硕士学位论文全文数据库(硕士) 信息科技辑》;20120315(第3期);第I135-162页 *

Also Published As

Publication number Publication date
CN108763777A (en) 2018-11-06

Similar Documents

Publication Publication Date Title
Zhang et al. A hybrid boundary node method
Liu et al. Model-reduced variational fluid simulation
CN108763777B (en) Method for establishing VLSI global layout model based on Poisson equation explicit solution
Fabritius et al. Improving the quality of finite volume meshes through genetic optimisation
CN113158527B (en) Method for calculating frequency domain electromagnetic field based on implicit FVFD
Zhang et al. Meshless regular hybrid boundary node method
Kelly et al. Numerical solution of the two-phase incompressible Navier–Stokes equations using a GPU-accelerated meshless method
CN109726465A (en) The three-dimensional method for numerical simulation streamed without viscous low speed based on non-structural curl grid
Yin et al. Isogeometric bi-directional evolutionary structural optimization
Barral et al. Anisotropic mesh adaptation in Firedrake with PETSc DMPlex
CN115577604A (en) Simulation method and system for quickly constructing overall matrix and related equipment
Wang et al. A projective transformation-based topology optimization using moving morphable components
Ghiu et al. Discrete diagonal recurrences and discrete minimal submanifolds
Brański et al. Galerkin Versions of Nonsingular Trefftz Method Derived from Variational Formulations for 2D Laplace Problem
Xu et al. Parallelizing a high-order CFD software for 3D, multi-block, structural grids on the TianHe-1A supercomputer
Poursalehi et al. An adaptive mesh refinement approach for average current nodal expansion method in 2-D rectangular geometry
Safinejad et al. A local meshless RBF method for solving fractional integro-differential equations with optimal shape parameters
Galbraith et al. A Discontinuous Galerkin Chimera scheme with implicit artificial boundaries
Spekreijse et al. Semi-automatic domain decomposition based on potential theory
Wen et al. Space–Time Conservation Element and Solution Element Method: Advances and Applications in Engineering Sciences
Habibi et al. Extending a new two-grid waveform relaxation on a spatial finite element discretization
Gong Immersed-interface finite-element methods for elliptic and elasticity interface problems
Yang et al. A fast iterated orthogonal projection framework for smoke simulation
Bouchon et al. An immersed method based on cut-cells for the simulation of 2d incompressible fluid flows past solid structures
Cui et al. The asymptotic concentration approach combined with isogeometric analysis for topology optimization of two-dimensional linear elasticity structures

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant