CN103745057A - Logical unit packing method for performing electronic design automation in FPGA (Field Programmable Gate Array) - Google Patents
Logical unit packing method for performing electronic design automation in FPGA (Field Programmable Gate Array) Download PDFInfo
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Abstract
The invention discloses a logical unit packing method for performing electronic design automation in an FPGA (Field Programmable Gate Array), mainly aiming to solve the problems of over big time delay of a circuit after packing and excessive consumption of configurable logical units (CLBs). A packing process comprises the following steps: representing a circuit which is subjected to process mapping and unit partition as a directed acyclic graph; initializing time delay information in the directed acyclic graph through a connecting way among look up tables (LUTs) in the circuit; computing the shatter value of each node through a breadth-first traversal method, and computing the criticality of each node in combination with the influence of each node on a key path of the circuit; computing the net gain value of each LUT according to the criticality of each node in combination with the number of nets of the LUTs and the number of nets used in the CLBs, and selectively filling the LUTs according to the net gain values. By adopting the logical unit packing method, the time delay of a final circuit is reduced greatly. Meanwhile, the number of the CLBs consumed in the final circuit is reduced greatly.
Description
Technical field
The invention belongs to field of computer technology, particularly a kind of electric design automation design vanning packaging method, can be used for isomorphism, the application design of the multiple fpga chip such as isomery.
Background technology
The mid-80, first U.S. Xilinx company has released FPGA FPGA, and it is the product further developing on the basis of programmable logic array PLA and generic array logic GAL.Along with the deep-submicron manufacturing technology of integrated circuit and developing rapidly of designing technique, integrated circuit has entered the system-level SOC epoch.The FPGA of 1,000,000 Virtex series that Xilinx company releases, for resolution system level design problem provides new FPGA platform.At present, the designing technique of external FPGA and processing technology are ripe, and product is covering extensive fields, and up to a hundred series of products can be provided, and chip integration has reached doors up to a million, and is widely used in the national defence fields such as communication, space flight, aviation, navigation, remote sensing, remote measurement.The company monopolizings such as U.S. Xilinx, Altera, Lattice and Actel global programmable logic device (PLD) market.And the development of domestic chip is substantially in the poor and underdeveloped stage, there is no the core process technology of autonomous property right, so it is very urgent to research and develop the autonomous fpga chip of China.
Use fpga chip must have the electronic design automation software of supporting FPGA exploitation, the design cycle of the electronic design automation software of exploitation based on FPGA comprises: logic synthesis, Technology Mapping, dividing elements, logical block vanning, layout, wiring, the steps such as program downloads, as shown in Figure 1.Wherein:
Net table is optimized, and for realizing the logic of eliminating redundancy, reduces the actual required area of circuit;
Technology Mapping, for the net table after optimizing is converted into the circuit being comprised of question blank LUT and timing unit, realizes and meeting under the condition of input constraint, more combinational logic is put into a question blank LUT, to reduce the capacity of required FPGA;
Dividing elements, for scale being surpassed to the LUT integrated unit of FPGA capacity, is divided into the several little LUT unit groups that can put into respectively in given FPGA;
Logical block vanning, be used for according to the interconnection Delay between the LUT unit group after dividing, calculate the interconnect delay between LUT and calculate the weighted value of each LUT, then according to the size of weighted value, LUT is sorted, LUT unit is cased in configurable logic cell CLB in order successively one by one;
Layout, for each logical place to actual FPGA by the CLB unit maps after vanning, to reach the stagger ratio that reduces line between CLB, alleviates the pressure of interconnect module;
Wiring, couples together for realizing the interconnection resources that adopts FPGA inside to exist each connection between CLB, and whole circuit is mapped completely on given fpga chip;
Coding is downloaded, and the circuit having shone upon according to wiring, generates the bit data stream file that will use by compiling, then this data file is downloaded in fpga chip.
Described logical block vanning, conventionally depend on the structure of FPGA, popular FPGA structure is exactly inner containing multiple queries table LUT at a configurable logic cell CLB at present, between these question blanks LUT, share input, their output simultaneously also can feed back to input end by interconnect resource.Existing logical block packing method is divided into following two kinds substantially:
A kind of is by sacrificing the quantity of configurable logic cell CLB, to improve the delay performance of final circuit, T-vpack logical block packing method for example, the method is exactly in the calculation delay stage, by backtracking repeatedly, to calculate to improve the time delay of final circuit, after each question blank LUT has been loaded, capital goes the Delay of whole circuit to upgrade, and calculates the corresponding time delay weights of question blank LUT simultaneously.Although this method can guarantee the efficient of circuit time delay performance, but there is no the area to final circuit, the quantity of the configurable logic cell CLB consuming is carried out good optimal control, and the configurable logic cell CLB that makes to be finally loaded into the circuitry consumes on FPGA development board is too much.
Another kind is that the configurable logic cell CLB that the delay performance by sacrifice circuit reduces final circuit consumes, R-pack logical block packing method for example, the method is exactly to the question blank LUT packing of casing using the number of final circuitry consumes configurable logic cell CLB as primary optimization aim, and in order to guarantee the continuity to question blank LUT vanning, in the calculation delay stage, the Delay of circuit is not carried out to backtracking renewal.Though this method is in the situation that guaranteeing that question blank LUT loads continuously, can fully control the quantity of the configurable logic cell CLB of final circuitry consumes, but ignored the guarantee to circuit final delay performance, the circuit that makes to be finally loaded on FPGA development board is long working time.
Summary of the invention
The object of the invention is to the deficiency for above-mentioned prior art, propose to carry out in a kind of FPGA the logical block packing method of electric design automation, to consider the quantity of the final delay performance of circuit and the configurable logic cell CLB of consumption, make final design circuit out reach high as far as possible performance.
The technical scheme that realizes the object of the invention, comprises the steps:
A. the crucial degree B of each question blank LUT in counting circuit:
(A1) will be through Technology Mapping, the circuit after dividing elements is processed is as a directed acyclic graph DAG, and the node in this directed acyclic graph represents to have the question blank LUT of memory circuit logic function; Limit in directed acyclic graph represents the gauze line between question blank LUT, according to the actual annexation between question blank LUT, upper corresponding time delay weighted value is composed in every limit in directed acyclic graph;
(A2) from the source node of circuit, according to the corresponding time delay weighted value in limit in directed acyclic graph, the method that adopts breadth First to travel through calculates Ta time of arrival the latest (i) of node i in directed acyclic graph, wherein i represents the label of i node in directed acyclic graph, the span of i is 1～N, the sum of node in N indication circuit, the input of node i is In (i) expression for node set, node sum in set In (i) represents with e1, the output node of node i is On (i) expression for set, and the node sum in set On (i) represents with e2;
(A3), from the endpoint node of circuit, in conjunction with every time delay weighted value that limit is corresponding, what adopt that the method for breadth First traversal calculates node i in directed acyclic graph needs to reach time T r (i) the latest;
(A4), according to Ta time of arrival the latest (i) of node i in the directed acyclic graph obtaining with need the latest to reach time T r (i), obtain shatter value corresponding to node i: s (i)=Tr (i)-Ta (i);
(A5) according to shatter value, calculate the time ductility of node i in directed acyclic graph: C (i)=1-s (i)/Ms, wherein Ms represents the maximal value of all node shatter values in directed acyclic graph;
(A6) calculate the affect weights of node i on critical path in directed acyclic graph:
TA(i)＝IA(i)+OA(i)，
Wherein: IA (i) represents the node sum of the corresponding input node of node i in critical path, OA (i) represents the node sum of the corresponding output node of node i in critical path;
(A7) according to time ductility C (i) and this node of node i critical path in directed acyclic graph affected to weights TA (i), the crucial degree of computing node i:
wherein
B. select question blank LUT to be loaded into new configurable logic cell CLB:
(B1) the crucial degree for resulting each node in step (A7) sorts, and selects the corresponding question blank LUT of that node that crucial degree is the highest, is filled in a new configurable logic cell CLB and goes;
(B2) the question blank LUT being loaded in configurable logic cell CLB is labeled as to H, calculate the associated gain of the gauze I (j) of j the question blank LUT being connected with H, wherein j represents j the question blank LUT being connected with H, the span of j is 1～M, and M represents total number of the question blank LUT that is connected with H;
(B3) the associated yield value I of the gauze of all question blank LUT that calculate (j) is sorted, that question blank LUT of the associated yield value maximum of selection gauze is filled in above-mentioned new configurable logic cell CLB to be gone;
(B4) repeating step (B2) and step (B3), until above-mentioned new configurable logic cell CLB is loaded completely;
C. refresh circuit Delay, continues question blank LUT to load:
(C1) for one, loaded full configurable logic cell CLB, according to the connected mode of other question blanks LUT in it and circuit, reset the time delay weighted value on limit in circuit, formed new directed acyclic graph DAG ';
(C2) utilize new directed acyclic graph DAG ', repeating step (A2) and step (B4), until all question blank LUT have been loaded in circuit.
The present invention compared with prior art institute's tool has the following advantages:
(1) the present invention is when selecting question blank LUT to be loaded into new configurable logic cell CLB, by calculating the method for the associated gain of gauze, question blank LUT is selected, space in configurable logic cell CLB can be utilized fully, reduced the quantity of using configurable logic cell CLB;
(2) the present invention carries out overall renewal to the Delay of circuit in vanning process, after having a configurable logic cell CLB to be loaded completely, according to the connected mode of other question blanks LUT in it and circuit, recalculate the time delay weighted value on limit in circuit, make the delay of final circuit reach optimum, reduced circuit final working time.
Accompanying drawing explanation
Fig. 1 is the existing process flow diagram that carries out automatic electronic design in FPGA;
Fig. 2 is that whole vanning of the present invention realizes general flow chart;
Fig. 3 is the crucial degree sub-process figure that calculates whole circuit question blank LUT in the present invention;
Fig. 4 selects according to the crucial degree of question blank LUT the sub-process figure loading in the present invention.
Embodiment
With reference to Fig. 2, performing step of the present invention is as follows:
Step 1, will be through Technology Mapping, and the circuit after dividing elements is processed is set to directed acyclic graph DAG.
Technology Mapping is that circuit is converted into question blank LUT integrated unit, if the scale of this integrated unit has surpassed the capacity of FPGA, to question blank LUT integrated unit be divided into a plurality of question blank LUT unit groups that can put in given FPGA by dividing elements.Because this unit group is interconnected and formed by multiple queries table LUT, therefore this circuit can be regarded as to a directed acyclic graph DAG, be in circuit, the question blank LUT with memory circuit logic function to be regarded as to a node in directed acyclic graph, regard the gauze line between question blank LUT as limit in directed acyclic graph;
According to the annexation between question blank LUT, upper corresponding time delay weighted value is composed in every limit in directed acyclic graph, in this example directed acyclic graph, the time delay weighted value on all limits is set to 0.1.
Step 2, the crucial degree of each question blank LUT in counting circuit, the i.e. crucial degree B of each node in directed acyclic graph:
With reference to Fig. 3, being achieved as follows of this step:
(2a) adopt the method for breadth First traversal calculate Ta time of arrival the latest (i) of node i in directed acyclic graph and need the latest to reach time T r (i), wherein i represents the label of i node in directed acyclic graph, the span of i is 1～N, the sum of node in N indication circuit:
(2a1) the input node set of establishing node i is In (i), and the node sum in set In (i) represents with e1, and the output node set of node i is On (i), and the node sum in set On (i) represents with e2;
(2a2) from the source node of circuit, the time of arrival the latest of calculating node i in directed acyclic graph in conjunction with every time delay weighted value corresponding to limit:
Ta(i)＝max{Ta(m)+t(m,i)}，
Wherein m represents m node in the input node set In (i) of node i, and the span of m is: 1～e1; T (m, i) represents the time delay weighted value between node i in m node in set In (i) and directed acyclic graph;
(2a3), from the endpoint node of circuit, that in conjunction with time delay weighted value corresponding to every limit, calculates node i in directed acyclic graph needs to reach the time the latest:
Tr(i)＝min{Tr(n)-t(i,n)}，
Wherein n represents n node in the output node set On (i) of node i, and the span of n is: 1～e2; T (i, n) represents n node in set On (i) and the time delay weighted value between the node i in directed acyclic graph;
(2b), according to Ta time of arrival the latest (i) of node i in the directed acyclic graph obtaining with need the latest to reach time T r (i), obtain the shatter value of node i: s (i)=Tr (i)-Ta (i);
(2c) according to shatter value, calculate the time ductility of node i in directed acyclic graph:
C(i)＝1-s(i)/Ms，
Wherein Ms represents the maximal value of all node shatter values in directed acyclic graph;
(2d) calculate the affect weights of node i on critical path in directed acyclic graph:
TA(i)＝IA(i)+OA(i)，
Wherein: IA (i) represents the node sum of the corresponding input node of node i in critical path, OA (i) represents the node sum of the corresponding output node of node i in critical path;
(2e) according to time ductility C (i) and this node of node i critical path in directed acyclic graph affected to weights TA (i), the crucial degree of computing node i:
wherein
Step 3, selects question blank LUT, and is loaded into new configurable logic cell CLB.
With reference to Fig. 4, being achieved as follows of this step:
(3a) the crucial degree of resulting each node in step (2e) is sorted, select the corresponding question blank LUT of that node that crucial degree is the highest, be filled in a new configurable logic cell CLB and go;
(3b) the question blank LUT of above-mentioned filling is labeled as to H, continues to select other question blank LUT to be filled in above-mentioned configurable logic cell CLB:
(3b1) calculate the associated gain of the gauze I (j) of j the question blank LUT being connected with H:
(3b11) calculate the gauze weights of j question blank LUT:
w(j)＝2.0/k，
Wherein k represents the gauze sum of j question blank LUT; J represents the label of j question blank LUT being connected with H, and the span of j is 1～M; M represents total number of the question blank LUT that is connected with H;
(3b12), according to the gauze weight w (j) of j the question blank LUT obtaining, calculate the gauze gain of j question blank LUT:
I(j)＝μ*w(j)*(1+a)，
Wherein, a represents the shared gauze number of configurable logic cell CLB under j question blank LUT and H, H is the question blank LUT being loaded in configurable logic cell CLB, μ represents gauze gain coefficient, in the time of in configurable logic cell CLB under the gauze of j question blank LUT is all comprised in H, the value of μ is 10.0, otherwise the value of μ is 1.0;
(3b2) the associated yield value I of the gauze of all question blank LUT that obtain (j) is sorted, select that question blank LUT of the associated yield value maximum of gauze, be filled in above-mentioned new configurable logic cell CLB and go;
(3c) repeating step (3b), until above-mentioned new configurable logic cell CLB is loaded completely;
(3d) refresh circuit Delay, continues question blank LUT to load:
(3d1) for one, loaded full configurable logic cell CLB, according to the connected mode of other question blanks LUT in it and circuit, the time delay weighted value of the gauze line between question blank LUT in this CLB is re-set as to 1.0, forms new directed acyclic graph DAG ';
(3d2) utilize new directed acyclic graph DAG ', repeating step 2 and step 3, until all question blank LUT have been loaded in circuit, whole vanning process finishes.
After finishing, whole vanning process enters FPGA electric design automation layout's stage, the configurable logic cell CLB unit maps that is about to form arrives each logical place of FPGA, to reduce the stagger ratio of line between configurable logic cell CLB, adequately and reasonably utilize existing resource on FPGA development board.
Effect of the present invention can be by following emulation experiment further instruction
1. simulated conditions
Select the large-scale circuit after Technology Mapping and dividing elements instrument ABC processing in international standard circuit
2. emulation content
By above-mentioned large mould rule circuit after Technology Mapping and dividing elements are processed, adopt respectively packing method of the present invention and in the world conventional T-vpack packing method carry out emulation experiment, time delay and area result that the circuit after casing is added up respectively to them.Wherein time delay represents the length in final circuit critical path, and it has determined this circuit final working time; The number of the configurable logic cell CLB that the final circuit of cartographic represenation of area will be used.
Each emulation repeats 20 times, and the simulation experiment result is averaged, and obtains two kinds of method simulation comparisons, as shown in table 1:
The result contrast of table 1 packing method of the present invention and existing T-vpack packing method
As can be seen from Table 1, aspect area, packing method of the present invention is better than T-vpack packing method, and final total area result has improved 1.5%; Aspect time delay, the handled circuit of the present invention is also better than the result of T-vpack, and final total time delay result has improved 5.8%.
According to above emulation experiment and data result, show, the present invention has considered the factor that affects circuit time delay and area in the vanning process on circuit, when the Delay to circuit of the overall situation upgrades, also considered to use the situation of configurable logic cell CLB in filling process, adopt the method for calculating gauze gain to select to load to question blank LUT, made the time delay of final circuit and two important performance indexes of area all obtain and significantly improve.
Claims (5)
1. a logical block packing method that carries out electric design automation in FPGA, comprises the steps:
A. the crucial degree B of each question blank LUT in counting circuit:
(A1) will be through Technology Mapping, the circuit after dividing elements is processed is as a directed acyclic graph DAG, and the node in this directed acyclic graph represents to have the question blank LUT of memory circuit logic function; Limit in directed acyclic graph represents the gauze line between question blank LUT, according to the actual annexation between question blank LUT, upper corresponding time delay weighted value is composed in every limit in directed acyclic graph;
(A2) from the source node of circuit, according to the corresponding time delay weighted value in limit in directed acyclic graph, the method that adopts breadth First to travel through calculates Ta time of arrival the latest (i) of node i in directed acyclic graph, wherein i represents the label of i node in directed acyclic graph, the span of i is 1～N, the sum of node in N indication circuit, the input of node i is In (i) expression for node set, node sum in set In (i) represents with e1, the output node of node i is On (i) expression for set, and the node sum in set On (i) represents with e2;
(A3), from the endpoint node of circuit, in conjunction with every time delay weighted value that limit is corresponding, what adopt that the method for breadth First traversal calculates node i in directed acyclic graph needs to reach time T r (i) the latest;
(A4), according to Ta time of arrival the latest (i) of node i in the directed acyclic graph obtaining with need the latest to reach time T r (i), obtain shatter value corresponding to node i: s (i)=Tr (i)-Ta (i);
(A5) according to shatter value, calculate the time ductility of node i in directed acyclic graph: C (i)=1-s (i)/Ms, wherein Ms represents the maximal value of all node shatter values in directed acyclic graph;
(A6) calculate the affect weights of node i on critical path in directed acyclic graph:
TA(i)＝IA(i)+OA(i)，
Wherein: IA (i) represents the node sum of the corresponding input node of node i in critical path, OA (i) represents the node sum of the corresponding output node of node i in critical path;
(A7) according to time ductility C (i) and this node of node i critical path in directed acyclic graph affected to weights TA (i), the crucial degree of computing node i:
wherein
B. select question blank LUT to be loaded into new configurable logic cell CLB:
(B1) the crucial degree for resulting each node in step (A7) sorts, and selects the corresponding question blank LUT of that node that crucial degree is the highest, is filled in a new configurable logic cell CLB and goes;
(B2) the question blank LUT being loaded in configurable logic cell CLB is labeled as to H, calculate the associated gain of the gauze I (j) of j the question blank LUT being connected with H, wherein j represents j the question blank LUT being connected with H, the span of j is 1～M, and M represents total number of the question blank LUT that is connected with H;
(B3) the associated yield value I of the gauze of all question blank LUT that calculate (j) is sorted, that question blank LUT of the associated yield value maximum of selection gauze is filled in above-mentioned new configurable logic cell CLB to be gone;
(B4) repeating step (B2) and step (B3), until above-mentioned new configurable logic cell CLB is loaded completely;
C. refresh circuit Delay, continues question blank LUT to load:
(C1) for one, loaded full configurable logic cell CLB, according to the connected mode of other question blanks LUT in it and circuit, reset the time delay weighted value on limit in circuit, formed new directed acyclic graph DAG ';
(C2) utilize new directed acyclic graph DAG ', repeating step (A2) and step (B4), until all question blank LUT have been loaded in circuit.
2. packing method according to claim 1, adopts Ta time of arrival the latest (i) of node i in the method counting circuit of breadth First traversal in wherein said (A2), by following formula, calculate:
Ta(i)＝max{Ta(m)+t(m,i)}，
Wherein m represents m node in the input node set In (i) of node i, and the span of m is: 1～e1; T (m, i) represents the time delay weighted value between node i in m node in set In (i) and directed acyclic graph.
3. packing method according to claim 1, in wherein said (A3), adopt method of breadth First traversal calculate node i in directed acyclic graph need the latest reach time T r (i), by following formula, calculate:
Tr(i)＝min{Tr(n)-t(i,n)}，
Wherein n represents n node in On (i) in the output node set of node i, and the span of n is: 1～e2; T (i, n) represents the time delay weighted value between node i in n node in set On (i) and directed acyclic graph.
4. packing method according to claim 1, calculates the associated gain of gauze I (j) of j the question blank LUT being connected with question blank LUTH in wherein said (B2), carry out as follows:
(B21) calculate the gauze weights of j question blank LUT:
w(j)＝2.0/k，
Wherein k represents the gauze sum of j question blank LUT;
(B22), according to the gauze weights of j the question blank LUT obtaining, calculate the gauze gain of j question blank LUT:
I(j)＝μ*w(j)*(1+a)，
Wherein, a represents the shared gauze number of configurable logic cell CLB under j question blank LUT and H, H is the question blank LUT being loaded in configurable logic cell CLB, u represents gauze gain coefficient, in the time of in configurable logic cell CLB under the gauze of j question blank LUT is all comprised in H, the value of u is 10.0, otherwise the value of u is 1.0.
5. packing method according to claim 1, in wherein said (C1), reset the time delay weighted value on limit in circuit: for one, loaded full configurable logic cell CLB, according to the connected mode of other question blanks LUT in it and circuit, the time delay weighted value of the gauze line between question blank LUT in this CLB is re-set as to 1.0, forms new directed acyclic graph DAG '.
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| CN109284578A (en) * | 2018-02-27 | 2019-01-29 | 上海安路信息科技有限公司 | Logic circuit layout wiring method, graphic software platform method and its system |
| CN109284578B (en) * | 2018-02-27 | 2021-06-01 | 上海安路信息科技股份有限公司 | Logic circuit layout and wiring method, graphical display method and system thereof |
| CN112948323A (en) * | 2021-04-16 | 2021-06-11 | 山东高云半导体科技有限公司 | Memory mapping processing method and device and FPGA chip |
| CN115017844A (en) * | 2022-08-03 | 2022-09-06 | 阿里巴巴（中国）有限公司 | Design parameter adjusting method and device, electronic equipment and storage medium |
| CN115017844B (en) * | 2022-08-03 | 2022-11-08 | 阿里巴巴（中国）有限公司 | Design parameter adjusting method, device, electronic equipment and storage medium |
| CN115862052A (en) * | 2023-02-24 | 2023-03-28 | 北京芯愿景软件技术股份有限公司 | Method, device, equipment and storage medium for automatically identifying clock crossing circuit |
| CN116187265A (en) * | 2023-04-28 | 2023-05-30 | 南方科技大学 | Chip design method and terminal |
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