CN115455890B

CN115455890B - Schematic diagram layout method for heuristic row and column positioning

Info

Publication number: CN115455890B
Application number: CN202211130138.4A
Authority: CN
Inventors: 胡志; 黄非凡
Original assignee: Shenzhen Huaxinsheng Software Technology Co ltd
Current assignee: Shenzhen Huaxinsheng Software Technology Co ltd
Priority date: 2022-09-15
Filing date: 2022-09-15
Publication date: 2024-07-16
Anticipated expiration: 2042-09-15
Also published as: CN115455890A

Abstract

The invention discloses a heuristic line-column positioning schematic diagram layout method, which comprises the following steps of firstly calculating strong communication branches, then laying out a single strong communication branch, laying out a directed acyclic graph, and finally carrying out channel estimation and position calculation, thereby designing and realizing automatic layout of the schematic diagram. By using the ideas of strong communication branching algorithm and force guiding, the time complexity of layout is effectively reduced, and the number of intersections is reduced.

Description

Schematic diagram layout method for heuristic row and column positioning

Technical Field

The invention relates to the technical field of EDA design, in particular to a schematic diagram layout method for heuristic row and column positioning.

Background

Electronic design automation (EDA-Electronic Design Automation) refers to the design model of very large scale integrated circuits that utilizes computer aided design software to implement a full process.

With the increase of the complexity of chip circuit design, high-level design methods are attracting attention. The use of schematic diagrams is critical to the design and can significantly improve the interactivity during the design process. Early chip designers manually drawn logic diagrams based on feedback from electronic design automation tools, which were inefficient and prone to errors. The automatic drawing tool of the circuit schematic diagram not only can rapidly and accurately draw the corresponding logic circuit schematic diagram according to the circuit netlist, is convenient for a designer to understand the circuit, shortens the development period of the circuit design, and can be used as a development document of the circuit design to be preserved.

The automatic generation algorithm of the schematic diagram includes a layout part and a wiring part. The layout algorithm of the current schematic diagram mainly adopts a row-column positioning method, and good layout brings better wiring effect. In the prior art, an incidence matrix is introduced, the intersection is reduced by iterating the incidence matrix, and the time complexity of one iteration is as high as O (n-4); another known technique, implementing the layout in a circuit-driven step-by-step manner, does not mention how to deal with the feedback loop present in the circuit; another known technique applies queuing techniques to the layout, but does not allow layout of the looped circuit diagram; another known technique implements a layout using a grading algorithm and a PO cone, the grading algorithm involves the computation of a circuit feedback loop, and the algorithm is not applicable to a set of unordered elements.

In summary, the known art has at least the following drawbacks and disadvantages:

(1) For a schematic diagram with a feedback loop, the algorithm time complexity is high;

(2) The layout of the ring circuit is not supported;

(3) Not applicable to a group of cluttered elements;

(4) The elements are the same in size or different in width and height.

Therefore, in order to solve the defects in the prior art, it is highly desirable to provide a method for implementing automatic layout of schematic diagrams, which avoids calculation of feedback loops, reduces time complexity of layout, supports different sizes of elements of the schematic diagrams, reduces the number of intersections, and designs and implements an automatic layout system of the schematic diagrams.

Disclosure of Invention

The invention discloses a schematic diagram layout method for heuristic row and column positioning, and aims to provide a method for realizing automatic layout of a schematic diagram. The invention introduces the concept of strong communication branches, converts the cyclic schematic diagram into the acyclic schematic diagram, and realizes the conversion of complex problems. In addition, a vertical grading algorithm is used, the left-right relationship of the vertexes is determined according to the degrees of the vertexes and the connection relationship, and therefore the grade number of the element is obtained. The determination of the row position depends to a large extent on the vertical placement order of the first column of elements, in order to reduce the number of line crossings, the final effect of influencing the layout due to the placement of the first column of elements is avoided as much as possible by iterative ideas.

In order to achieve the above purpose, the present invention adopts the following technical scheme:

The invention provides a heuristic line and row positioning schematic diagram layout method, which is characterized by comprising the following steps:

Step S1: analyzing data;

Step S2: the algorithm is based on depth-first search of the graph, the non-visited vertexes are searched by searching the depth-first, the vertexes are placed in a stack according to the access order, a time stamp (DNF) and a trace back value (LOW) are set, and then other nodes are sequentially visited according to the edge connection relation. If the edge of the vertex is traversed, the vertex is popped, and a group of popped vertices can be used as a strong communication branch by utilizing the traceability value and the timestamp;

Step S3: judging whether the number of the strong communication branches is equal to the number of the nodes of the graph, if the number of the strong communication branches is equal to the number of the nodes of the graph, directly entering a step S5, directly laying out the directed acyclic graph, otherwise, if the number of the strong communication branches is not equal to the number of the nodes of the graph, entering a step S4, laying out single strong communication branches, contracting each strong communication branch into a point after finishing the layout of each single strong communication branch, splicing to form the directed acyclic graph, and entering the step S5;

Step S4: for the layout of a single strong communication branch, calculating a sub-graph corresponding to the strong communication branch, scanning all directed edges of the directed graph, if the starting point and the ending point of the directed edge are in the single strong communication branch, the edge belongs to the sub-graph where the strong communication branch is located, and calculating the level where all vertexes are located by traversing the edge of the sub-graph;

step S5: and for the directed acyclic graph layout, scanning and grading the directed acyclic graph according to a topological ordering mode. After the column number of the vertexes is determined, calculating the average weight of each level of vertexes in an iterative mode to obtain the number of rows of each vertex, sequencing according to the average weight, and placing the vertexes according to the sequencing result;

Step S6: channel estimation and position calculation.

Further, the data analysis in the step S1 specifically includes: logic netlists have many descriptive forms, the same physical meaning of netlist format representation of different forms, and circuit structure, because Electronic Design Interchange Format (EDIF) is supported by most Computer Aided Design (CAD) tools, and EDIF is used herein as input data to store the data using a contiguous table of Graph model g= < V, E >.

Further, the adjacency list is a storage structure combining sequential allocation and chained allocation, is a most main storage structure of the graph, and is used for describing each point in the graph.

Further, the step S2 specifically includes the following steps:

step S21: searching a vertex u for the first time, and setting a time stamp DFN [ u ] and a tracing value LOW [ u ] of the vertex u as time;

Step S22: pressing the vertex u into a stack, and modifying the time to be time+1;

Step S23: each edge with u end point v is traversed, if the vertex v is not visited, the process goes to step S21. During backtracking, modifying the tracking value LOW [ u ] of the vertex u into the smaller one of the tracking values LOW [ u ] and LOW [ V ]; at search time, if vertex v is in stack, modifying the trace back value of u, LOW [ u ], to be the smaller of LOW [ u ] and DFN [ v ];

step S24: if DFN [ u ] and LOW [ u ] are the same and u and v are different, v is popped off the stack, where v is a vertex in the strongly connected branch.

Further, the time stamp DFN refers to that in the dfs process of the graph, the time ranking of each point accessed for the first time is the time stamp DFN. The trace back value LOW refers to that, for each point, the trace back value of the point is the minimum value of the time stamps of all points which can reach the point through an edge which is not on the search tree in the subtree taking the point as the root.

Further, the step S4 specifically includes the following steps:

step S41: calculating a sub graph G1= < V1, E1> corresponding to a single strong communication branch, traversing each edge E of the edge set, and if the starting point u and the ending point V of the edge E are both in the vertex set V1 of the strong communication branch, putting the edge E into the edge set E1;

Step S42: calculating the output degrees of all vertexes according to the edge set E1, and placing the vertex with the largest output degree in the kth column;

step S43: symmetrically placing the child nodes which are not placed in the (k+1) th row according to the positions of the vertices of the (k) th row, and continuing the step S42 until all the vertices are completely placed;

Step S44: and finally, the relative positions of all vertexes of the strong communication branch can be obtained.

Further, the step S5 specifically includes the following steps:

step S51: calculating the degree of incidence of each vertex in the directed acyclic graph, and setting the number of stages of the vertex with zero degree of incidence;

Step S52: removing the edge related to the vertex u with zero degree, wherein the graph is not blank, and jumping to the step S51, otherwise jumping to the step S53;

step S53: obtaining vertexes contained in the ith stage and the (i+1) th stage according to the stages of the vertexes, and setting weights for the elements of the ith stage according to the position relation;

Step S54: scanning all the edges e, and if the starting point u of the edge e is in the ith stage and the finishing point v is in the (i+1) th stage, updating the weight sum of the (i+1) th stage;

step S55: calculating the average weight of the (i+1) -th vertex according to the weight sum of the (i+1) -th vertex and the incidence of the vertex;

step S56: sorting the (i+1) th-stage vertexes according to average weights, and placing vertexes according to sorting results;

Step S57: setting weights according to the placement sequence of the (i+1) th level;

Step S58: scanning all the edges e, if the starting point u of the edge e is at the ith stage and the finishing point v is at the (i+1) th stage, updating the weight sum of the vertexes u, and calculating the average weight of the vertexes of the ith stage according to the weight sum of the vertexes of the ith stage and the degree of emergence of the vertexes;

Step S59: step S54 to step S58 are performed a plurality of times;

step S510: step S54 is executed, in which the average weight of the (i+1) th level is calculated according to the weight of the i th level and the connection relationship between the i th level and the (i+1) th level, the order is performed according to the average weight, and the vertices are placed according to the order result.

Further, the average weight=weight and/or ingress or average weight=weight and/or egress.

Further, the step S6 includes the steps of:

step S61: calculating the row and column widths of the elements, wherein the size of the row (column) of the elements is the maximum value of the heights (widths) of all the elements in the row (column);

step S62: calculating the distance between the rows (columns) of the elements, scanning the connection relation among all the elements, and increasing the channel weight value between the columns and the rows for one connection relation;

step S63: the element location in a row (column) is determined by the weight of the channel between the element in the row (column) and the zeroth row (column) and the width of all rows above the element (column width), placing the element in a position centered in the row.

According to the heuristic line-row positioning schematic diagram layout method, through the adoption of a strong communication branch algorithm and a force guiding idea, calculation of a feedback loop is avoided, and time complexity of layout is reduced; and the sizes of the elements supporting the schematic diagram are different; meanwhile, the iteration and force guiding ideas are used for reference, so that the line crossing is effectively reduced, an automatic layout system of the schematic diagram can be automatically realized, the layout efficiency of a large-scale schematic diagram is high, the layout is reasonable, and the subsequent wiring is convenient.

Drawings

FIG. 1 is a schematic diagram layout method flow chart of heuristic row-column positioning according to the present invention;

fig. 2 is a schematic diagram illustrating parsing according to a given EDIF file;

FIG. 3 is an adjacency list corresponding to the schematic diagram of FIG. 2;

FIG. 4 is an illustration showing a process of computing strongly connected branches;

FIG. 5 is a schematic drawing of a vertex F pop;

FIG. 6 is a schematic drawing of a vertex E pop;

FIG. 7 is a schematic diagram of a push of node D;

FIG. 8 is a schematic diagram of the return from node D to node C;

FIG. 9 is a schematic diagram of the traversal completion of all nodes;

FIG. 10 is a sub-graph corresponding to the strong communication branch of FIG. 4;

FIG. 11 is a schematic layout of all vertices for a single strongly connected branch;

FIG. 12 is a directed acyclic graph for a grading presentation;

FIG. 13 is a graph of degree of ingress and egress for all vertices of the directed acyclic graph of FIG. 12;

FIG. 14 is a directed acyclic graph with first-stage vertices and associated directed edges removed;

FIG. 15 is a series of all vertices of FIG. 12;

FIG. 16 is a schematic diagram of the directed acyclic graph stage 1 element setting weights;

FIG. 17 is an average weight of the level 2 of the directed acyclic graph;

FIG. 18 is a graph showing the calculation of the class 1 vertex average weights based on the class 2 vertex weights;

FIG. 19 is a graph showing the calculation of the weights of subsequent vertices based on the post-iteration level 1 vertex weights;

FIG. 20 is a diagram showing the arrangement of the stages according to the average weight;

fig. 21 is a schematic layout diagram (parts a-G).

Detailed Description

The present invention is further described in conjunction with the accompanying drawings and examples to facilitate a more accurate, intuitive, and thorough understanding of the policy design of the present invention by those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced otherwise than as described herein; it will be apparent that the embodiments in the specification are only some, but not all, embodiments of the disclosure.

The figure: a structure used to represent some relationship between an object and a physical object is referred to as a "vertex" and the relationship between an object and an object is referred to as an "edge". Edges may or may not be directional, and if edges are directional, the graph is referred to as a directed graph, otherwise, it is referred to as an undirected graph. The number of edges of each vertex pointing to other vertices is referred to as the out-degree of the vertex, and the number of edges of other vertices pointing to the vertex is referred to as the in-degree of the vertex.

Directed acyclic graph: if a directed graph cannot return to itself from any vertex, the graph is a directed acyclic graph.

Logic netlists have a number of descriptive ways in which Electronic Design Interchange Format (EDIF) is supported by most Computer Aided Design (CAD) tools, and in embodiments of the invention, using electronic design interchange format as input data, a Graph model g= < V, E > adjacency list is employed to store the data.

FIG. 1 is a schematic diagram layout method flowchart of heuristic row-column positioning according to the present invention, specifically comprising:

Step S1: and (5) data analysis. Firstly, in data analysis, according to a given electronic design exchange format file (EDIF file for short), analyzing to obtain a schematic diagram shown in FIG. 2, and describing the connection relation of the schematic diagram by using an adjacency list shown in FIG. 3.

Step S2: a strongly connected branch is calculated. Comprises the following steps of the method,

Step S21 searches the vertex u, and sets the time stamp DFN [ u ] and the tracing value LOW [ u ] of the vertex u as time;

step S22, pressing the vertex u into a stack, and simultaneously modifying the time to be time+1;

step S23, traversing each edge with the starting point of u and the ending point of v, if the vertex v is not accessed, jumping to step S22 and modifying the tracing value LOW [ u ] of the vertex u to be smaller of the tracing values of u and v; if vertex v is in stack, modify the trace back value of u, LOW [ u ], to the smaller of the original LOW [ u ] and LOW [ v ];

Step S24 pops v, where v is a vertex in the strongly connected branch, if DFN [ u ] and LOW [ u ] are the same and u and v are different.

The strong connected branches of the directed graph are calculated beginning below, and the algorithm is a graph-based depth-first search, as shown in FIG. 4, which is an illustration showing the process of calculating strong connected branches. Searching the non-visited vertexes by searching depth first, placing the vertexes in a stack according to the visiting order, setting a time stamp (DFN) and a trace back value (LOW), and visiting other nodes according to the edge connection relation in sequence. If the edge of the vertex is traversed, the vertex is popped, and a group of popped vertices can be judged to be used as a strong communication branch by using the traceback value and the timestamp.

Then the traversal starts for fig. 4, for depth traversal, first starts with a, traverses C, E, traverses all the way to F, finds F to the head, then compares if the current node is DFN [ F ] =low [ F ], finds DFN [ F ] =

LOW f=4, F pops off the stack. All nodes popped out of the stack are the first sub-strong communication branch: { F }, the schematic diagram is shown in FIG. 5, which is the pop of vertex F. Returning to node E, LOW [ E ] =min (LOW [ E ], LOW [ F ])=3, and finding DFN [ E ] =low [ E ] =3, then E is popped. A second sub-strong communication branch is obtained: { E }, the schematic diagram is shown in FIG. 6, which is the pop of vertex E. Returning to node C, obtaining LOW [ C ] =min (LOW [ C ], LOW [ E ])=2, then node C goes to node D, and continues to node a, finding that node a is already inside the stack, indicating that a strong communication branch is found, returning to node D, LOW [ D ] =min (LOW [ D ], DFN [ a ])=1, as shown in fig. 7, to return from node a to node D. After node D walks (node F is not walked since node F is a node that has been traversed and is not inside the stack), it returns to node C, LOW [ C ] =min (LOW [ C ], LOW [ D ])=1, as shown in fig. 8, to return from node D to node C. Then return to node a (not walk node E because node E is also a node that has been traversed and is not inside the stack), LOW [ a ] =min (LOW [ a ], LOW [ C ])=1, then walk node B, walk node D, find node D has been traversed while traversing node D, but node D is inside the stack, then LOW [ B ] =min (LOW [ B ], DFN [ D ])=5, then fall back to node a, the deep walk is completed, as shown in fig. 9, for all nodes being traversed. At this point DFN [ a ] =low [ a ] =1 is found, all nodes in the stack are fetched, forming one connected branch { B, D, C, a }.

Three strongly connected branches can be finally obtained, respectively { F }, { E }, { B, D, C, A }.

Step S3: and judging whether the number of the strong communication branches is equal to the number of nodes of the graph. If the number of the strong communication branches is equal to the number of the nodes of the graph, the step S5 can be directly carried out, otherwise, if the number of the strong communication branches is not equal to the number of the nodes of the graph, the step S4 is carried out, after the layout of each single strong communication branch is finished, each strong communication branch is contracted into a point, the points can be spliced to form a directed acyclic graph, and the step S5 is carried out on the layout of the directed acyclic graph.

Step S4: for a single strongly connected branch layout.

Step S41 calculates the sub graph g1= < V1, E1> corresponding to the single strong communication branch, traverses each edge E of the edge set, and puts the edge E into the edge set E1 if the starting point u and the ending point V of the edge E are both in the vertex set V1 of the strong communication branch;

step S42, calculating the output degrees of all vertexes according to the adjacent table, and placing the vertex with the largest output degree in the kth column;

Step S43 symmetrically places the child nodes not placed in the (k+1) th row according to the positions of the vertices in the (k) th row, and continues to step S42, so as to obtain the relative positions of all vertices of the strongly connected branch.

Taking one strong communication branch { B, D, C, a } of fig. 4 as an example, first, a sub-graph corresponding to the strong communication branch is calculated, all the directed edges of fig. 4 are scanned, if the start point and the end point of the directed edge of fig. 4 are all in { B, D, C, a }, then the edge belongs to the sub-graph where the strong communication branch is located, and after the scanning is finished, the sub-graph corresponding to the strong communication branch is shown in fig. 10. By traversing the edges of the subgraph, the hierarchy where all the vertices are located can be calculated, node A is laid out at the first level with the maximum degree of 2, node B and node C are laid out at the second level symmetrically, and the last node D is laid out at the third level. A layout diagram for a single strongly connected branch B, D, C, a is shown in fig. 11.

Step S5: directed acyclic graph layout. "loop-free" means here a graph derived by contracting each strongly connected branch into a vertex.

Step S51, calculating the degree of entering each vertex in the directed acyclic graph, and setting the number of stages of the vertex with zero degree of entering;

Step S52, removing the edge related to the vertex u with zero degree, wherein the graph is not blank, and jumping to step S51, otherwise jumping to step S53;

Step S53 can obtain the vertexes contained in the ith stage and the (i+1) th stage according to the stages of the vertexes, and set weights for the elements of the ith stage according to the position relation;

Step S54 scans all edges e, if the starting point u of the edge e is at the ith level and the end point v is at the (i+1) th level, updating the weight sum of the vertexes v;

Step S55, calculating the average weight of the (i+1) -th vertex according to the weight sum of the (i+1) -th vertex and the incidence of the vertex;

step S56, sorting the (i+1) th-stage vertexes according to the average weight, and placing vertexes according to the sorting result;

step S57, setting weights according to the placement sequence of the (i+1) th level;

Step S58 scans all edges e, if the starting point u of the edge e is at the ith stage and the end point v is at the (i+1) th stage, the weight sum of the vertexes u is updated, and the average weight of the vertexes of the ith stage is calculated according to the weight sum of the vertexes of the ith stage and the degree of the vertex;

step S59 performs steps S54 to S58 a plurality of times;

Step S510 is executed to step S54, where the average weight of the (i+1) th level is calculated according to the weight of the i-th level and the (i+1) th level, the vertices are sorted according to the average weight, and the vertices are placed according to the sorting result.

A directed acyclic graph for a grading demonstration is shown in fig. 12. The degree of ingress and egress of each vertex in the directed acyclic graph of FIG. 12 for a grading demonstration is shown in FIG. 13. Wherein, the vertices with the ingress degree of 0 are A, B and C, the vertices A, B and C are set as the 1 st stage, then the 1 st stage vertex and the associated directed edge are removed, and the first stage vertex and the associated directed edge are removed as shown in fig. 14. Then, on the basis of fig. 14, vertices D, E, F with degree of penetration of 0 are removed again, vertices D, E, F are set to the 2 nd stage, then the 2 nd stage vertices and the associated directed edges are removed, and the above steps are repeated until the graph becomes empty. The series of all vertices is schematically shown in fig. 15.

The vertices included in the 1 st stage and the 2 nd stage can be obtained according to the number of the vertices, weights are respectively set to 100, 200 and 300 according to the position relation of the 1 st stage element, and the schematic diagram is shown in fig. 16, and weights are set to the 1 st stage element according to the position relation.

Scanning all the edges e, and if the starting point u of the edge e is in the 1 st level and the end point v is in the 2 nd level, updating the weight sum of the vertexes v to be 100, 400 and 500 respectively; and calculating the average weight of the 2 nd-stage vertexes according to the weight sum of the 2 nd-stage vertexes and the incidence degree of the vertexes, wherein the incidence degree of the 2 nd-stage vertexes is 1,2 and 2 respectively. The average weight=weight and/or degree of entering of the vertex of the 2 nd stage, the average weights of the vertex of the 2 nd stage are respectively 100, 200 and 250, the vertex of the 2 nd stage is ordered according to the average weight, the vertex is placed according to the ordering result, and the schematic diagram is shown in fig. 17, and is the average weight of the second stage of the directed acyclic graph.

Scanning all the edges e, if the starting point u of the edge e is in the 1 st stage and the end point v is in the 2 nd stage, updating the weight sum of the vertexes u to be 200, 250 and 450 respectively, and calculating the average weight of the vertexes of the ith stage according to the weight sum of the vertexes of the 1 st stage and the output degrees of the vertexes, wherein the output degrees of the vertexes of the 1 st stage are 2, 1 and 2 respectively. Average weight=weight and/or degree of exit of the 1 st stage vertex, the average weights of the 1 st stage vertex are respectively 100, 250 and 225, which are obtained by the formula, and the schematic diagram is shown in fig. 18, and the average weight of the first stage vertex is calculated according to the weight of the second stage vertex.

And continuing to scan all the edges e, if the starting point u of the edge e is in the 1 st stage and the end point v is in the 2 nd stage, updating the weight sum of the vertexes v to be 150, 375 and 475 respectively, and calculating the average weight of the vertexes of the 2 nd stage according to the weight sum of the vertexes of the 2 nd stage and the incidence of the vertexes, wherein the incidence of the vertexes of the 2 nd stage is 1,2 and 2 respectively. Average weight=weight and/or ingress of the vertex of stage 2, the average weight of the vertex of stage 2 is found to be 150, 162.5, 237.5 from the formula. Similarly, the average weights of the 3 rd vertex points can be calculated to be 200 and 193.75 respectively. The average weights of the 4 th-stage vertices are 200 and 193.875, respectively. The schematic diagram is shown in fig. 19, in which the weights of the subsequent vertices are calculated according to the weights of the first-stage vertices after iteration.

The vertices are sorted according to the size of each stage of the average weight, and the vertices are placed according to the sorting result, and the schematic diagram is shown in fig. 20, and is the number of rows of each vertex after sorting.

Step S6: channel estimation and position calculation. The channel is estimated, the absolute position of the element is calculated from the relative position,

Step S61, calculating the row and column widths of the elements, wherein the row (column) size of the elements is the maximum value of the height (width) of all the elements in the row (column);

Step S62, calculating the distance between the rows (columns) of the elements, scanning the connection relation among all the elements, and increasing the channel weight value between the columns and the rows for one connection relation;

step S63, where the element is located in the row (column) is determined by the weight of the channel between the row (column) and the zeroth row (column) and the width of all rows (column width) above the element, and the element is placed in the middle of the row.

After the relative positions of all nodes are obtained from the above steps, the channel needs to be estimated, i.e. the absolute positions of the vertices are calculated from the relative positions. For example, the relative positions and relative sizes between the elements are as follows: there are 7 elements { A, B, C, D, E, F, G }; the relative positions of the two components are A (1, 1), B (1, 2), C (1, 3), D (2, 2), E (2, 3), F (3, 1) and G (3, 2); the sizes of the elements are A (3, 2), B (4, 3), C (4, 1), D (3, 2), E (2, 4), F (4, 3), G (2, 2), the former number in brackets is the width of the element, and the latter number is the height of the element, thereby calculating the absolute position of the element.

And calculating the row width and the column width of the element according to the size of the element, setting an initial value, scanning all connection relations, and calculating the spacing between the rows/columns of the element by using the connection relations. The absolute position of the element is calculated by the row-column width of the element and the space between the rows and columns, the absolute position of each column of each row is calculated (the column is represented by the upper coordinates and the row is represented by the left coordinates), the absolute position of the element is represented by the upper left corner point of the element, so that the element is centered at the row column position, the column absolute position (x) of the element=the absolute position of the column + (column width-element width)/2; row absolute position of element (y) =absolute position of row + (row-element height)/2, column absolute position of a (x) =0+ (4-3)/2=0.5; row absolute position of a (y) =0+ (3-2)/2=0.5; the absolute positions of the other elements are calculated in the same way as B (0, 9), C (0, 20.5), D (14, 9.5), E (14.5, 19), F (25, 0), G (26, 9.5), and the final layout diagram (A-G part) is shown in FIG. 21.

Claims

1. A schematic layout method for heuristic line and column positioning, comprising the steps of:

s1, analyzing data, wherein in the data analysis, according to a given electronic design exchange format file, a schematic diagram is obtained through analysis, and the connection relation of the schematic diagram is described by using an adjacency list;

step S2, calculating strong communication branches, wherein an algorithm is based on depth-first search of a graph, and searching unviewed vertexes through the search depth-first search;

step S3, judging whether the number of the strong communication branches is equal to the number of the nodes of the graph, if the number of the strong communication branches is equal to the number of the nodes of the graph, entering a step S5, otherwise, entering a step S4;

Step S4, for the layout of a single strong communication branch, calculating a sub-graph corresponding to the strong communication branch, scanning all directed edges, if the starting point and the end point of the directed edge are in the single strong communication branch, the directed edge belongs to the sub-graph where the strong communication branch is located, and calculating the level where all vertexes are located by traversing the directed edge of the sub-graph;

step S5, classifying the directed acyclic graph layout after scanning in a topological ordering mode, calculating the average weight of all levels of vertexes in an iterative mode, ordering according to the average weight, and placing the vertexes according to an ordering result, wherein the step S5 specifically comprises the following steps:

Step S52, removing the edge related to the vertex u with zero degree, wherein the figure is not blank, and jumping to step S51, otherwise jumping to step S53;

step S54 scans all edges e, if the starting point u of the edge e is in the ith stage and the end point v is in the (i+1) th stage, updating the weight sum of the (i+1) th stage;

step S59 performs steps S54 to S58 a plurality of times;

Step S510, according to the weight of the ith stage, calculating the average weight of the ith and the (i+1) th stages according to the connection relation between the ith stage and the (i+1) th stage, sorting according to the average weight, and placing vertexes according to the sorting result;

step S6: the step S6 specifically includes the following steps:

Step S61, calculating the row width and the column width of the element, wherein the row/column size of the element is the maximum value of the height/width of all the elements in the row/column;

Step S62, calculating the distance between the rows/columns of the elements, scanning the connection relation among all the elements, and increasing the channel weight value among the rows/columns for one connection relation;

step S63 the element placement in the row/column position is determined by the weight of the channel between the element placement in the row/column and the zeroth row/column and the width of all rows/columns above the element placement in the center of the row/column.

2. The schematic layout method of heuristic line-column positioning according to claim 1, wherein step S1 uses an adjacency list of Graph model g= < V, E > to store data.

3. The schematic layout method of heuristic line-column positioning according to claim 1, wherein the step S2 specifically comprises the following steps:

step S21 searches the vertex u, and sets a time stamp DFN [ u ] and a tracing value LOW [ u ] of the vertex u as ti me;

Step S23 traverses each edge with the starting point of u and the ending point of V, if the vertex V is not accessed, the step S21 is skipped, and when backtracking is performed, the tracing value LOW [ u ] of the vertex u is modified to be the smaller of the tracing values of LOW [ u ] and LOW [ V ]; at search time, if vertex v is in stack, modifying trace back value LOW [ u ] of u to be the smaller of LOW [ u ] and DFN [ v ];

4. A schematic layout method according to claim 3, wherein said step S4 comprises the steps of:

Step S42, calculating the output degrees of all vertexes according to the edge set E1, and placing the vertex with the largest output degree in the kth column;

Step S43 is to symmetrically place the child nodes not placed in the k+1 row according to the positions of the vertices in the k row, and continue step S42 until all the vertices are placed completely, so as to obtain the relative positions of all the vertices of the strongly connected branch.

5. A schematic layout method of heuristic line-column positioning according to claim 1, wherein the average weight is equal to the sum of weights divided by the ingress or equal to the sum of weights divided by the egress.

6. A schematic layout system comprising at least one processor; and

A computer readable storage medium storing a schematic layout method which, when executed by the at least one processor, causes the system to perform a heuristic line locating method according to any of claims 1-5.