CN106503296B - A kind of process mapping method and device based on whitepack - Google Patents
A kind of process mapping method and device based on whitepack Download PDFInfo
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- CN106503296B CN106503296B CN201610848736.3A CN201610848736A CN106503296B CN 106503296 B CN106503296 B CN 106503296B CN 201610848736 A CN201610848736 A CN 201610848736A CN 106503296 B CN106503296 B CN 106503296B
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- whitepack
- gate level
- level netlist
- netlist
- time delay
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
Abstract
The present invention relates to a kind of process mapping method and device based on whitepack, method provided by the embodiment of the present invention includes: by rtl netlist logic synthesis into structuring gate level netlist；Gate level netlist is traversed, multiple whitepacks included in gate level netlist are obtained；The realization of gate level netlist is added for each whitepack, and generates time delay table for each whitepack；According to gate level netlist, multiple whitepacks and the multiple time delay tables progress Technology Mapping for respectively corresponding multiple whitepacks, and calculate the logic time delay and critical path of the gate level netlist after Technology Mapping.Institute of embodiment of the present invention providing method, arithmetic logic unit in gate level netlist is identified as whitepack, and be indicated with the combinational logic gate circuit of standard, Technology Mapping then is carried out to entire netlist, provides a kind of method of general processing special function unit module during Technology Mapping.
Description
Technical field
The present invention relates to the IC design technical fields more particularly to a kind of work based on whitepack in microelectronic field
Skill mapping method and device.
Background technique
Field programmable gate array (Field-Programmable Gate Array, FPGA) is a kind of with abundant hard
The logical device of part resource, powerful parallel processing capability and flexible reconfigurable ability.And Technology Mapping (Technology
Mapping related by technique is mapped as to the description of technique unrelated structure) as an important step during FPGA design
Physics realization, the synthesis result for enabling integrated systems at different levels abstract is converted into a kind of specific technique and realizes.
Traditional process mapping method can only by simple combinational logic (with or NOT logic etc.) be mapped on look-up table,
With the continuous development of fpga chip, more and more special function units (such as adder, DSP) have appeared in fpga chip
In the middle.Therefore, during Technology Mapping, a kind of general method that can handle such special function unit module is found,
It is a problem to be solved.
Summary of the invention
On the one hand, the embodiment of the invention provides a kind of process mapping methods based on whitepack, this method comprises: by RTL
Grade netlist logic synthesis is at structuring gate level netlist；Gate level netlist is traversed, multiple whitepacks included in gate level netlist are obtained；For
The realization of each whitepack addition gate level netlist, and time delay table is generated for each whitepack；According to gate level netlist, multiple whitepacks and divide
Do not correspond to multiple whitepacks multiple time delay tables carry out Technology Mapping, and calculate the gate level netlist after Technology Mapping logic time delay and
Critical path.
Optionally, in the above-mentioned methods, it when carrying out Technology Mapping, is carried out according to the peripheral logic of whitepack and whitepack
Logic optimization, and do not change the internal logic of whitepack.
Optionally, in the above-mentioned methods, time delay table include the input signal of corresponding whitepack, the output signal of corresponding whitepack with
And the time delay between input signal and output signal.
Optionally, in the above-mentioned methods, whitepack is the specific logical functional module in gate level netlist, including arithmetical operation function
It can module.
On the other hand, the embodiment of the present invention provides a kind of Technology Mapping device based on whitepack, which includes: that netlist is raw
The rtl netlist logic synthesis for being used to receive at unit is at structuring gate level netlist；Whitepack searching unit is for traversing door
Grade netlist, searches multiple whitepacks included in gate level netlist；Whitepack realizes that unit is used to add gate level netlist for each whitepack
Realization, and for each whitepack generate time delay table；Technology Mapping unit is used for according to gate level netlist, multiple whitepacks and right respectively
It answers multiple time delay tables of multiple whitepacks to carry out Technology Mapping, and calculates the logic time delay and key of the gate level netlist after Technology Mapping
Path.
Process mapping method and device based on whitepack provided by the embodiment of the present invention, the arithmetic in gate level netlist is patrolled
It collects unit and is identified as whitepack, and be indicated with the combinational logic gate circuit of standard, Technology Mapping then is carried out to entire netlist,
Provide a kind of method of general processing special functional module during Technology Mapping.
Detailed description of the invention
Fig. 1 is the process mapping method flow diagram provided in an embodiment of the present invention based on whitepack；
Fig. 2 is the Technology Mapping apparatus structure schematic diagram based on whitepack provided by the embodiment of the present invention；
Fig. 3 is gate level netlist structural schematic diagram provided by embodiment one；
Fig. 4 is the combinational logic circuit structural schematic diagram of one full adder of the embodiment of the present invention；
Fig. 5 is the gate level netlist being made of provided by the embodiment of the present invention one standard logic circuits；
Fig. 6 is the netlist after Technology Mapping provided by the embodiment of the present invention one.
Specific embodiment
Below by drawings and examples, technical scheme of the present invention will be described in further detail.
In the prior art, process mapping method can only handle the pure combinational logic based on standard cell lib, and will be above-mentioned
Combinational logic is mapped in look-up table, but for the unit module with specific function, such as with the addition of arithmetical operation function
Device, subtracter, DSP etc. can only be used and temporarily be cut off it from netlist, while the input of the unit module being mapped to entirely
The output of netlist and the input that the output of the module is mapped to entire netlist is subjected to compromise processing.Obviously, with FPGA skill
The development of art more and more joined the arithmetical operations functional modules such as the adder for completing high-speed computation in fpga chip,
Using first cut off add by the way of carry out process mapping method, lose during Technology Mapping to arithmetic operation unit mould
The logic optimization process of block.
The embodiment of the present invention provides a kind of process mapping method based on whitepack, and Fig. 1 is base provided in an embodiment of the present invention
In the process mapping method flow diagram of whitepack, as shown in Figure 1, this method comprises:
Step S101, by RTL (Register Transfer Level) grade netlist logic synthesis at structuring gate leve net
Table.
Step S102 traverses gate level netlist, obtains multiple whitepacks included in gate level netlist.
It should be noted that being identified in gate level netlist using some specific logical functional modules as whitepack, such as will
The logic units such as adder, full adder, DSP (Digital Signal Process) of arithmetical operation are carried out as whitepack, on
Stating specific logical functional module and referring to needs in traditional handicraft mapping process using first cutting off can not providing with other logics of adding afterwards
The functional module of source progress uniform logical optimization, however it is not limited to arithmetical operation functional module provided by the embodiment of the present invention.
In above-mentioned steps, logic unit inside whitepack during following Technology Mappings can clear " seeing ",
And the logic unit inside whitepack remains unchanged during following Technology Mappings.It is proposed the concept of whitepack, primarily to
It during Technology Mapping, keeps whitepack internal logic metastable simultaneously, and can guarantee that the logic around whitepack still can be with
" passing through " whitepack completes optimization, such as constant broadcast (constant propagation).
Step S103 adds the realization of gate level netlist for each whitepack, and generates time delay table for each whitepack.
It should be noted that being that the logic unit for identifying whitepack is used by the realization of each whitepack addition gate level netlist
The combinational logic gate circuit of standard indicates；After being realized for whitepack addition, calculate whitepack currently indicate in all be input to output
Delay value, and it is recorded to (such as table 1) in table form.
It is excellent to carry out logic according to gate level netlist and its time delay table of corresponding multiple whitepacks and each whitepack by step S104
Change and complete Technology Mapping process, and calculates the logic time delay and critical path of the gate level netlist after Technology Mapping.
According to the above method, the embodiment of the present invention also provides a kind of Technology Mapping device based on whitepack, and Fig. 2 is the present invention
Technology Mapping apparatus structure schematic diagram based on whitepack provided by embodiment, as shown in Fig. 2, the device includes:
Netlist generation unit 10, the rtl netlist logic synthesis for will receive is at structuring gate level netlist.
Whitepack searching unit 20 is searched multiple white included in the gate level netlist for traversing the gate level netlist
Box.
Whitepack realizes unit 30, for adding the realization of the gate level netlist for each whitepack, and is each described
Whitepack generates time delay table.
Technology Mapping unit 40, for according to the gate level netlist, the multiple whitepack and respectively corresponding the multiple
Multiple time delay tables of whitepack carry out Technology Mapping, and calculate logic time delay and the pass of the gate level netlist after Technology Mapping
Key path.
For technical solution provided by the clearer expression embodiment of the present invention, below by specific embodiment into one
Step is described.
Embodiment one
By taking the part logical gate of gate level netlist generated during certain FPGA design as an example, Fig. 3 is one institute of embodiment
The gate level netlist structural schematic diagram of offer, as shown in figure 3, in netlist comprising with door 01, full adder 02 and XOR gate 03, according to this
The process of the mapping of method concrete technology provided by inventive embodiments are as follows:
Full adder 02 is identified as whitepack after obtaining gate level netlist shown in Fig. 3 by step 1, and by whitepack standard
Combinational logic circuit be indicated, and finally obtain the gate level netlist that is all made of the logic circuit of standard (such as Fig. 5 institute
Show).Fig. 4 is the combinational logic circuit structural schematic diagram of one full adder of the embodiment of the present invention, as shown in figure 4, adding to full adder 02
After the realization for adding gate level netlist, logic circuit obtained is by a data selector (multiplexer, abbreviation MUX) and two
A XOR gate composition.Fig. 5 is the gate level netlist being made of provided by the embodiment of the present invention one standard logic circuits.
Step 2 calculates the delay value of logic circuit shown in Fig. 4, records the delay value that output is each input in whitepack,
Table 1 is the time-delay table obtained.
1 time-delay table of table
Step 3 carries out logic optimization to the gate level netlist that step 2 obtains, and completes Technology Mapping, and Fig. 6 is that the present invention is real
Netlist after applying Technology Mapping provided by example one, as shown in fig. 6, the netlist is by a LUT, two XOR gates and one
MUX composition.It will not go into details herein for the delay for calculating netlist and critical path.
If above-mentioned Technology Mapping process is carried out using conventional method, it is (final just logic optimization cannot to be carried out to full adder
Netlist after the Technology Mapping of acquisition is shown in Fig. 5), cause logical resource to waste.
Professional should further appreciate that, described in conjunction with the examples disclosed in the embodiments of the present disclosure
Unit and algorithm steps, can be realized with electronic hardware, computer software, or a combination of the two, hard in order to clearly demonstrate
The interchangeability of part and software generally describes each exemplary composition and step according to function in the above description.
These functions are implemented in hardware or software actually, the specific application and design constraint depending on technical solution.
Professional technician can use different methods to achieve the described function each specific application, but this realization
It should not be considered as beyond the scope of the present invention.
Above-described specific embodiment has carried out further the purpose of the present invention, technical scheme and beneficial effects
It is described in detail, it should be understood that being not intended to limit the present invention the foregoing is merely a specific embodiment of the invention
Protection scope, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should all include
Within protection scope of the present invention.
Claims (4)
1. a kind of process mapping method based on whitepack, which is characterized in that the described method includes:
By rtl netlist logic synthesis at structuring gate level netlist；
The gate level netlist is traversed, multiple whitepacks included in the gate level netlist are obtained；
The realization of the gate level netlist is added for each whitepack, and generates time delay table for each whitepack；
According to the gate level netlist, the multiple whitepack and the multiple time delay tables progress for respectively corresponding the multiple whitepack
Technology Mapping, and calculate the logic time delay and critical path of the gate level netlist after Technology Mapping；
When carrying out the Technology Mapping, logic optimization is carried out according to the peripheral logic of the whitepack and the whitepack, and
The internal logic of the whitepack is not changed.
2. the method according to claim 1, wherein the time delay table includes the input letter of the corresponding whitepack
Number, the time delay between the output signal and the input signal and the output signal of the corresponding whitepack.
3. the method according to claim 1, wherein the whitepack is the specific logical function in the gate level netlist
Energy module, including arithmetical operation functional module.
4. a kind of Technology Mapping device based on whitepack is applied to the method as claimed in claims 1-3, which is characterized in that institute
Stating device includes:
Netlist generation unit, the rtl netlist logic synthesis for will receive is at structuring gate level netlist；
Whitepack searching unit searches multiple whitepacks included in the gate level netlist for traversing the gate level netlist；
Whitepack realizes unit, for adding the realization of the gate level netlist for each whitepack, and it is raw for each whitepack
At time delay table；
Technology Mapping unit, for according to the gate level netlist, the multiple whitepack and respectively corresponding the multiple whitepack
Multiple time delay tables carry out Technology Mapping, and calculate the logic time delay and critical path of the gate level netlist after Technology Mapping
Diameter.
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| CN103366029A (en) * | 2012-03-31 | 2013-10-23 | 中国科学院微电子研究所 | Field programmable gate array chip layout method |
| CN103699705A (en) * | 2012-09-27 | 2014-04-02 | 中国科学院微电子研究所 | System and method for designing FPGA (field programmable gate array) structure |
| CN104598659A (en) * | 2013-10-31 | 2015-05-06 | 国际商业机器公司 | Method and device for simulating digital circuit |
| CN105303000A (en) * | 2015-11-26 | 2016-02-03 | 浪潮(北京)电子信息产业有限公司 | Circuit design method and system |
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- 2016-09-23 CN CN201610848736.3A patent/CN106503296B/en active Active
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| CN1495649A (en) * | 2002-09-10 | 2004-05-12 | ���µ�����ҵ��ʽ���� | System for estimating performance of integrated circuit in register transfer level |
| CN101317180A (en) * | 2005-12-02 | 2008-12-03 | Nxp股份有限公司 | Method for providing an IC design and IC design tool |
| CN103366029A (en) * | 2012-03-31 | 2013-10-23 | 中国科学院微电子研究所 | Field programmable gate array chip layout method |
| CN103699705A (en) * | 2012-09-27 | 2014-04-02 | 中国科学院微电子研究所 | System and method for designing FPGA (field programmable gate array) structure |
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