CN106407023A - Parallel wiring method for field-programmable gate array chip based on multi-core processor - Google Patents
Parallel wiring method for field-programmable gate array chip based on multi-core processor Download PDFInfo
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- CN106407023A CN106407023A CN201610805258.8A CN201610805258A CN106407023A CN 106407023 A CN106407023 A CN 106407023A CN 201610805258 A CN201610805258 A CN 201610805258A CN 106407023 A CN106407023 A CN 106407023A
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- main thread
- candidate nodes
- sub
- line journey
- cost value
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/546—Message passing systems or structures, e.g. queues
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/54—Indexing scheme relating to G06F9/54
- G06F2209/548—Queue
Abstract
The invention relates to a parallel wiring method for a field-programmable gate array chip based on a multi-core processor. A process of the method can be divided into a main thread and at least one child thread. The main thread identifies a source node of the FPGA chip, obtains first candidate nodes associated with the source node, determines the number of the child threads according to the number of the first candidate nodes and the core number of the multi-core processor and starts the child threads; and the main thread starts the child threads having the same number as the number of the first candidate nodes according to the number of the first candidate nodes. The main thread sends the first candidate nodes to the child threads in sequence and receives corresponding COST values obtained by parallel computing of the child threads according to the first candidate nodes. The main thread identifies the first candidate node corresponding to the lowest COST value and carries out wiring on the FPGA chip according to an identification result. According to the method, the child threads carry out parallel computing on the COST values of the candidate nodes, so that the run time of wiring is effectively reduced.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly, to a kind of field-programmable gate array based on polycaryon processor
The parallel routing method of row (Field Programmable Gate Array, FPGA) chip.
Background technology
On-site programmable gate array FPGA chip is that one kind has abundant hardware resource, powerful parallel processing capability and flexibly
The logical device of reconfigurable ability.These features make FPGA be got in a lot of field such as data processing, communication, network
Carry out more extensive applications.
The software flow of FPGA can include integrated treatment, mapping, place and route.The Routing Algorithm of prior art is base
The process of the serial computing node cost value carrying out in uniprocessor single thread, that is, in a digraph from a source node to
The path search process of destination node.Using the cost evaluation value of node, this cost evaluation value when node cost value refers to connect up
Including by the physics time delay of this node, current congestion state, history congestion state, the letter such as criticality of gauze residing for this node
Breath.
However, the many factors being related to due to COST value, amount of calculation therefore is generally than larger.In existing fpga chip
Whole software flow in, the run time of wiring generally take up the ratio of time often more than 50% that is to say, that existing
The wiring run time of technology is longer.
Content of the invention
The embodiment of the present application provides a kind of parallel routing of the field programmable gate array chip based on polycaryon processor
Method.The method flow process can be divided into main thread and at least one sub-line journey.The method can reduce wiring run time.
In a first aspect, the method can include：Main thread is identified to the source node of fpga chip, obtains source node and closes
First both candidate nodes of connection；The quantity according to the first both candidate nodes for the main thread and the check figure of polycaryon processor, determine sub-line journey
Quantity, and promoter thread.The sub-line journey to after start for the main thread sends the first both candidate nodes successively；Main thread receives sub-line journey
The corresponding COST value being gone out according to the first both candidate nodes parallel computation.Main thread is to minimum corresponding first both candidate nodes of COST value
It is identified, and according to recognition result, fpga chip is connected up.
In an optional realization, main thread is identified to fpga chip, obtains source node association at least one
After first both candidate nodes, the first both candidate nodes are stored in first queue main thread.Main thread sends successively to sub-line journey
First both candidate nodes, specifically include：Main thread receives the wiring request that sub-line journey sends；Main thread, according to wiring request, judges
Whether first queue is empty；If it is not, then main thread sends described first both candidate nodes to idle sub-line journey；If so, then main line
Journey sends to all of sub-line journey and terminates thread signal, to notify wiring to terminate.
In an optional realization, after main thread receives the wiring request of at least one sub-line journey transmission, main thread
Send request response signal to sub-line journey, receive wiring request to indicate.
In an optional realization, when main thread identifies that the first both candidate nodes are not destination node, main thread pair
First both candidate nodes are identified, and obtain the second both candidate nodes of the first both candidate nodes, to receive the second time of sub-line journey transmission
Select the COST value of node.
In an optional realization, main thread receives the COST value that sub-line journey goes out according to the first both candidate nodes parallel computation
Afterwards, the first both candidate nodes and the first both candidate nodes corresponding COST value are stored in second queue main thread.
In an optional realization, main thread is identified specifically to minimum corresponding first both candidate nodes of COST value
Including：When main thread determines that corresponding first both candidate nodes of minimum COST value are that destination node main thread connects up to fpga chip
Complete；When main thread determines that corresponding first both candidate nodes of minimum COST value are not destination node, main thread obtains first
The second both candidate nodes that both candidate nodes drive, for identifying that corresponding second both candidate nodes of minimum COST value are purpose sections
Point, completes to connect up.
A kind of parallel routing method flow of FPGA based on polycaryon processor provided in an embodiment of the present invention can be divided into
Main thread and at least one sub-line journey.Main thread is identified to the source node of fpga chip, obtains the first of source node association
Both candidate nodes, main thread is according to the quantity of the first both candidate nodes, startup and quantity identical sub-line journey afterwards.Main thread pass through to
Sub-line journey sends the first both candidate nodes successively, receives the corresponding COST value that sub-line journey goes out according to the first both candidate nodes parallel computation.
Main thread is identified to minimum corresponding first both candidate nodes of COST value, according to recognition result, carries out cloth to fpga chip
Line.The method passes through the parallel computation to both candidate nodes COST value for the sub-line journey, effectively reduces the run time of wiring.
Brief description
In order to be illustrated more clearly that the technical scheme of the embodiment of the present invention, below will be to required use in embodiment description
Accompanying drawing be briefly described it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill of field, on the premise of not paying creative work, can also be obtained other according to these accompanying drawings
Accompanying drawing.
Figure 1A is the interconnection resource structural representation of prior art；
Figure 1B is a kind of structural representation of the interconnection resource shown in Figure 1A；
Fig. 2 is the parallel routing method flow diagram of the fpga chip based on polycaryon processor provided in an embodiment of the present invention；
Fig. 3 A position main thread provided in an embodiment of the present invention method flow schematic diagram；
Fig. 3 B position sub-line provided in an embodiment of the present invention journey method flow schematic diagram.
Specific embodiment
Below by drawings and Examples, technical scheme is described in further detail.
Method in the following embodiment of the present invention is that the fpga chip based on polycaryon processor is realized.In fpga chip
Interconnection resource in figure, interconnection resource is all generally generally each mux presented in MUX (mux) in hardware
Much individual mux will be driven.In interconnection resource shown in Figure 1A, each mux is a node.1 multichannel is wherein selected with 4
As a example selector mux, this interconnection resource can include source node muxA0 (i.e. start node), intermediate node muxB0-muxB2 and
Destination node muxC0 (i.e. end node), source node muxA0 can drive intermediate node muxB0-muxB2, intermediate node
MuxB1-muxB2 can drive destination node muxC0.
It is understood that this interconnection resource can also include source node muxA1, source node muxA1 can drive centre
At least one of node muxB0-muxB2 node, or drive at least one of intermediate node muxB1-muxB2 node and/
Or destination node muxC0.
Figure 1B is a kind of structural representation of the interconnection resource shown in Figure 1A.A node is source node, B node, C node and D
Node is intermediate node, and E node is purpose node.
Wiring process is divided into main thread and sub-line journey by polycaryon processor by the embodiment of the present invention, thus multiple sub-line journeys
Carry out the COST value of parallel computational nodes.Wherein, according to actual techniques situation, the number of sub-line journey can be according to polycaryon processor
Depending on check figure it is also possible to according to source node drive node number depending on.
The wiring process of polycaryon processor will be described in detail below.
Fig. 2 is the parallel routing method flow diagram of the fpga chip based on polycaryon processor provided in an embodiment of the present invention.
As shown in Fig. 2 the method may include steps of：
Step 210, main thread promoter thread.
When main thread is to start fpga chip, the thread of self-starting, main thread can obtain initialization information.This initialization
Information can include source node and the destination node of routing task.
Alternatively, before main thread promoter thread, main thread, according to the source node of fpga chip, obtains source node and closes
First both candidate nodes of connection.Main thread scans fpga chip, the source node of locking fpga chip, and source node is identified,
Obtain at least one first both candidate nodes of source node association.
The quantity according to the first both candidate nodes for the main thread and the check figure of polycaryon processor, determine the quantity of sub-line journey, such as many
Core processor is 4 core processors, and source node associates 8 both candidate nodes, then main thread can only start 3 sub- thread (main threads
Itself takies a core).Because the amount of calculation of calculate node COST value is larger, the time that calculates is longer, therefore uses the first both candidate nodes
Quantity determine sub-line journey quantity it is ensured that the COST value of each the first both candidate nodes completed by independent sub-line journey or
Completed by idle sub-line journey.
Return to step 210, main thread can be by sending trigger (as low and high level) to sub-line journey, to start sub-line
Journey is so as to enter working condition.
The first both candidate nodes obtaining are stored in first queue for step 220, main thread.
Step 230, sub-line journey send wiring request to main thread.
Step 240, main thread receive the wiring request that sub-line journey sends.
If main thread is not connected to the wiring request of sub-line journey transmission, main thread will continue waiting for the wiring of sub-line journey transmission
Request.
Alternatively, receive the wiring request of sub-line journey transmission in main thread after, send, to sub-line journey, the sound confirming to receive
Induction signal, is asked with indicating that main thread receives this wiring.
After step 250, main thread judge whether first queue is empty queue, send the first signal to sub-line journey.
When first queue is not empty queue, main thread to sub-line journey send the first signal, the first signal can include from
After first both candidate nodes taken out in first queue, execution step 240, main thread receives the wiring of sub-line journey transmission again
Request.
Alternatively, sub-line journey, according to the first both candidate nodes receiving, calculates the COST value of this node.
Sub-line journey sends secondary signal to main thread, and secondary signal can include the COST value of this node.
When first queue is empty queue, main thread sends the first signal to sub-line journey, and the first signal is to terminate thread letter
Number, to notify wiring to terminate.Now by the first both candidate nodes and its corresponding COST value that calculates sends to main thread sub-line journey.
The first both candidate nodes receiving and its corresponding COST value are stored in second queue for step 260, main thread.
Step 270, when main thread determines that the first both candidate nodes are destination node, main thread according to COST value, to FPGA
Chip is connected up.
If this first both candidate nodes is destination node, it is cabled successfully, that is, main thread has found the minimum cloth of wiring time
Line scheme.
If this first both candidate nodes is not destination node, main thread takes out minimum COST from second queue now
It is worth corresponding first both candidate nodes, main thread is using this first both candidate nodes as source node：Main thread is known to this source node
Not, obtain the second both candidate nodes of source node association, return execution step 230- step 270, until main thread is from second queue
Till the minimum corresponding both candidate nodes of COST value of middle taking-up are purpose node.
It should be noted that after main thread takes out both candidate nodes from first queue or second queue, first queue or
This both candidate nodes is there will be no in two queues.
In one example, in conjunction with Figure 1B, the main thread method flow shown in Fig. 3 A and sub-line Cheng Fang shown in Fig. 3 B
In method flow process, main thread scans fpga chip, the source node A of locking fpga chip, and source node A is identified, and obtains source
First both candidate nodes B, C of node A association and D, and the first both candidate nodes B, C obtaining and D are put into as shown in table 1 first
In queue.
Table 1
| First both candidate nodes |
| B |
| C |
| D |
As shown in table 1, the first both candidate nodes that in first queue, storage main thread obtains.
Sub-line journey after startup sends wiring request to main thread, and waits main thread to respond, until sub-line journey receives
The response signal that main thread sends, just shows that main thread receives this request.Whether main thread identification first queue is empty queue,
Whether there are the first both candidate nodes：When first queue is not empty queue, then main thread takes out one from first queue successively
Individual first both candidate nodes send to sub-line journey, so that sub-line journey calculates corresponding COST value according to the first both candidate nodes, afterwards
Again wait for the request of sub-line journey.
When first queue is empty queue, then main thread sends to sub-line journey and terminates thread signal, to notify wiring to terminate,
Now by the first both candidate nodes and its corresponding COST value that calculates sends to main thread sub-line journey.Main thread will receive first
Both candidate nodes and its corresponding COST value are stored in second queue, and second queue as shown in table 2 can include following content：
Table 2
| First both candidate nodes | COST value |
| B | x |
| C | y |
| D | z |
In table 2, both candidate nodes B corresponding COST value is x；Both candidate nodes C corresponding COST value is y；Both candidate nodes D pair
The COST value answered is z.
(1) main thread takes out corresponding first both candidate nodes C of minimum COST value from second queue, and identify this
One both candidate nodes C are not destination nodes, then main thread obtains whole node D and E that current first both candidate nodes C drive, as
Second both candidate nodes are stored in first queue, execute above-mentioned steps again, until inquiring destination node E in second queue
Till.
(2) main thread takes out corresponding first both candidate nodes B of minimum COST value from second queue, and identify this
One both candidate nodes B are not destination node E, and the second both candidate nodes that current first both candidate nodes B do not drive, then main thread
Taken out corresponding first both candidate nodes C of minimum COST value again from second queue now, returned to (1).
The parallel routing method flow that the present invention implements a kind of FPGA based on polycaryon processor of offer can be divided into
Main thread and at least one sub-line journey.After main thread promoter thread, the source node of fpga chip is identified, obtains source section
First both candidate nodes of point association, main thread is by sending the first both candidate nodes, reception sub-line journey root successively to sub-line journey afterwards
The corresponding COST value going out according to the first both candidate nodes parallel computation.When main thread identifies that the first both candidate nodes are end node,
Main thread, according to the minimum of a value of COST, connects up to fpga chip.The method passes through sub-line journey to both candidate nodes COST value
Parallel computation, effectively reduces the run time of wiring.
The step of the method in conjunction with the embodiments described herein description or algorithm can be with hardware, computing device
Software module, or the combination of the two is implementing.Software instruction can be made up of corresponding software module, and software module can be by
Deposit in random access memory, flash memory, read-only storage, erasable programmable read-only register (English：erasable
Programmable read-only memory, EPROM) memory, EEPROM memory (English：
Electrically erasable programmable read-only memory, EEPROM), hard disk, read-only optical disc (English
Literary composition：Compact disc read-only memory, CD-ROM) or any other form well known in the art storage be situated between
In matter.A kind of exemplary storage medium is coupled to processor, thus enabling a processor to from this read information, and
Information can be write to this storage medium.Certainly, storage medium can also be the part of processor.Processor and storage medium
May be located in ASIC.In addition, this ASIC may be located in user equipment.Certainly, processor and storage medium can also conducts
Discrete assembly is present in user equipment.
Those skilled in the art it will be appreciated that in said one or multiple example, work(described in the invention
Can be able to be realized with hardware, software, firmware or their any combination.When implemented in software, can be by these functions
It is stored in computer-readable medium or be transmitted as the one or more instructions on computer-readable medium or code.
Above-described specific embodiment, has been carried out to the purpose of the present invention, technical scheme and beneficial effect further
Describe in detail, be should be understood that the specific embodiment that the foregoing is only the present invention, be not intended to limit the present invention
Protection domain, all any modification, equivalent substitution and improvement on the basis of technical scheme, done etc., all should
Including within protection scope of the present invention.
Claims (6)
1. a kind of parallel routing method of the field programmable gate array chip based on polycaryon processor is it is characterised in that described
Method flow is divided into main thread and at least one sub-line journey, and methods described includes：
Described main thread is identified to the source node of fpga chip, obtains the first both candidate nodes of described source node association；
The quantity according to described first both candidate nodes for the described main thread and the check figure of polycaryon processor, determine the number of described sub-line journey
Amount, and start described sub-line journey；
The described sub-line journey to after start for the described main thread sends described first both candidate nodes successively；
Described main thread receives the corresponding COST value that described sub-line journey goes out according to described first both candidate nodes parallel computation；
Described main thread is identified to minimum corresponding described first both candidate nodes of described COST value；
Described main thread, according to recognition result, connects up to described fpga chip.
2. method according to claim 1, it is characterised in that described main thread is identified to fpga chip, obtains institute
After stating at least one first both candidate nodes of source node association, methods described also includes：
Described first both candidate nodes are stored in first queue described main thread；
The described sub-line journey to after start for the described main thread sends described first both candidate nodes successively, specifically includes：
Described main thread receives the wiring request that described sub-line journey sends；
Described main thread, according to described wiring request, judges whether described first queue is empty；
If it is not, then described main thread sends described first both candidate nodes successively to idle described sub-line journey；
If so, then described main thread sends end thread signal to all of described sub-line journey, to notify wiring to terminate.
3. method according to claim 2 is it is characterised in that the wiring that described main thread receives described sub-line journey transmission please
After asking, methods described also includes：
Described main thread sends request response signal to described sub-line journey, receives described wiring request to indicate.
4. method according to claim 1 is it is characterised in that methods described also includes：
When described main thread identifies that described first both candidate nodes are not destination node, described main thread is to described first candidate
Node is identified, and obtains the second both candidate nodes of described first both candidate nodes, with receive that described sub-line journey sends described the
The COST value of two both candidate nodes.
5. method according to claim 1 is it is characterised in that described main thread receives described sub-line journey according to described first
After the COST value that both candidate nodes parallel computation goes out, methods described also includes：
Described first both candidate nodes and the corresponding COST value of described first both candidate nodes are stored in the second team by described main thread
In row.
6. method according to claim 1 is it is characterised in that described main thread is to the minimum corresponding institute of described COST value
State the first both candidate nodes to be identified, specifically include：
When described main thread determines that corresponding described first both candidate nodes of minimum described COST value are destination node, described master
Thread completes to the wiring of described fpga chip；
When described main thread determines that corresponding described first both candidate nodes of minimum described COST value are not destination node, described
Main thread obtains the second both candidate nodes that described first both candidate nodes drive, and the described COST value for identifying minimum corresponds to
Described second both candidate nodes be described destination node, complete connect up.
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| CN201610805258.8A CN106407023A (en) | 2016-09-06 | 2016-09-06 | Parallel wiring method for field-programmable gate array chip based on multi-core processor |
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