CN104182556B - The layout method of chip - Google Patents
The layout method of chip Download PDFInfo
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- CN104182556B CN104182556B CN201310192832.3A CN201310192832A CN104182556B CN 104182556 B CN104182556 B CN 104182556B CN 201310192832 A CN201310192832 A CN 201310192832A CN 104182556 B CN104182556 B CN 104182556B
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Abstract
The present invention relates to a kind of layout method of chip, this method includes：Obtain the sum M and species L of logic unit clock signal；When the global clock signal number N of chip is less than the sum M of the logic unit clock signal got, according to the species L of logic unit clock signal, logic unit is sorted out；According to the clock signal of every logic of class unit, N logic of class units are chosen from L logic of class units；Clock signal using N number of global clock signal as selected N logic of class units；Remaining L N logic of class unit is configured to macroblock respectively；During by macroblock layout to chip, clock signal of the local clock signal of region as the macroblock is selected；According to the macroblock, default netlist is updated；Object function is established according to the netlist after renewal, calculates the position of the macroblock in a chip layout.The present invention is effectively guaranteed clock safety problem, improves the process performance of chip.
Description
Technical field
The present invention relates to placement algorithm, more particularly to a kind of layout method of chip.
Background technology
At present, programmable gate array (Field Programmable Gate Array, FPGA) is applied at the scene
In, it is desirable to integrated circuit has programmable or configurable interference networks, and gate is by configurable interference networks and each other
Connection.The FPGA to be worked as core in individual chips or system is applied to a large amount of microelectronic devices extensively
In.The definition of the FPGA of broad sense gate, does not refer to simple NAND gate singly, also refer to combinational logic with configurable functionality with
The logic unit of sequential logic or the logical block for being interconnected and being formed by multiple logic units.
With the expansion of fpga chip scale, placement algorithm more seems crucial and important, mainly faces both sides and chooses
War：How to tackle large-scale layout circuit and improve chip performance.In the case that global clock number is limited on chip, such as
What ensures that when handling large-scale circuit register and having many clock signals be not in clock safety problem, turns into guarantee core
The key of tablet quality.
Industrial quarters can also ensure the method for clock safety in the case of solution design multi-clock well without proposition at present.
The content of the invention
It is an object of the invention to provide one kind in the case that global clock number is limited on chip, and large-scale integrated is electric
When road register has many clock signals, solves the chip layout method of clock safety problem.
To achieve the above object, the invention provides a kind of method of chip layout, this method to include：
Obtain the sum M and species L of logic unit clock signal；
When the global clock signal number N of chip is less than the sum M of the logic unit clock signal got, root
According to the species L of the logic unit clock signal, the logic unit is sorted out, when there is identical per logic of class unit
Clock signal；
According to the clock signal of every logic of class unit, N logic of class units are chosen from L logic of class units；Will be described N number of complete
Clock signal of the office clock signal respectively as selected N logic of class units；Remaining L-N logic of class unit is built respectively
For macroblock；During by macroblock layout to chip, a local clock signal of region is selected as described grand
The clock signal of module；
According to the macroblock, default netlist is updated；
Object function is established according to the netlist after renewal, calculates the position of the macroblock in a chip layout.
In the above-mentioned methods, methods described also includes：
It is more than or equal to the logic unit clock letter got in the global clock signal number N of the chip
Number sum M when, all logic units are directly constituted into the base unit in the chip layout, using global clock signal make
For the clock signal of base unit.
In the above-mentioned methods, it is described according to clock signal per logic of class unit, N classes are chosen from L logic of class units
Logic unit includes：
According to the number of the logic unit under each species clock signal, each species clock signal is ranked up；According to
According to ranking results, N logic of class units are chosen from L logic of class units.
In the above-mentioned methods, the macroblock according to the structure, updating default netlist includes：
The logic unit that macroblock is formed in default netlist is replaced with into macroblock, by the base unit and macroblock
It is expressed as node；
Believed according to the line that the annexation between the node is updated in the netlist on each each port of logic unit
Breath.
In the above-mentioned methods, the netlist according to after renewal establishes object function, solves the macroblock in chip
Also include after position in layout：
According to the macroblock tried to achieve position in a chip layout and the size of default macroblock, determine successively grand
The each position of logic unit in a chip layout in module.
In the above-mentioned methods, methods described also includes：
Judge layout it is overlapping to whether having between the logic unit on chip and macroblock, have it is overlapping in the case of, will
The macroblock or logic unit are moved to the position of lap position ambient idle.
The present invention is effectively protected by the way that the less logic unit of logic unit number under clock signal is built into macroblock
Clock safety problem is demonstrate,proved, so as to improve chip performance；In addition, because the structure of macroblock of the present invention, reduce clock letter
Number occupancy, therefore large-scale layout circuit can be tackled.
Brief description of the drawings
Fig. 1 is the flow chart of the chip layout method of the embodiment of the present invention；
Fig. 2 is the basic composition structure chart of logic unit；
Fig. 3 is a kind of structural representation of netlist；
Fig. 4 is the structural representation of another netlist.
Embodiment
Below by drawings and examples, technical scheme is described in further detail.
Fig. 1 is the flow chart of the chip layout method of the embodiment of the present invention.As shown in figure 1, the layout side of chip of the present invention
Method includes：
Step 101, default subscriber's line circuit is integrated and storehouse maps, obtain elementary cell.
In a step 101, default subscriber's line circuit is formed using hardware description language compiling, by using high-level
Hardware description language（verilog）Compiling the subscriber's line circuit synthesis formed turns into the gate level circuit of low level；And by gate level circuit
It is mapped in elementary cell, elementary cell can include three kinds of citation forms：It is the look-up tables and register of four inputs, independent four defeated
Look-up table, the single register entered.Look-up table（LUT, Look-Up-Table) substantially it is exactly a random access memory
（RAM, Random Access Memory）.More LUT using 4 inputs in industrial quarters FPGA at present, so each LUT can be with
Regarding one as has the 16x1 RAM of 4 bit address lines.When user passes through schematic diagram or hardware description language（HDL, Hardware
Description Language）After describing a logic circuit, exploitation software PLD/FPGA can automatic calculating logic electricity
The all possible result on road, and result is write RAM in advance, so, often input a signal progress logical operation and be equal to
One address of input is tabled look-up, and finds out content corresponding to address, is then exported.
Step 102, the elementary cell is packaged into logic unit.
The base unit of packing processing is to look for table and register, and the target of packing is primarily to solve three problems：
First, the constraint of some look-up table ranks when processing is laid out, such as：Certain two look-up table has to be placed on adjacent position
Put, the look-up table and register of some special relationships can not put together, it is however generally that, constrain more early processing, the difficulty of processing
It is relatively smaller；Second, some small logic units are combined into a big logic unit during packing, reduce logic unit
The order of magnitude, it can so greatly reduce solution scale during global wiring below, reduce layout time；3rd, it can improve
The area service efficiency of chip, the editable programmed logical module on chip（PLB,Programmable Logic Block）
It is corresponding with the logic unit being packaged into, the utilization rate of each logic unit can be easily controlled in packing, so as to
Improve the utilization rate of chip area.The process of packing is broadly divided into two steps：The first step, by look-up table, register, or look-up table
Combination with register forms elementary cell；Second step, by elementary unit groups combinator unit.
Fig. 2 is the basic composition structure chart of logic unit, as shown in Fig. 2 a logic unit（LE,Logic
Element）By 4 basic programmable logic elements（LP, Logic Parcel）, fast hop carry chain input（Carry
skip in）, fast hop carry chain output（Carry skip out）And local buffer LBUF compositions.Each LP includes two
Individual LUT4,1 LUT4C（LUT4 with carry chain）With two registers.Amounting in 1 LE has 12 LUT4 and 8 registers,
The ratio of LUT4 and register is 3:2, the input of fast hop carry chain and fast hop carry chain are exported for realizing quick jump
Jump carry chain function, and LBUF is used for the control signal clock for producing register in logic unit.
Return to Fig. 1.Step 103, the sum M and species L of the logic unit clock signal are obtained.
In step 103, first by each logic unit, all of the port of each logic unit and and each logic unit
Each port on link information recorded in default netlist, then according to default netlist, count all logic units
Number, and by analyzing the clock of each logic unit（clock）The species of line is determined corresponding to the logic unit on port
The species of clock signal.
Step 104, it is less than the total of the logic unit clock signal got in the global clock signal number N of chip
During number M, according to the species L of the logic unit clock signal, the logic unit is sorted out, had per logic of class unit
Identical clock signal.
At step 104, the global clock signal number of chip is fixed by hardware, is a determination value.Specifically,
The global clock signal number of chip is represented with N, the number of logic unit clock signal that gets is represented with M.In chip
When global clock signal number N is less than the sum M of the logic unit clock signal got, during according to the logic unit
The species L of clock signal, sorts out to the logic unit, has identical clock signal per logic of class unit.According to each
The number of logic unit under species clock signal, each species clock signal is ranked up according to order from big to small,
Logic unit clock signal after sequence is expressed as CLK1,CLK2..., CLKm, use CLKiRepresent i-th of species clock signal；
According to ranking results, N logic of class units are chosen from L logic of class units.Using N number of global clock signal as selected
The clock signal of N logic of class units.
Global clock signal number N such as fruit chip is more than or equal to the sum M of the logic unit clock signal got
When, all logic units are directly constituted into the base unit in the chip layout, it is substantially single using the conduct of global clock signal
The clock signal of position.
Step 105, remaining L-N logic of class unit is configured to macroblock respectively, macroblock layout is arrived into chip
When upper, clock signal of the local clock signal of region as the macroblock was selected.
Specifically, the ranking results according to step 104, structure is distinguished to the logic unit under remaining L-N classes clock signal
L-N macroblock is built, when the macroblock is laid out onto chip, selects a local clock signal of region as institute
State the clock signal of macroblock.It is exemplified as, there is the PLB of 16*32 number on chip, whole PLB arrays can be divided into many small
Region, wherein may be considered a zonule per 2*8 regions.Each PLB zonule can arbitrarily select 4 signal lines
As clock signal wires, when macroblock layout arrives the PLB zonules, wherein 1 signal line can be selected as the macroblock
Clock signal.
Step 106, according to the macroblock of the structure, default netlist is updated.
Default netlist includes each logic unit of user's design, all of the port of each logic unit and and each
Link information on each port of logic unit, and the structure of macroblock has been carried out to part logic unit in step 105,
Therefore the macroblock according to structure is needed, updates default netlist；The logic unit of macroblock will be formed in default netlist
Macroblock is replaced with, the base unit and macroblock are expressed as node；Updated according to the annexation between the node
Link information in the netlist on each each port of logic unit.
Step 107, object function is established according to the netlist after renewal, solves the position of the macroblock in a chip layout
Put.Fig. 3 is a kind of structural representation of netlist, and netlist interior joint A is connected with node B, C and D respectively in figure.By node A, B,
When C and D layouts are on chip, it is desirable to the wire length between wire length, node A and node B between node A and node C,
Wire length between node A and node D is minimum respectively.Exemplified by requiring the wire length minimum between node A and node C.
In Fig. 3, the half cycle of the equivalent rectangle frame for regarding 2 points of compositions of node A and node C as of the wire length between node A and node C
It is long（HPWL）, it is possible to the optimization of wire length is converted into the optimization of HPWL between node A and node C.HPWL growth
Trend again and the rectangle length of side it is square directly proportional, therefore, HPWL optimization can be converted into the optimization of the rectangle length of side square again.
Similarly, node A and node B, the wire length between node A and node D can also optimize in a manner described.Finally, list
The final object function optimized is needed, shown in equation below：
Wherein,Represent to need the object function optimized, w1, w2And w3Represent first and second in netlist and three connections
Weights corresponding to line,（xA,yA）The coordinate of the start node of first and second and three connecting lines is represented,（xB,yB）、（xC,yC）With
（xD,yD）Represent the coordinate of the terminal node of first and second and three connecting lines.
After object function determination, wherein each node coordinate value will be solved.Fig. 4 is that the structure of another netlist is shown
It is intended to, the netlist includes six nodes of node A, B, C, D, E and F, and annexation is as shown in the figure；Wherein, C, D, E and F are net
Stationary nodes in table, as input-output equipment IO etc., the position of stationary nodes in the chips are usually fixed；A and B points
Logic unit or the macroblock being arranged into chip Wei not needed；W is the weights on each bar side, the weights between A-D and B-F
For 2, remaining is 1.Generally in layout, X-direction and Y-direction separately consider.X-direction is considered first.Assuming that C and D X-coordinate is all
All it is 400 for 100, E and F X-coordinate, then object function can be listed below according to formula 1：
To object function respectively to XAAnd XBPartial derivative is sought, tries to achieve formula（3）With（4）, it is as follows：
Building matrix equation is：
Abbreviation obtains：
Solution matrix equation obtains XA=120, XB=340。
Similarly, node A and node B ordinate can be tried to achieve.
Fig. 1 is returned to, step 108, according to the big of the macroblock tried to achieve position in a chip layout and default macroblock
It is small, each position of logic unit in a chip layout in macroblock is determined successively.
The transverse and longitudinal coordinate value of macroblock in a chip layout is tried to achieve according to step 107, has also just tried to achieve macroblock in chip
Position in layout, and the size of macroblock is set in advance, can be 2*8 logic unit, or 4*4 logic
Unit, each logic unit correspond to a PLB in chip.Specifically, if trying to achieve what some macroblock was laid out in the chips
Position is（1,2）, then when if the size of macroblock is 2*8 logic unit, on chip, position（1,2）Extremely（8,3）
It is arranged to occupied, and includes 16 logic units in macroblock altogether, then the position of each logic unit in a chip layout
Put and be followed successively by（1,2）,（1,3）,（2,2）,（2,3）,（3,2）,（3,3）,（4,2）,（4,3）,（5,2）,（5,3）,（6,2）,（6,
3）,（7,2）,（7,3）,（8,2）,（8,3）.
Step 109, judge that layout is overlapping to whether having between the logic unit on chip and macroblock, there are overlapping feelings
Under condition, the macroblock or logic unit are moved to the position of lap position ambient idle.
Specifically, trying to achieve positions of the macroblock A on chip in step 107 is（1,2）, logic unit B is tried to achieve in core
Position in piece is（4,2）, then judge that A and B is overlapping, using lap position as root node, weight searched for BFS method
Clear position around folded position, if position（4,1）Free time, then logic unit B is moved to position（4,1）.
To sum up, the present invention first determines whether the number of the logic unit of user's design is big when being laid out to chip
In the global clock number of chip, more than in the case of, logic unit is sorted out according to the species of clock signal, will be returned
After class processing, macroblock is built comprising the logic unit under the less clock signal of logic unit number, then by chip
Clock signal of the local clock signal as macroblock, is solved in extensive layout circuit, and global clock signal is not enough
The problem of；Then global wiring algorithm is used, that is, considers the annexation between default netlist interior joint and node, structure
Object function is built, by asking object function the method for partial derivative to obtain the position of each elementary cell in the chips, so that it is determined that
Each base unit optimal position in the chips；Finally by partial layout algorithm, base unit overlapping on chip is entered
Row processing, legalize each layout of basic unit in the chips.
Above-described embodiment, the purpose of the present invention, technical scheme and beneficial effect are carried out further
Describe in detail, should be understood that the embodiment that the foregoing is only the present invention, be not intended to limit the present invention
Protection domain, within the spirit and principles of the invention, any modification, equivalent substitution and improvements done etc., all should include
Within protection scope of the present invention.
Claims (5)
1. a kind of layout method of chip, it is characterised in that this method includes：
Obtain the sum M and species L of logic unit clock signal；
When the global clock signal number N of chip is less than the sum M of the logic unit clock signal got, according to institute
The species L of logic unit clock signal is stated, the logic unit is sorted out, there is identical clock letter per logic of class unit
Number；
According to the clock signal of every logic of class unit, N logic of class units are chosen from L logic of class units；When will be described N number of global
Clock signal of the clock signal respectively as selected N logic of class units；Remaining L-N logic of class unit is configured to respectively grand
Module, when the macroblock is laid out onto chip, a local clock signal of region is selected as the macroblock
Clock signal；
According to the macroblock, default netlist is updated；
Object function is established according to the netlist after renewal, calculates the position of the macroblock in a chip layout；
The macroblock according to the structure, updating default netlist includes：
The logic unit that macroblock is formed in default netlist is replaced with into macroblock, base unit and macroblock are expressed as saving
Point；
Link information in the netlist on each each port of logic unit is updated according to the annexation between the node.
2. according to the method for claim 1, it is characterised in that methods described also includes：
It is more than or equal to the logic unit clock signal got in the global clock signal number N of the chip
During sum M, all logic units are directly constituted into the base unit in the chip layout, using global clock signal as base
The clock signal of our unit.
3. according to the method for claim 1, it is characterised in that it is described according to clock signal per logic of class unit, from L
N logic of class units are chosen in logic of class unit to be included：
According to the number of the logic unit under each species clock signal, each species clock signal is ranked up；According to row
Sequence result, N logic of class units are chosen from L logic of class units.
4. according to the method for claim 1, it is characterised in that the netlist according to after renewal establishes object function, asks
Solve the position of the macroblock in a chip layout also includes afterwards：
According to the macroblock tried to achieve position in a chip layout and the size of default macroblock, macroblock is determined successively
In each position of logic unit in a chip layout.
5. according to the method for claim 1, it is characterised in that methods described also includes：
Judge layout it is overlapping to whether having between the logic unit on chip and macroblock, have it is overlapping in the case of, will described in
Macroblock or logic unit are moved to the position of lap position ambient idle.
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| CN105868431B (en) * | 2015-01-22 | 2018-12-21 | 京微雅格（北京）科技有限公司 | Wiring method based on anchor point |
| CN106649899B (en) * | 2015-10-29 | 2023-04-18 | 京微雅格（北京）科技有限公司 | Local memory layout method |
| CN106649898B (en) * | 2015-10-29 | 2019-12-13 | 京微雅格（北京）科技有限公司 | Packing layout method of adder |
| CN110313002B (en) * | 2015-12-28 | 2023-02-24 | 京微雅格（北京）科技有限公司 | FPGA chip wiring method based on PLB |
| CN106934077B (en) * | 2015-12-29 | 2020-06-16 | 京微雅格（北京）科技有限公司 | Precise block carry chain time sequence analysis method |
| CN109086467B (en) * | 2017-06-14 | 2023-05-02 | 上海复旦微电子集团股份有限公司 | I/O unit layout method and device, medium and equipment of programmable logic device |
| CN113807043B (en) * | 2021-09-17 | 2024-06-18 | 中国科学院上海微系统与信息技术研究所 | Clock tree synthesis and layout hybrid optimization method and device, storage medium and terminal |
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