CN111753484B

CN111753484B - Layout method of multi-die structure FPGA (field programmable Gate array) based on circuit performance

Info

Publication number: CN111753484B
Application number: CN202010611936.3A
Authority: CN
Inventors: 单悦尔; 虞健; 徐彦峰; 惠锋; 闫华; 张艳飞
Original assignee: CETC 58 Research Institute; Wuxi Zhongwei Yixin Co Ltd
Current assignee: CETC 58 Research Institute; Wuxi Zhongwei Yixin Co Ltd
Priority date: 2020-06-30
Filing date: 2020-06-30
Publication date: 2021-12-24
Anticipated expiration: 2040-06-30
Also published as: CN111753484A

Abstract

The invention discloses a layout method of a multi-die structure FPGA based on circuit performance, relating to the field of FPGA, the method cuts a large user input netlist into a plurality of small sub-netlists, ensures that each bare chip can have enough resources to arrange each small sub-netlist, and after the positions of all IO ports are fixed, analyzing the circuit performance of the signal connection relation between the bare chips to determine the key index, selecting a connection point on the bare chips to form a connection path matched with the connection point according to the key index, adding a virtual stress point, and then, single bare chip layout is carried out on each bare chip based on the traction action of the virtual stress point on the corresponding connection point and the traction action of the IO port at the designated position, the bare chips are mutually pulled, and the connection path with better circuit performance is arranged to form a signal connection relation with poorer circuit performance, so that the overall circuit performance of the FPGA with the whole multi-bare chip structure tends to be optimal.

Description

Layout method of multi-die structure FPGA (field programmable Gate array) based on circuit performance

Technical Field

The invention relates to the technical field of FPGA, in particular to a layout method of a multi-die structure FPGA based on circuit performance.

Background

A Field Programmable Gate Array (FPGA) is a general-purpose Programmable logic device, and a user can flexibly configure the FPGA as required to implement different circuit functions. When designing the FPGA circuit, a user firstly writes a circuit hardware description language according to the circuit function to be realized and converts the circuit hardware description language into a corresponding user input netlist, and then performs layout and wiring on the FPGA chip according to the user input netlist. The number of logic resources of the FPGA chip needs to meet the logic resource requirement of the user input netlist, so that along with the continuous expansion of the user design, the scale of the logic resources of the FPGA chip must be correspondingly increased, but along with the increase of the scale of the chip, the processing difficulty of the chip is higher and higher, and the growth yield of the chip is lower and lower.

Disclosure of Invention

The present invention provides a layout method of a multi-die FPGA based on circuit performance, aiming at the above problems and technical requirements, and the technical scheme of the present invention is as follows:

a layout method of a multi-die structure FPGA based on circuit performance is disclosed, the multi-die structure FPGA comprises a silicon connection layer and a plurality of FPGA dies which are arranged on the silicon connection layer in a stacking mode, each FPGA die is provided with a plurality of connection point leading-out ends connected with signal paths inside the FPGA die, the connection point leading-out end in each FPGA die is connected with the connection point leading-out end of any other FPGA die through a cross-die connection line in the silicon connection layer to realize interconnection among the FPGA dies, and the method comprises the following steps:

acquiring a user input netlist, and cutting the user input netlist into a plurality of connected sub-netlists according to the number of logic resources contained in each FPGA bare chip, wherein the sub-netlists correspond to the FPGA bare chips one to one, and the number of the logic resources on each FPGA bare chip meets the logic resource requirements of the corresponding sub-netlists;

arranging IO ports on the FPGA bare chips at specified positions according to the sub netlist corresponding to each FPGA bare chip;

analyzing the circuit performance of the user input netlist, determining the key index of each group of signal connection relations according to the circuit performance of each group of signal connection relations among the sub netlists, wherein the worse the circuit performance of the signal connection relations is, the higher the corresponding key index is;

for each group of signal connection relations between two sub netlists corresponding to any two FPGA bare chips, respectively selecting a logic unit layout position on the two FPGA bare chips as a connection point according to a key index of each group of signal connection relations to form each group of connection points for forming each group of signal connection relations, wherein the higher the key index of the signal connection relation is, the better the circuit performance of a connection path formed by the corresponding group of connection points through a silicon connection layer is;

for any group of connection points between any two FPGA bare chips, respectively selecting connection point leading-out ends on the two FPGA bare chips according to the group of connection points and adding virtual stress points to form a group of virtual stress points corresponding to the group of connection points;

after the configuration of the IO port, the connection point and the virtual stress point of each FPGA bare chip is completed, for each FPGA bare chip, the FPGA bare chip is distributed based on the traction action of the virtual stress point on the FPGA bare chip on the corresponding connection point and the traction action of the IO port at the specified position according to the sub-netlist corresponding to the FPGA bare chip and the force-oriented layout algorithm model.

The circuit performance analysis comprises time sequence analysis, the circuit performance of the signal connection relation and the connection path is time delay length, and the shorter the time delay is, the better the circuit performance is;

then, analyzing the circuit performance of the user input netlist, and determining the key index of each group of signal connection relations according to the circuit performance of each group of signal connection relations among the sub netlists, including:

determining the time margin of each group of signal connection relations through a static time sequence analysis STA based on a time sequence constraint condition, wherein the longer the time delay of the signal connection relations is, the smaller the time margin is;

and determining corresponding key indexes according to the time margins of the signal connection relations, wherein the smaller the time margin of the signal connection relation is, the higher the corresponding key index is.

The circuit performance analysis also comprises power consumption analysis, the circuit performance of the signal connection relation and the connection path is a power consumption value, and the smaller the power consumption is, the better the circuit performance is;

and/or the circuit performance analysis also comprises signal quality analysis, the circuit performance of the signal connection relation and the connection path is a signal quality factor, and the higher the signal quality factor is, the better the circuit performance is;

and/or the circuit performance analysis also comprises on-chip power supply noise analysis, the circuit performance of the signal connection relation and the connection path is a noise value, and the smaller the noise value is, the better the circuit performance is;

and/or the circuit performance analysis also comprises on-chip electromagnetic interference analysis, the circuit performance of the signal connection relation and the connection path is a shielding coefficient, and the higher the shielding coefficient is, the better the circuit performance is.

The further technical scheme is that the method also comprises the following steps:

when the key indexes of P groups of signal connection relations between the two sub netlists corresponding to the two FPGA bare chips are both first key indexes, and the logic unit layout positions on the two FPGA bare chips form Q first connection paths which have the same circuit performance and correspond to the first key indexes through the silicon connection layer;

if P is larger than Q, forming a signal connection relation of Q groups of first key indexes by using Q first connection paths, and forming a signal connection relation of the remaining P-Q groups of first key indexes by using a second connection path between the two FPGA dies, wherein the second connection path is a connection path with circuit performance worse than that of the first connection path;

if P is less than Q, P first connecting paths are selected from the Q first connecting paths to form a signal connection relation of P groups of first key indexes, the remaining Q-P first connecting paths are used as connecting paths corresponding to second key indexes, and the second key indexes are lower than the first key indexes.

The further technical scheme is that when P is larger than Q, Q first connecting paths are used for forming a signal connection relation of a first key index of a Q group, and the signal connection relation comprises the following steps:

randomly forming a signal connection relation of Q groups of first key indexes by using Q first connection paths;

or forming a signal connection relation of a first key index of the Q groups logically in advance according to the circuit logic sequence of the P groups of signal connection relations by utilizing the Q first connection paths.

The further technical scheme is that when P is less than Q, P first connecting paths are selected from Q first connecting paths to form a signal connection relation of P groups of first key indexes, and the signal connection relation comprises the following steps:

randomly selecting P first connecting paths from the Q first connecting paths to form a signal connection relation of P groups of first key indexes;

or selecting P first connection paths according to a predetermined selection order according to the positions of the connection points of the Q first connection paths on one FPGA die, wherein the predetermined selection order is as follows: taking a predetermined position on the FPGA bare chip as a starting point, and sequentially arranging the FPGA bare chip in a determinant structure along the transverse direction and the longitudinal direction of the FPGA bare chip; or, taking a predetermined position on the FPGA bare chip as a starting point, and sequentially arranging the S-shaped structures along the transverse direction and the longitudinal direction of the FPGA bare chip; or, starting from a predetermined position on the FPGA die, the order of the ring structures from outside to inside or from inside to outside along the clockwise or counterclockwise direction.

The further technical scheme is that when P is less than Q, when a signal connection relation of a second key index is formed:

selecting a connection path from all connection paths corresponding to the second key index according to the equal priority to form a signal connection relation of the second key index;

or, preferably selecting the remaining Q-P first connecting paths to form the signal connection relation of the second key index.

The further technical scheme is that a connection point leading-out end is respectively selected on two FPGA bare chips according to a group of connection points, virtual stress points are added to form a group of virtual stress points corresponding to the group of connection points, and the method comprises the following steps:

adding an mth virtual stress point corresponding to the mth connection point at a connection point leading-out end, which is closest to the mth connection point, on the mth FPGA die for a group of connection points formed by the mth connection point on the mth FPGA die and the nth connection point on the nth FPGA die; and adding an nth virtual stress point corresponding to the nth connection point at the connection point leading-out end closest to the mth virtual stress point on the nth FPGA bare chip, wherein the mth virtual stress point and the nth virtual stress point form a group of virtual stress points.

The technical scheme is that the method for arranging the IO ports on the FPGA bare chip at the designated positions comprises the following steps:

and randomly arranging at least one IO port on the FPGA bare chip at a designated position by using an IO EDITOR software tool.

The technical scheme is that an IO EDITOR software tool is used for manually arranging at least one IO port on the FPGA bare chip at an appointed position according to any sequence.

According to a further technical scheme, at least one IO port on the FPGA bare chip is arranged at a designated position according to an IO automatic arrangement algorithm.

According to the technical scheme, the FPGA bare chip is distributed based on the traction action of the virtual stress point on the FPGA bare chip on the corresponding connection point and the traction action of the IO port at the specified position according to the sub netlist corresponding to the FPGA bare chip by using a force-oriented layout algorithm model, and the method comprises the following steps:

regarding the layout positions of the logic units in the sub netlist as nodes, establishing a signal relationship between the nodes into a point-to-point edge relationship, and establishing a force-directed layout algorithm model according to the sub netlist;

solving a force guidance layout algorithm model under the traction action of an IO port to obtain the position of each node in a force balance state;

breaking the force balance state under the traction action of the virtual stress point on the corresponding node serving as the connection point, and solving the force-oriented layout algorithm force model again to obtain an initial layout structure;

and uniformly spreading the initial layout structure until the iteration reaches an iteration termination condition.

The beneficial technical effects of the invention are as follows:

the application discloses a layout method of a multi-die structure FPGA based on circuit performance, a large user input netlist is cut into a plurality of small sub netlists, each FPGA die can be guaranteed to have enough resources to layout each small sub netlist, after the positions of all IO ports are fixed, circuit performance analysis is carried out on the signal connection relation between the FPGA dies to determine the key index of the FPGA die, connection points are selected on the FPGA dies to form connection paths matched with the FPGA dies according to the key index, virtual stress points are added, then single-die layout is carried out on each FPGA die based on the traction effect of the virtual stress points on the FPGA die on the corresponding connection points and the traction effect of the IO ports at the specified positions, and when the multi-die are separately arranged, the points with the connection relation between the dies can be drawn close to one direction, so that the purpose of optimizing the connection relation between the dies is achieved. And the signal connection relation with poorer circuit performance is formed by arranging the connection paths with better circuit performance, so that the overall performance of the whole multi-die FPGA tends to be optimal.

Drawings

FIG. 1 is a simplified side view of the structure of a multi-die architecture FPGA to which the method of the present application is directed.

Fig. 2 is a top view of the corresponding structure of fig. 1.

Fig. 3 is another block diagram of a multi-die architecture FPGA to which the method of the present application is directed.

Fig. 4 is a flow chart of a layout method of the present application.

FIG. 5 is a schematic diagram of connection points and virtual stress points on two FPGA dies in the present application.

FIG. 6 is a schematic diagram of a selected sequence of the present application in selecting connection points on an FPGA die.

FIG. 7 is a schematic diagram of another selection sequence for selecting connection points on an FPGA die according to the present application.

FIG. 8 is a schematic diagram of another selection sequence for selecting connection points on an FPGA die according to the present application.

FIG. 9 is a schematic flow chart of a force-directed placement algorithm as used herein.

FIG. 10 is a schematic diagram of one of the force guidance placement algorithms.

FIG. 11 is another schematic diagram in a force guidance placement algorithm.

FIG. 12 is another schematic diagram in a force guidance placement algorithm.

FIG. 13 is another schematic diagram in a force guidance placement algorithm.

Fig. 14 is a side view in structural detail of a portion of the structure of fig. 1.

Detailed Description

The following further describes the embodiments of the present invention with reference to the drawings.

The application discloses a layout method of a multi-die structure FPGA based on circuit performance, which is a layout method for the multi-die structure FPGA, namely the FPGA does not only have one FPGA die but also comprises a plurality of FPGA dies, please refer to the structural schematic diagrams shown in figures 1 and 2, the FPGA dies are all stacked on the same silicon connection layer 1, the silicon connection layer 1 covers all the FPGA dies, figures 1 and 2 show schematic diagrams comprising three FPGA dies, which are respectively represented by a die 1, a die 2 and a die 3. Each FPGA bare chip is provided with a plurality of connection point leading-out terminals 2 connected with the internal signal path of the FPGA bare chip. The silicon connection layer 1 is internally provided with the cross-bare-chip connecting wires 3, the cross-bare-chip connecting wires 3 are distributed in the whole area or partial area of the silicon connection layer 1, and the cross-bare-chip connecting wires 3 are arranged in the silicon connection layer 1 in a layered and crossed manner, so that the cross-bare-chip connecting wires 3 are not influenced with each other. Since the silicon connection layer 1 covers all the FPGA dies, each FPGA die can be connected to any other FPGA die through the cross-die connection 3 according to the circuit requirement, the circuit interconnection between the dies is almost unlimited in space, each FPGA die can be connected to the adjacent FPGA die through the cross-die connection 3, or can be connected to the FPGA die at intervals through the cross-die connection 3, for example, in fig. 1 and 2, the die 1 can be connected to the die 2, and the die 1 can be connected to the die 3.

It should be noted that, in actual implementation, the internal structure of the multi-die FPGA may have a variety of variations, for example, the plurality of FPGA dies may be arranged on the silicon connection layer 1 in a one-dimensional manner as shown in fig. 1 and 2, or may be arranged in a two-dimensional stacking manner, that is, arranged along two directions, i.e., a horizontal direction and a vertical direction, on a horizontal plane, as shown in fig. 3, at this time, a cross-die connection line inside the silicon connection layer 1 is arranged in a cross manner along the two directions. However, no matter how the structure of the multi-die structure FPGA is deformed, as long as it forms the above-mentioned interconnect structure, it can be laid out by using the method of the present application, and for the convenience of understanding of those skilled in the art, the present application will add to the description of one implementation structure of the multi-die structure FPGA, but first, the present application describes the layout method as follows, and the layout method includes the following steps, please refer to fig. 4:

1. and acquiring a user input netlist, wherein the user input netlist is specific to the whole multi-die structure FPGA, and the total logic resource requirement of the user input netlist exceeds the number of logic resources on any one FPGA die but is less than or equal to the sum of the numbers of logic resources of all FPGA dies.

Firstly, cutting a user input netlist according to the number of logic resources contained in each FPGA bare chip, cutting the user input netlist into a plurality of sub netlists, wherein the sub netlists correspond to the FPGA bare chips one to one, and the number of the logic resources on each FPGA bare chip meets the logic resource requirements of the corresponding sub netlists, so that each FPGA bare chip can have enough resource layout. The cut sub netlists have connection relations, and each sub netlist is often connected with one or more other sub netlists, and one or more groups of signal connection relations are included between every two sub netlists.

2. After cutting the user input netlist, arranging the IO ports on the FPGA bare chips at the specified positions according to the sub netlist corresponding to each FPGA bare chip, and fixing the positions of all the IO ports. For each FPGA die, the method for fixing the IO port position according to the sub netlist includes but is not limited to the following methods:

(1) and manually arranging at least one IO port on the FPGA bare chip at a specified position by using an IO EDITOR software tool.

(2) And arranging at least one IO port on the FPGA bare chip at a specified position according to any sequence.

(3) And arranging at least one IO port on the FPGA bare chip at a specified position according to an IO automatic arrangement algorithm.

3. In a designed multi-die structure FPGA, two FPGA dies have a certain physical connection relationship, which is specifically represented as follows: the connection point leading-out terminals 2 in the two FPGA bare chips are connected through a cross-bare chip connecting wire 3, and the connection point leading-out terminals are connected in a signal path inside the FPGA bare chips, namely the connection point leading-out terminals are connected with the logic unit layout position inside the FPGA bare chips. Therefore, a logic cell layout position a-a connection point leading-out terminal a-cross die connection-a connection point leading-out terminal b-a logic cell layout position b form a connection path, wherein the logic cell layout position a and the connection point leading-out terminal a are on one FPGA die, and the connection point leading-out terminal b and the logic cell layout position b are on another FPGA die, for example, in fig. 5, 6 connection paths are formed between any mth FPGA die and nth FPGA die as shown in the figure. On the other hand, signal connection relations also exist between the sub netlists corresponding to the two FPGA dies, when the FPGA with the multi-die structure is laid out, the signal connection relations between the sub netlists corresponding to the FPGA dies need to be considered and formed, and the essence is that the signal connection relations between the FPGA dies need to be formed by using connection paths between the FPGA dies.

According to the method, when the signal connection relations among the bare chips are formed by laying out the FPGA bare chips, the corresponding connection paths are selected according to the circuit performance of the signal connection relations, therefore, in the step, firstly, circuit performance analysis is carried out on a user input netlist, the key indexes of the signal connection relations are determined according to the circuit performance of the signal connection relations among the sub netlists, and the worse the circuit performance of the signal connection relations is, the higher the corresponding key indexes are. In the present application, the circuit performance of the signal connection relationship may be of various types, different analysis methods are adopted for different types of circuit performance, and the specific analysis methods of various circuit performances can be realized by adopting an industry-wide method.

For example, in the present application, as a typical example, the circuit performance of a signal connection relationship is a delay length, the shorter the delay between a group of signal connection relationships is, the better the circuit performance is, and the lower the corresponding key index is, the corresponding circuit performance analysis includes timing analysis, and at this time, specifically: and determining the time margin of each group of signal connection relations through a static time sequence analysis STA based on the time sequence constraint condition, wherein the longer the time delay of the signal connection relations is, the smaller the time margin is, determining the corresponding key index according to the time margin of each group of signal connection relations, and the smaller the time margin of the signal connection relations is, the higher the corresponding key index is.

The circuit performance of the signal connection relation and the corresponding circuit performance analysis method can also comprise the following conditions:

the circuit performance analysis also comprises power consumption analysis, the circuit performance of the signal connection relation is a power consumption value, and the smaller the power consumption of the signal connection relation is, the better the circuit performance is;

and/or, the circuit performance analysis also comprises signal quality analysis, the circuit performance of the signal connection relation is a signal quality factor, and the higher the signal quality factor of the signal connection relation is, the better the circuit performance is;

and/or the circuit performance analysis also comprises on-chip power supply noise analysis, the circuit performance of the signal connection relation is a noise value, and the smaller the noise value of the signal connection relation is, the better the circuit performance is;

and/or the circuit performance analysis also comprises on-chip electromagnetic interference analysis, the circuit performance of the signal connection relation is a shielding coefficient, and the higher the shielding coefficient of the signal connection relation is, the better the circuit performance is.

4. And after determining the key indexes of each group of signal connection relations among the sub netlists, selecting corresponding connection points on the two corresponding FPGA bare chips according to the key indexes of each group of signal connection relations. The specific method comprises the following steps: and for each group of signal connection relations between two sub netlists corresponding to any two FPGA bare chips, respectively selecting logic unit layout positions on the two FPGA bare chips as connection points according to the key indexes of the signal connection relations to form each group of connection points for forming the signal connection relations, wherein the corresponding group of connection points form a connection path matched with the signal connection relations through a silicon connection layer.

The matching relationship between the signal connection relationship and the connection path in the present application means that the signal connection relationship is matched with the circuit performance of the same type of the connection path, specifically, the circuit performance of the signal connection relationship is in inverse proportion to the circuit performance of the same type of the connection path, that is: the circuit performance of the connection path matched with the circuit performance is better when the circuit performance of the signal connection relation is worse and the corresponding key index is higher; the better the circuit performance of the signal connection relation is, and the lower the corresponding key index is, the worse the circuit performance of the connection path matched with the signal connection relation is. For example, when the circuit performance of the signal connection is the delay length, the delay of the connection path matching the signal connection with longer delay is shorter. The circuit performance of the connection path is determined by the circuit structure, for example, the longer the winding distance of the connection path, the longer the time delay thereof if the connection path is provided with a corresponding analog device, and the like, similar to the signal connection relationship, the corresponding circuit performance can be determined by analyzing the circuit performance of the connection path, and the specific meaning and method can refer to the corresponding contents in the third step, which is not described in detail herein.

When the logic unit layout positions are respectively selected on the two FPGA bare chips to form a group of connection points, one logic unit layout position is actually selected on one FPGA bare chip to form one connection point, and the logic unit layout position has a fixed connection relation with one logic unit layout position on the other corresponding FPGA bare chip, so that the other corresponding connection point on the other FPGA bare chip can be determined immediately. The selected logic when selecting a logic cell layout location as a connection point on one of the FPGA dies includes, but is not limited to, the following two:

(1) and (4) selecting in a random order. Randomly selecting a logic unit layout position on the mth FPGA bare chip as an mth connection point, correspondingly determining the nth connection point on the nth FPGA bare chip, and completing the selection of a group of connection points.

(2) And selecting according to a preset selection order. And selecting a logic unit layout position on the mth FPGA die as an mth connection point according to a preset selection order, and correspondingly determining the nth connection point on the nth FPGA die to finish the selection of a group of connection points. The predetermined selection order includes, but is not limited to, the following:

(2-1) starting from a predetermined position on the FPGA die, in the order of the determinant structure along the lateral and longitudinal directions of the FPGA die. The predetermined positions are typically four corner positions of the FPGA die, and may be any other predetermined position on the FPGA die. The FPGA die comprises the following components in the order of the determinant structure along the transverse direction and the longitudinal direction of the FPGA die: and sequentially selecting logic unit layout positions in the current row from the starting point in the transverse direction as an m-th connection point, and returning to the next row at the starting point to continue to be sequentially selected in the transverse direction after all the logic unit layout positions in the current row are selected. Or, sequentially selecting logic unit layout positions in the current column from the starting point in the longitudinal direction as the mth connection point, and after all the logic unit layout positions in the current column are selected, returning to the next column at the starting point to continue to be sequentially selected in the longitudinal direction. The next row may be a row adjacent to the current row, or may be a row spaced several rows apart from the current row, and the same holds true for the definition of the next column. For example, taking the starting point as the upper left corner of the FPGA die as an example, the selected sequence is shown in fig. 6 when the starting point is selected according to the rank-based structure sequence along the horizontal direction and the next row is the adjacent row of the current row.

And (2-2) taking a predetermined position on the FPGA bare chip as a starting point, and sequentially arranging the predetermined positions along the transverse direction and the longitudinal direction of the FPGA bare chip according to an S-shaped structure, wherein the predetermined positions are usually four vertex angles of the FPGA bare chip and can be any other predetermined position on the FPGA bare chip. The FPGA die comprises the following steps in the order of S-shaped structures along the transverse direction and the longitudinal direction of the FPGA die: and sequentially selecting logic unit layout positions in the current row from the starting point in the transverse direction as an m-th connection point, and after all the logic unit layout positions in the current row are selected, continuously and sequentially selecting the logic unit layout positions in the reverse direction from the next row at the last logic unit layout position in the current row in the transverse direction. Or, sequentially selecting logic unit layout positions in the current column from the starting point in the longitudinal direction as the m-th connection point, and after all the logic unit layout positions in the current column are selected, continuously and sequentially selecting in the reverse direction from the next column at the last logic unit layout position in the current column. The definition of the next row and the next column is as above, and the detailed description of the present application is omitted. With reference to fig. 6, under the same setting, when the sequence of the S-shaped structure is adopted, please refer to fig. 7 for a schematic sequence diagram.

(2-3) taking a predetermined position on the FPGA bare chip as a starting point, and sequentially arranging the annular structures from outside to inside or from inside to outside along a clockwise or anticlockwise direction, wherein the predetermined position is usually four vertex angles of the FPGA bare chip, and can also be any other predetermined position on the FPGA bare chip. Each ring may be directly adjacent to the previous ring or may be spaced apart. For example, the starting point is the upper left corner of the FPGA die, and the sequence of the ring structures from the outside to the inside along the clockwise direction is selected, please refer to fig. 8.

It should be noted that, in the structure shown in fig. 1, when a group of connection points are selected on the die 1 and the die 2, the connection points may be selected on the die 1 to correspondingly determine the connection points on the die 2, or the connection points may be selected on the die 2 to correspondingly determine the connection points on the die 1. And besides the predefined connection relationship between the sub-netlists corresponding to the die 1 and the die 2, the predefined connection relationship may also exist between the sub-netlists corresponding to the die 2 and the die 3, provided that the connection point is selected by using a first selected logic on the die 1 so as to correspondingly determine the connection point on the die 2, and the connection point is defined by using a second selected logic on the die 2 so as to correspondingly determine the connection point on the die 3, the first selected logic and the second selected logic may be the same or different, for example, when the first selected logic is selected in a random order, the second selected logic may be selected in a random order, or may be selected in a sequence of a column structure from a starting point along the transverse direction and the longitudinal direction of the FPGA die. In addition, the die 1 may have a predetermined connection relationship with the sub-netlist corresponding to the die 2 and may also have a predetermined connection relationship with the sub-netlist corresponding to the die 3, and in this case, the connection points on the die 2 and the die 3 are determined by selecting the connection points on the die 1. In actual operation, the FPGA dies in the FPGA with the multi-die structure are subjected to the operation of selecting the connection point according to a predetermined sequence, for example, 10 FPGA dies are provided in total, it is assumed that the connection point is selected according to the sequence from the die 1 to the die 10, it is further assumed that the die 1 is connected to the die 2, the die 3, the die 5, and the die 9, the die 2 is connected to the die 1, the die 3, the die 5, and the die 6, and other examples are not illustrated in detail, and then the general method is as follows: the connection points between the die 2, the die 3, the die 5 and the die 9 are sequentially selected on the die 1 by the first selected logic, so that the connection points on the die 2, the die 3, the die 5 and the die 9 are correspondingly determined, after the connection points on the die 1 are all selected, the connection points between the die 3, the die 5 and the die 6 are sequentially selected on the die 2 by the second selected logic, so that the connection points on the die 3, the die 5 and the die 6 are correspondingly determined, and the like, and the same first selected logic and second selected logic can be the same or different.

In practical application, the situation that the signal connection relation is not matched with the number of the connection paths to be matched with the signal connection relation often exists, that is, when the key indexes of the P groups of signal connection relations between the two sub netlists corresponding to the two FPGA bare chips are the first key indexes, the logic unit layout positions on the two FPGA bare chips form the first connection paths which have the same performance and are corresponding to the first key indexes through the silicon connection layer. If P ═ Q then the quantity just matches at this moment, directly utilize Q first connecting paths to form the signal connection relation of the first key index of P group, but the condition that often appears P > Q or P < Q, this application's way is at this moment:

(1) if P is larger than Q, Q first connecting paths are used for forming the signal connection relation of the Q groups of first critical indexes, and a second connecting path between two FPGA dies is used for forming the signal connection relation of the remaining P-Q groups of first critical indexes, wherein the second connecting path is a connecting path with circuit performance worse than that of the first connecting path. When Q groups of signal connection relations are formed by using Q first connection paths, the selection logic for selecting Q groups of signal connection relations from the total number P groups of signal connection relations includes: and randomly forming a signal connection relation of the Q groups of first key indexes by using Q first connection paths. Or forming a signal connection relation of a first key index of the Q groups logically in advance according to the circuit logic sequence of the P groups of signal connection relations by utilizing the Q first connection paths.

Taking 6 connection paths shown in fig. 5 and taking circuit performance as time delay as an example, assume that in fig. 5, the time delays of path (i), path (iii) and path (ii) are all 5ns, the time delays of path (ii) and path (iv) are 8ns, and the time delay of path (v) is 10 ns. When 10 groups of signal connection relations need to be formed between the two FPGA bare chips, the time delay of 3 groups of signal connection relations is 3ns, the time delay of 3 groups of signal connection relations is 6ns, and the time delay of the remaining 4 groups of signal connection relations is 20 ns. The key index of 4 groups of signal connection relations with 20ns of time delay is the highest and matched with the path (i), the path (iii) and the path (ii) with the shortest time delay, that is, 3 connection paths with 5ns of time delay are needed to form 4 groups of signal connection relations with 20ns of time delay, then 3 groups of signal connection relations with 20ns of time delay are formed by using the path (i), the path (iii) and the path (ii), and then the remaining 1 group of signal connection relations with 20ns of time delay are formed by using the path (ii), the path (iii) and the path (iv) with poorer circuit performance, that is, 8ns of time delay.

(2) If P is less than Q, P first connecting paths are selected from the Q first connecting paths to form a signal connection relation of P groups of first key indexes. The selection logic to select P of the Q first connection paths comprises: and randomly selecting P first connection paths from the Q first connection paths. Or selecting P first connection paths according to a predetermined selection order according to the positions of the connection points of the Q first connection paths on one FPGA die, wherein the predetermined selection order is as follows: taking a predetermined position on the FPGA bare chip as a starting point, and sequentially arranging the FPGA bare chip in a determinant structure along the transverse direction and the longitudinal direction of the FPGA bare chip; or, taking a predetermined position on the FPGA bare chip as a starting point, and sequentially arranging the S-shaped structures along the transverse direction and the longitudinal direction of the FPGA bare chip; or, starting from a predetermined position on the FPGA die, the order of the ring structures from outside to inside or from inside to outside along the clockwise or counterclockwise direction. Reference may be made to fig. 6-8 and the corresponding description for details.

No matter what selection logic is adopted, after P first connection paths are selected to form a signal connection relation of P groups of first key indexes, Q-P first connection paths are remained, and then the Q-P first connection paths are used as connection paths corresponding to second key indexes, wherein the second key indexes are lower than the first key indexes. When the signal connection relationship of the second key index is formed, all the connection paths corresponding to the second key index include not only the connection path matched with the second key index itself, but also the remaining Q-P first connection paths, and at this time, the connection paths may be selected from all the connection paths corresponding to the second key index according to the same priority to form the signal connection relationship of the second key index, or the remaining Q-P first connection paths may be preferentially selected to form the signal connection relationship of the second key index.

Similarly, taking 6 connection paths shown in fig. 5 and taking circuit performance as time delay as an example, in fig. 5, the time delays of the path (i), the path (iii) and the path (ii) are all 5ns, the time delays of the path (ii) and the path (iv) are 8ns, and the time delay of the path (v) is 10 ns. When 10 groups of signal connection relations need to be formed between the two FPGA bare chips, the time delay of 6 groups of signal connection relations is 3ns, the time delay of 2 groups of signal connection relations is 6ns, and the time delay of the rest 2 groups of signal connection relations is 20 ns. The key index of 4 groups of signal connection relations with 20ns of time delay is the highest and is matched with the path (i), the path (iii) and the path (ii) with the shortest time delay, namely 3 connection paths with 5ns of time delay are needed to form 2 groups of signal connection relations with 20ns of time delay, then the path (i), the path (iii) and the path (ii) are used to form 2 groups of signal connection relations with 20ns of time delay, for example, the path (iii) and the path (iv) are randomly selected, and then the path (iii) and the path (iii) are selected according to the line-type structure sequence from the lower left corner according to the position of the 3 connection paths on the mth FPGA bare chip. Assuming that the selected path (c) and the path (c) form a signal connection relationship in which 2 groups of time delays are 20ns, the remaining path (c) is used for forming a signal connection relationship in which the key index is lower and the time delay is 6 ns.

At this time, for 2 groups of signal connection relations with the time delay of 6ns, all the corresponding connection paths comprise a path (i) and a path (ii) which are matched with the key index and have the time delay of 8ns, and also comprise the remaining unselected paths (i), namely, the 2 groups of signal connection relations with the time delay of 6ns are formed by utilizing 3 connection paths comprising the path (i), the path (ii) and the path (ii). At this time, the last group of the remaining paths can be preferentially selected to form a group of signal connection relations, and then one path is selected from the paths and the paths to form another group of signal connection relations, and the specific selection method can refer to the condition that P is greater than Q. Or the path (i), the path (ii) and the path (iv) may be according to the same priority, and then 2 connection paths may be selected from 3 connection paths to form a signal connection relationship using the above case that P > Q.

5. After selecting the sets of connection points, selecting a corresponding virtual force application point for each set of connection points: and respectively selecting connection point leading-out ends on the two FPGA bare chips to add virtual stress points to form a group of virtual stress points. Because the sub netlists are connected, the connection relation between the FPGA bare chip and other FPGA bare chips needs to be taken into consideration when a certain FPGA bare chip is subjected to single-die layout, and therefore the connection relation between different sub netlists is taken into consideration by adding a virtual stress point on the FPGA bare chip. For a group of connection points formed by an mth connection point on an mth FPGA die and an nth connection point on an nth FPGA die, a method for adding a group of virtual stress points to the group of connection points is as follows: and adding an mth virtual stress point corresponding to the mth connection point at the connection point leading-out end closest to the mth connection point on the mth FPGA bare chip, adding an nth virtual stress point corresponding to the nth connection point at the connection point leading-out end closest to the mth virtual stress point on the nth FPGA bare chip, and forming a group of virtual stress points by the mth virtual stress point and the nth virtual stress point.

For example, in fig. 5, the mth connection point (denoted by m in the figure) of the mth FPGA die and the mth connection point (denoted by n in the figure) of the nth FPGA die form a path (r) through the silicon connection layer, and then the mth virtual stress point (denoted by m 'in the figure) is added to the mth FPGA die, and the nth virtual stress point (denoted by n' in the figure) is added to the nth FPGA die, and m 'and n' form a set of virtual stress points.

It should be noted that, although fig. 5 shows that the mth FPGA die and the nth FPGA die are arranged adjacently, the same is true in the case that the mth FPGA die and the nth FPGA die are not adjacent.

6. After the configuration of the IO port, the connection point and the virtual stress point of each FPGA bare chip is completed, for each FPGA bare chip, the FPGA bare chip is distributed based on the traction action of the virtual stress point on the FPGA bare chip on the corresponding connection point and the traction action of the IO port at the specified position according to the sub-netlist corresponding to the FPGA bare chip and the force-oriented layout algorithm model.

Referring to fig. 9, a flow chart of the algorithm of the quadratic algorithm used in the single die layout is shown, and the principle of the quadratic algorithm is described as follows:

and (5-1) establishing a Quadratic netlist model.

In the placement netlist, all logic cell placement positions can be regarded as nodes, and the signal relationship among all nodes is established as a point-to-point edge relationship. As shown in FIG. 10, there are 5 nodes in the netlist, node A, B, C, D, E, and signal 1 is output from node A to 4 destinations on node B, C, D, E. During modeling, signal 1 is converted into edge 1, edge 2, edge 3 and edge 4 in the graph, and a point- > edge- > point model is formed. Thus, when the layout is performed with the line length as the constraint condition, the shortest line length from the source end a to the destination end B, C, D, E of the signal 1 can be equivalently regarded as the shortest sum of the side lengths of the side 1, the side 2, the side 3 and the side 4. Then the layout optimization goal is to minimize the sum of the lengths of all edges in the netlist for the entire netlist.

As shown in FIG. 10, assume node A (x)₁,y₁)，B(x₂,y₂) If the sizes of the nodes A and B are ignored, and the weight of the edge 1 is assumed to be 1, the length of the edge 1 is

From the expression of the length of the edge 1, the length of the edge 1 is positively correlated to the expression (x)₂-x₁)²+(y₂-y₁)²I.e. length is in (x)₂-x₁)²+(y₂-y₁)²Taking the minimum value is to obtain the minimum value.

(5-2) constructing a solving matrix.

For the entire netlist, assuming n nodes, the optimization objective function can be equivalent to:

from the quadratic property of the objective function, the minimum value is obtained when its partial derivative is 0, i.e.:

to be written as a matrixThe equation form AX ═ B, AY ═ B. To illustrate, as shown in fig. 11, suppose A, B, E, F is 4 fixed points in the netlist, where the X coordinates of A, B are all 10, the X coordinates of E, F are all 40, and C, D is the layout target point, the positions need to be determined so that the line length of the whole netlist is minimal. The objective function in the X-direction can be established as:

φ＝(x_c-10)²+2(x_c-10)²+(x_d-x_c)²+(x_d-40)²+2(x_d-40)² (1)

for the target function respectively at x_c、x_dThe partial derivative is obtained by the above calculation:

obtaining a minimum value from its partial derivative as 0 to obtain a matrix equation

Solved and obtained x_c＝16,x_dIn this case, the net length is set to 34, i.e., the minimum value. During layout, the X coordinate of the node C is determined to be 16, the X coordinate of the node D is determined to be 34, and the Y-direction coordinate is solved in the similar X direction.

Also in the above example, the X coordinate of node C is found to be 16 and the X coordinate of D is found to be 34, so that the fixed point A, B can be considered to produce a left-hand pulling force on C in the X direction when viewed from node C. The movable point D pair C can be considered to generate a rightward pulling force in the X direction, and the magnitude is as follows: force_right＝w_cd(x_d-x_c) 1 (34-16) ═ 18. It can be seen that point C is in a force balance state in the X direction, and similarly, D is also in a force balance state. After the netlist structure is built by the force model, when the position of the movable point is changed in the layout, the target node can be added with a fixed force according to the force balance model.

(5-3) a congested area spreading method.

The logic unit positions obtained by the method for obtaining the extreme value according to the partial derivative of the quadratic function have logic unit overlapping to a large extent, and the premise condition of legal layout is that the logic units cannot be overlapped. Therefore, the solved result needs to be expanded, so that the continuous overlapping is reduced.

As shown in fig. 12, there are 1, 2, 3, 4, 5 nodes in the 5 blocks from left to right in sequence, and it is assumed that the maximum capacity of each block in the figure is 3 nodes. The dotted line in the figure is used as a cutting line, and if the number of nodes in unit squares on the left and right sides of the cutting line is the same, a plurality of nodes need to be moved from the left side to the right side of the cutting line or from the right side to the left side of the cutting line. Assuming that the movement from the left to the right of the cut line is positive, how the equation can be established:

wherein L is_nRepresenting the number of nodes to the left of the cutting line, R_nRepresenting the number of nodes to the right of the cutting line, L_cRepresenting the sum of the volumes of the squares to the left of the cutting line, R_cRepresents the sum of the volumes of the squares to the right of the cut line and P represents the number of nodes that need to be moved to the right. Can be derived from the equation

Namely, it is

Wherein T is_cRepresenting the sum of the capacities of all the squares.

Assuming that the capacity of a square is proportional to the length of the square, we can convert the movement of the node into the movement of the square edge where the cutting line is located, as shown in fig. 12. Assuming that the right movement is positive, the movement of the square edge on which the cutting line is located

Where P is the number of nodes that need to be moved to the right, W_bIs the width of a single square grid, C_bThe capacity of a single square. Assuming the width of the square is 1, then

According to the solution result, the square edge where the cutting line is located needs to be moved to the left

Distance.

In calculating X_mThen, the squares representing the left and right sides of the cut line need to be compressed or expanded by a distance X_mAnd equivalently, the nodes on the left side and the right side of the cutting line stretch respectively according to the frame. That is, the equation may hold for the node to the left of the cut line:

the node to the right of the cut line may be formed as an equation

Where min represents the x coordinate of the left boundary of the full row of tiles, max represents the x coordinate of the right boundary of the full row of tiles, L_lRepresents the sum of the lengths of the squares to the left of the cutting line, L_rRepresenting the sum of the lengths of the squares to the right of the cutting line, x_oriRepresenting the original x-coordinate value, x, of the node_newRepresenting the new coordinates of the required nodes. Through the above equation, the target position of the node can be obtained, and if the positive direction is represented by the rightward direction, it can be obtained that the node needs to move the distance x rightward_new-x_ori。

By the method, the cutting line is sequentially moved to the right by one square grid, and the new positions of all the nodes based on node density balance can be obtained by recalculation. After a plurality of iterations, the nodes in the target range can be pulled more uniformly. According to the force model described above, if a node needs to be moved a certain distance in the netlist, how to equivalently think that a force is applied in the moving direction to make the node in a new equilibrium stateState. As shown in fig. 13, point D is originally in a force equilibrium state of a, B, and C, and it is now necessary to move D to the position of D ', a fixed point E may be added to the right of point D to generate a force pulling D toward D ', i.e., a pulling force of f ═ D ' -D |. At point E, the weight of the force added can be considered to be

Where w represents the weight of the link between D, E, L_deRepresents the distance of D, E in the X direction.

Therefore, when the single-die layout is performed on each FPGA die based on the algorithm model, the method comprises the following steps: regarding the layout positions of the logic units in the sub netlist as nodes, establishing a signal relationship between the nodes into a point-to-point edge relationship, and establishing a force-directed layout algorithm model according to the sub netlist; solving a force guidance layout algorithm model under the traction action of an IO port to obtain the position of each node in a force balance state; breaking the force balance state under the traction action of the virtual stress point on the corresponding node serving as the connection point, and solving the force-oriented layout algorithm force model again to obtain an initial layout structure; and uniformly spreading the initial layout structure until the iteration reaches an iteration termination condition.

Based on the layout method, in the example shown in fig. 5, when the mth FPGA die layout is solved, the mth virtual stress point pulls the mth connection point to approach to the mth virtual stress point, and when the nth FPGA die layout is solved, the nth virtual stress point pulls the nth connection point to approach to the nth virtual stress point. Therefore, when the multiple bare chips are separately arranged, the points with the connection relation among the bare chips can be pulled close to one direction, and the purpose of optimizing the connection relation among the bare chips is achieved.

Thus, having described the layout method for the multi-die FPGA provided in the present application, in order to make the skilled person have a clearer understanding of the physical connection relationship between the PFGA dies and thus better understand the layout method of the present application, the present application describes a structure of the multi-die FPGA in detail as follows, please refer to fig. 14, the multi-die FPGA includes, in addition to the silicon connection layer 1 and the plurality of dies, a substrate 4 disposed below the silicon connection layer 1, and actually further includes a package housing packaged outside the substrate 4, the silicon connection layer 1 and the FPGA dies for protecting each component, and further includes pins and the like connected to the substrate for signal extraction.

Each FPGA bare chip is provided with a connection point leading-out end 2, the interior of each FPGA bare chip also comprises a logic unit, and the connection point leading-out end 2 is connected with the logic unit in the FPGA bare chip through a top layer metal wire in a redistribution layer (RDL layer). In practical application, the logic unit in the FPGA die includes a conventional logic unit and a silicon stacking connection point 5, the conventional logic unit is a CLB, a PLBs, an IOB, a BRAM, a DSP, a PC, etc., and the silicon stacking connection point is a special logic unit designed specifically inside the die for meeting the signal interconnection requirement between the dies. All logic cells have an interconnection resource distributed around the logic cells, and the logic cells are connected via the interconnection resource such that the silicon stack connection point 5 is connected to other conventional logic cells. And the silicon stack connection point is connected with the connection point leading-out terminal 2 through a top layer metal wire in the RDL layer.

The micro-convex ball grows on the FPGA bare chip, the connection point leading-out end 2 is connected with the silicon connection layer 1 through the micro-convex ball and is connected to other FPGA bare chips through a cross bare chip connection wire 3 inside the silicon connection layer 1, and the micro-convex ball structure at the bottom of the FPGA bare chip can be seen in figure 14. Micro convex balls grow on one side of the silicon connecting layer 1, which is far away from the FPGA bare chip, and the silicon connecting layer 1 is connected with the substrate 4 through the micro convex balls. In addition, a through silicon via 6 is further formed in the silicon connection layer 1, and the IOB on the FPGA bare chip is connected to the substrate 1 through the through silicon via 6 on the silicon connection layer 1 so as to finally lead out a signal.

What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.

Claims

1. A layout method of a multi-die structure FPGA based on circuit performance is characterized in that the multi-die structure FPGA comprises a silicon connection layer and a plurality of FPGA dies stacked on the silicon connection layer, each FPGA die is provided with a plurality of connection point leading-out ends connected with internal signal paths of the FPGA dies, and the connection point leading-out ends in each FPGA die are connected with connection point leading-out ends of any other FPGA die through a cross-die connection line in the silicon connection layer to realize interconnection among the FPGA dies, and the method comprises the following steps:

the method comprises the steps of obtaining a user input netlist, cutting the user input netlist into a plurality of connected sub netlists according to the number of logic resources contained in each FPGA bare chip, wherein the sub netlists are in one-to-one correspondence with the FPGA bare chips, and the number of the logic resources on each FPGA bare chip meets the logic resource requirements of the corresponding sub netlists;

performing circuit performance analysis on the user input netlist, and determining a key index of each group of signal connection relations according to the circuit performance of each group of signal connection relations among the sub netlists, wherein the worse the circuit performance of the signal connection relations is, the higher the corresponding key index is;

for each group of signal connection relations between two sub netlists corresponding to any two FPGA bare chips, respectively selecting logic unit layout positions on the two FPGA bare chips as connection points according to the key indexes of each group of signal connection relations to form each group of connection points for forming each group of signal connection relations, wherein the higher the key index of the signal connection relation is, the better the circuit performance of a connection path formed by the corresponding group of connection points through the silicon connection layer is;

after the configuration of the IO port, the connection point and the virtual stress point of each FPGA bare chip is completed, for each FPGA bare chip, the FPGA bare chips are distributed according to the sub-netlist corresponding to the FPGA bare chip by using a force-oriented layout algorithm model based on the traction action of the virtual stress point on the FPGA bare chip on the corresponding connection point and the traction action of the IO port at the specified position.

2. The method of claim 1, wherein the circuit performance analysis comprises timing analysis, and the circuit performance of the signal connection relation and the connection path is a delay length, and the shorter the delay, the better the circuit performance;

then, the analyzing the circuit performance of the user input netlist and determining the key index of each group of signal connection relations according to the circuit performance of each group of signal connection relations among the sub netlists includes:

and determining corresponding key indexes according to the time margins of the signal connection relations of each group, wherein the smaller the time margin of the signal connection relation is, the higher the corresponding key index is.

3. The method of claim 2,

the circuit performance analysis also comprises power consumption analysis, the signal connection relation and the circuit performance of the connection path are power consumption values, and the smaller the power consumption is, the better the circuit performance is;

and/or the circuit performance analysis also comprises on-chip power supply noise analysis, wherein the circuit performance of the signal connection relation and the connection path is a noise value, and the smaller the noise value is, the better the circuit performance is;

4. The method according to any one of claims 1-3, further comprising:

when the key indexes of P groups of signal connection relations between the two sub netlists corresponding to the two FPGA bare chips are first key indexes, and the logic unit layout positions on the two FPGA bare chips form Q first connection paths which have the same circuit performance and correspond to the first key indexes through the silicon connection layer;

and if P is less than Q, selecting P first connecting paths from the Q first connecting paths to form a signal connection relation of P groups of first key indexes, and taking the remaining Q-P first connecting paths as connecting paths corresponding to a second key index which is lower than the first key index.

5. The method according to claim 4, wherein when P > Q, the signal connection relationship of Q groups of first key indexes is formed by using Q first connection paths, and the method comprises the following steps:

randomly forming a signal connection relation of Q groups of first key indexes by using the Q first connection paths;

or forming a signal connection relation of a first key index of the Q groups with logic prior according to the circuit logic sequence of the P groups of signal connection relations by using the Q first connection paths.

6. The method according to claim 4, wherein when P < Q, said selecting P first connection paths from the Q first connection paths to form a signal connection relationship of P sets of first key indexes comprises:

7. The method of claim 4, wherein when P < Q, in forming the signal connection relationship of the second key exponent:

selecting connection paths from all connection paths corresponding to the second key index according to the equal priority to form a signal connection relation of the second key index;

or preferentially selecting the remaining Q-P first connecting paths to form the signal connection relation of the second key index.

8. The method of claim 1, wherein adding virtual stress points to the respectively selected pinout of the two FPGA dies according to the set of pinouts to form a set of virtual stress points corresponding to the set of pinouts comprises:

adding an mth virtual stress point corresponding to an mth connection point at a connection point leading-out end closest to the mth connection point on the mth FPGA die for a group of connection points formed by the mth connection point on the mth FPGA die and the nth connection point on the nth FPGA die; adding an nth virtual stress point corresponding to the nth connection point at a connection point leading-out end closest to the mth virtual stress point on the nth FPGA die, wherein the mth virtual stress point and the nth virtual stress point form a group of virtual stress points.

9. The method of claim 1, wherein the arranging the IO ports on the FPGA die in designated locations comprises: and randomly arranging at least one IO port on the FPGA bare chip at a designated position by using an IO EDITOR software tool.

10. The method of claim 1, wherein the arranging the IO ports on the FPGA die in designated locations comprises: and manually arranging at least one IO port on the FPGA bare chip at an appointed position according to any sequence by using an IO EDITOR software tool.

11. The method of claim 1, wherein the arranging the IO ports on the FPGA die in designated locations comprises: and arranging at least one IO port on the FPGA bare chip at a specified position according to an IO automatic arrangement algorithm.

12. The method according to claim 1, wherein the step of laying out the FPGA die according to the sub netlist corresponding to the FPGA die by using a force-oriented layout algorithm model based on a traction effect of a virtual force application point on the FPGA die on a corresponding connection point and a traction effect of an IO port at a specified position comprises:

regarding the layout positions of the logic units in the sub netlist as nodes, establishing a signal relationship between the nodes into a point-to-point edge relationship, and establishing a force-oriented layout algorithm model according to the sub netlist;

solving the force-oriented layout algorithm model under the traction action of the IO port to obtain the position of each node in a force balance state;

breaking the force balance state under the traction action of the virtual stress point on the corresponding node serving as the connection point, and solving the force-oriented layout algorithm model again to obtain an initial layout structure;

and uniformly spreading the initial layout structure until iteration reaches an iteration termination condition.