CN111753482B - Layout method of multi-die structure FPGA with automatic IO distribution - Google Patents

Layout method of multi-die structure FPGA with automatic IO distribution Download PDF

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CN111753482B
CN111753482B CN202010611920.2A CN202010611920A CN111753482B CN 111753482 B CN111753482 B CN 111753482B CN 202010611920 A CN202010611920 A CN 202010611920A CN 111753482 B CN111753482 B CN 111753482B
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fpga
connection
bare chip
fpga bare
layout
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CN111753482A (en
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单悦尔
虞健
徐彦峰
惠锋
闫华
张艳飞
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CETC 58 Research Institute
Wuxi Zhongwei Yixin Co Ltd
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CETC 58 Research Institute
Wuxi Zhongwei Yixin Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/343—Logical level

Abstract

The invention discloses a layout method of an FPGA (field programmable gate array) with an IO (input/output) automatic distribution multi-die structure, which relates to the technical field of the FPGA and is characterized in that a large user input net list is cut into a plurality of small sub net lists, each FPGA die can be ensured to have enough resources to layout each small sub net list, mutual traction layout of single dies is carried out after the initial position of an IO port is given, the IO port is set to be in an undistributed state after the initial layout is finished, then the layout is carried out again, and the layout positions of all the IO ports are redetermined according to the latest layout condition, so that the connecting line between the IO port and an internal net list is shortest, and a better layout effect is achieved.

Description

Layout method of multi-die structure FPGA with automatic IO distribution
Technical Field
The invention relates to the technical field of FPGA, in particular to a layout method of an FPGA with an IO automatic allocation multi-die structure.
Background
A Field Programmable Gate Array (FPGA) is a general-purpose Programmable logic device, and a user can flexibly configure the FPGA as required to implement different circuit functions. When designing the FPGA circuit, a user firstly writes a circuit hardware description language according to the circuit function to be realized and converts the circuit hardware description language into a corresponding user input netlist, and then performs layout and wiring on the FPGA chip according to the user input netlist. The number of logic resources of the FPGA chip needs to meet the logic resource requirement of the user input netlist, so that along with the continuous expansion of the user design, the scale of the logic resources of the FPGA chip must be correspondingly increased, but along with the increase of the scale of the chip, the processing difficulty of the chip is higher and higher, and the growth yield of the chip is lower and lower.
Disclosure of Invention
The invention provides a layout method of an FPGA with an IO automatic allocation multi-die structure aiming at the problems and the technical requirements, and the technical scheme of the invention is as follows:
a layout method of an FPGA with an IO automatic allocation multi-die structure comprises a silicon connection layer and a plurality of FPGA dies stacked on the silicon connection layer, wherein each FPGA die is provided with a plurality of connection point leading-out ends connected with signal paths inside the FPGA die, and the connection point leading-out end in each FPGA die is connected with the connection point leading-out end of any other FPGA die through a cross-die connection line in the silicon connection layer to realize interconnection among the FPGA dies, and the method comprises the following steps:
acquiring a user input netlist, and cutting the user input netlist into a plurality of connected sub-netlists according to the number of logic resources contained in each FPGA bare chip, wherein the sub-netlists correspond to the FPGA bare chips one to one, and the number of the logic resources on each FPGA bare chip meets the logic resource requirements of the corresponding sub-netlists;
arranging IO ports on the FPGA bare chips at initial positions according to the sub netlist corresponding to each FPGA bare chip;
selecting mutual traction points on the two FPGA bare chips according to the connection relation between the two sub netlists corresponding to the two FPGA bare chips and a connection path formed by the silicon connection layer between the FPGA bare chips, and performing initial layout on the FPGA bare chips by utilizing a force-oriented layout algorithm model according to the sub netlist corresponding to each FPGA bare chip based on the traction action of an IO port on each FPGA bare chip and the mutual traction points;
and (3) the IO ports at the initial positions on all the FPGA bare chips are released from being laid out to be in an undisposed state, the FPGA bare chips are re-laid by utilizing the force guiding layout algorithm model, and the layout positions of the IO ports on the FPGA bare chips are determined according to the re-laid structure.
The further technical scheme is that the method for determining the layout position of the IO port on the FPGA bare chip according to the re-laid structure comprises the following steps:
and arranging the IO ports on the FPGA bare chip at the position with the shortest connecting line of the sub netlist corresponding to the FPGA bare chip according to the structure of the re-layout of the FPGA bare chip to obtain the layout position of the IO ports on the FPGA bare chip.
The further technical scheme is that the IO ports on the FPGA bare chip are arranged at the initial position, and the method comprises the following steps:
randomly arranging at least one IO port on the FPGA bare chip at an initial position by using an IO EDITOR software tool;
or, manually arranging at least one IO port on the FPGA bare chip at an initial position according to any sequence by using an IO EDITOR software tool;
or at least one IO port on the FPGA bare chip is randomly arranged at the initial position according to an IO automatic arrangement algorithm.
The further technical scheme is that mutual traction points are respectively selected on the two FPGA bare chips according to the connection relation between the two sub netlists corresponding to the two FPGA bare chips and the connection path formed by the silicon connection layer between the FPGA bare chips, and the FPGA bare chips are initially laid out by utilizing a force guiding layout algorithm model based on the traction action of the IO port on each FPGA bare chip and the mutual traction points according to the sub netlists corresponding to each FPGA bare chip, and the method comprises the following steps:
for any group of preset connection relations between two sub netlists corresponding to the two FPGA bare chips, logic unit layout positions connected through a silicon connection layer are respectively selected on the two FPGA bare chips to serve as connection points to form a group of connection points for forming the preset connection relations, and virtual stress points are added to leading-out ends of the selected connection points on the two FPGA bare chips according to the group of connection points to form a group of virtual stress points;
and initially arranging the FPGA bare chips by utilizing a force guiding arrangement algorithm model based on the IO port on each FPGA bare chip and the traction action of the virtual stress point on the FPGA bare chips on the corresponding connection point according to the sub netlist corresponding to each FPGA bare chip.
The further technical scheme is that logic unit layout positions connected through a silicon connection layer are respectively selected on two FPGA bare chips to serve as connection points to form a group of connection points used for forming a preset connection relation, and the method comprises the following steps:
randomly selecting or selecting a logic unit layout position as an mth connection point on one mth FPGA die according to a preset selection sequence, determining that the logic unit layout position connected with the mth connection point on the other nth FPGA die through a silicon connection layer is the nth connection point on the nth FPGA die, and enabling the mth connection point and the nth connection point to form a preset connection relation;
the further technical scheme is that the preset selection sequence is as follows: taking a predetermined position on the FPGA bare chip as a starting point, and sequentially arranging the FPGA bare chip in a determinant structure along the transverse direction and the longitudinal direction of the FPGA bare chip; or, taking a predetermined position on the FPGA bare chip as a starting point, and sequentially arranging the S-shaped structures along the transverse direction and the longitudinal direction of the FPGA bare chip; or, starting from a predetermined position on the FPGA die, the order of the ring structures from outside to inside or from inside to outside along the clockwise or counterclockwise direction.
The further technical scheme is that mutual traction points are respectively selected on the two FPGA bare chips according to the connection relation between the two sub netlists corresponding to the two FPGA bare chips and the connection path formed by the silicon connection layer between the FPGA bare chips, and the FPGA bare chips are initially laid out by utilizing a force guiding layout algorithm model based on the traction action of the IO port on each FPGA bare chip and the mutual traction points according to the sub netlists corresponding to each FPGA bare chip, and the method comprises the following steps:
determining a time sequence key index of a predetermined connection relation for any group of predetermined connection relations between two sub netlists corresponding to the two FPGA bare chips, wherein the longer the time delay of the predetermined connection relation is, the higher the corresponding time sequence key index is;
determining link time delay of each connection path formed by logic unit layout positions connected through a silicon connection layer in the two FPGA bare chips;
respectively selecting logic unit layout positions connected through a silicon connection layer on the two FPGA bare chips as connection points to form a group of connection points for forming the predetermined connection relation according to the time sequence key index of the predetermined connection relation and the link time delay of each connection path between the two FPGA bare chips; the link time delay of a connection path between a group of connection points corresponds to the time sequence key index of a preset connection relation, and the higher the time sequence key index of the preset connection relation is, the shorter the link time delay of the corresponding connection path is;
respectively selecting connection point leading-out ends on the two FPGA bare chips according to the group of connection points and adding virtual stress points to form a group of virtual stress points;
and initially arranging the FPGA bare chips by utilizing a force guiding arrangement algorithm model based on the IO port on each FPGA bare chip and the traction action of the virtual stress point on the FPGA bare chips on the corresponding connection point according to the sub netlist corresponding to each FPGA bare chip.
The further technical scheme is that a connection point leading-out end is respectively selected on two FPGA bare chips according to a group of connection points, and virtual stress points are added to form a group of virtual stress points, and the method comprises the following steps:
for a group of connection points formed by an mth connection point on an mth FPGA bare chip and an nth connection point on an nth FPGA bare chip, an mth virtual stress point corresponding to the mth connection point is added at a connection point leading-out end, closest to the mth connection point, on the mth FPGA bare chip, an nth virtual stress point corresponding to the nth connection point is added at a connection point leading-out end, closest to the mth virtual stress point, on the nth FPGA bare chip, and the mth virtual stress point and the nth virtual stress point form a group of virtual stress points.
The further technical scheme is that mutual traction points are respectively selected on the two FPGA bare chips according to the connection relation between the two sub netlists corresponding to the two FPGA bare chips and the connection path formed by the silicon connection layer between the FPGA bare chips, and the FPGA bare chips are initially laid out by utilizing a force guiding layout algorithm model based on the traction action of the IO port on each FPGA bare chip and the mutual traction points according to the sub netlists corresponding to each FPGA bare chip, and the method comprises the following steps:
for a first FPGA bare chip, performing initial layout on the first FPGA bare chip based on an IO port on the first FPGA bare chip by using a force-oriented layout algorithm model according to a sub netlist corresponding to the first FPGA bare chip, wherein logic units with connection relations between the sub netlists corresponding to other FPGA bare chips on the first FPGA bare chip are arranged at an optimal position and form a connection point on the first FPGA bare chip;
for the (i + 1) th FPGA bare chip, determining that the layout position of a logic unit connected with the connection point on the (i) th FPGA bare chip through a silicon connection layer on the (i + 1) th FPGA bare chip is the connection point connected with the (i) th FPGA bare chip on the (i + 1) th FPGA bare chip, selecting a connection point leading-out end closest to the (q) th connection point on the (i + 1) th FPGA bare chip according to the (q) th connection point connected with the (p) th connection point on the (i + 1) th FPGA bare chip to add a virtual stress point corresponding to the (p) th connection point, and initially laying out the (i + 1) th FPGA bare chip according to a sub netlist corresponding to the (i + 1) th FPGA bare chip by utilizing a stress guide layout algorithm model based on the traction action of the virtual stress point on the (i + 1) th FPGA bare chip on the corresponding connection point and the traction action of an IO port, wherein the starting value of the (i) is 1.
The further technical scheme is that the (i + 1) th FPGA bare chip is an FPGA bare chip adjacent to the ith FPGA bare chip.
The further technical scheme is that the (i + 1) th FPGA bare chip is the FPGA bare chip corresponding to the sub-netlist which has the most connection relation with the sub-netlist corresponding to the ith FPGA bare chip.
According to the further technical scheme, the method for initially arranging the FPGA bare chips by utilizing the force-oriented layout algorithm model based on the traction action of the IO ports and the mutual traction points on each FPGA bare chip according to the sub netlist corresponding to each FPGA bare chip comprises the following steps:
regarding the layout positions of the logic units in the sub netlist as nodes, establishing a signal relationship between the nodes into a point-to-point edge relationship, and establishing a force-directed layout algorithm model according to the sub netlist;
solving a force guidance layout algorithm model under the traction action of an IO port to obtain the position of each node in a force balance state;
breaking the force balance state under the traction action of the mutual traction points, and solving the force-oriented layout algorithm model again to obtain an initial layout structure;
and uniformly spreading the initial layout structure until the iteration reaches an iteration termination condition.
The beneficial technical effects of the invention are as follows:
the application discloses a layout method of an FPGA with an IO automatic distribution multi-die structure, a large user input net list is cut into a plurality of small sub net lists, each FPGA die can be guaranteed to have enough resources to layout each small sub net list, mutual traction layout of single dies is carried out after the initial position of an IO port is given, the IO port is set to be in an undistributed state after the initial layout is completed, then the layout is carried out again, the layout positions of all the IO ports are determined again according to the latest layout condition, the IO port and an internal net list connecting line are enabled to be shortest, and a better layout effect is achieved.
Drawings
FIG. 1 is a simplified side view of the structure of a multi-die architecture FPGA to which the method of the present application is directed.
Fig. 2 is a top view of the corresponding structure of fig. 1.
Fig. 3 is another block diagram of a multi-die architecture FPGA to which the method of the present application is directed.
Fig. 4 is a flow chart of a layout method of the present application.
FIG. 5 is a schematic diagram of connection points and virtual stress points on two FPGA dies in the present application.
FIG. 6 is a schematic diagram of one of the force guidance placement algorithms.
FIG. 7 is another schematic diagram in a force guidance placement algorithm.
FIG. 8 is another schematic diagram in a force guidance placement algorithm.
FIG. 9 is another schematic diagram in a force guidance placement algorithm.
Fig. 10 is a side view in structural detail of a portion of the structure of fig. 1.
Detailed Description
The following further describes the embodiments of the present invention with reference to the drawings.
The application discloses a layout method of an FPGA with an IO automatic allocation multi-die structure, which is a layout method for an FPGA with a multi-die structure, namely the FPGA does not only have one FPGA die but also comprises a plurality of FPGA dies, please refer to the structural schematic diagrams shown in fig. 1 and 2, the FPGA dies are all stacked on the same silicon connection layer 1, the silicon connection layer 1 covers all the FPGA dies, and fig. 1 and 2 show schematic diagrams comprising three FPGA dies, which are respectively represented by a die 1, a die 2 and a die 3. Each FPGA bare chip is provided with a plurality of connection point leading-out terminals 2 connected with the internal signal path of the FPGA bare chip. The silicon connection layer 1 is internally provided with the cross-bare-chip connecting wires 3, the cross-bare-chip connecting wires 3 are distributed in the whole area or partial area of the silicon connection layer 1, and the cross-bare-chip connecting wires 3 are arranged in the silicon connection layer 1 in a layered and crossed manner, so that the cross-bare-chip connecting wires 3 are not influenced with each other. Since the silicon connection layer 1 covers all the FPGA dies, each FPGA die can be connected to any other FPGA die through the cross-die connection 3 according to the circuit requirement, the circuit interconnection between the dies is almost unlimited in space, each FPGA die can be connected to the adjacent FPGA die through the cross-die connection 3, or can be connected to the FPGA die at intervals through the cross-die connection 3, for example, in fig. 1 and 2, the die 1 can be connected to the die 2, and the die 1 can be connected to the die 3.
It should be noted that, in actual implementation, the internal structure of the multi-die FPGA may have a plurality of variations, for example, the plurality of FPGA dies may be arranged on the silicon connection layer 1 in a one-dimensional manner as shown in fig. 2, or may be arranged in a two-dimensional stacking manner, that is, arranged along two directions, i.e., a horizontal direction and a vertical direction, on a horizontal plane, as shown in fig. 3, at this time, a cross-die connection line inside the silicon connection layer 1 is arranged in a crossing manner along the two directions. However, no matter how the structure of the multi-die structure FPGA is deformed, as long as it forms the above-mentioned interconnect structure, it can be laid out by using the method of the present application, and for the convenience of understanding of those skilled in the art, the present application will add to the description of one implementation structure of the multi-die structure FPGA, but first, the present application describes the layout method as follows, and the layout method includes the following steps, please refer to fig. 4:
1. and acquiring a user input netlist, wherein the user input netlist is specific to the whole multi-die structure FPGA, and the total logic resource requirement of the user input netlist exceeds the number of logic resources on any one FPGA die but is less than or equal to the sum of the numbers of logic resources of all FPGA dies.
Firstly, cutting a user input netlist according to the number of logic resources contained in each FPGA bare chip, cutting the user input netlist into a plurality of sub netlists, wherein the sub netlists correspond to the FPGA bare chips one to one, and the number of the logic resources on each FPGA bare chip meets the logic resource requirements of the corresponding sub netlists, so that each FPGA bare chip can have enough resource layout. The cut sub netlists have connection relations, and each sub netlist is connected with one or more other sub netlists, and one or more groups of preset connection relations are included between every two sub netlists.
2. And arranging the IO ports on the FPGA bare chips at initial positions according to the sub netlist corresponding to each FPGA bare chip. For each FPGA die, the method for arranging the initial positions of the IO ports according to the sub netlist includes but is not limited to the following methods:
(1) and randomly arranging at least one IO port on the FPGA bare chip at an initial position by using an IO EDITOR software tool.
(2) And arranging at least one IO port on the FPGA bare chip in an arbitrary sequence at an initial position manually by using an IO EDITOR software tool.
(3) And randomly arranging at least one IO port on the FPGA bare chip at an initial position according to an IO automatic arrangement algorithm.
3. In a designed multi-die structure FPGA, two FPGA dies have a certain physical connection relationship, which is specifically represented as follows: the connection point leading-out terminals 2 in the two FPGA bare chips are connected through a cross-bare chip connecting wire 3, and the connection point leading-out terminals are connected in a signal path inside the FPGA bare chips, namely the connection point leading-out terminals are connected with the logic unit layout position inside the FPGA bare chips. Therefore, a logic unit layout position a, a connection point leading-out end a, a cross-die connection line, a connection point leading-out end b and a logic unit layout position b form a connection path, wherein the logic unit layout position a and the connection point leading-out end a are arranged on one FPGA die, and the connection point leading-out end b and the logic unit layout position b are arranged on the other FPGA die. On the other hand, signal connection relations also exist between the sub netlists corresponding to the two FPGA dies, when the FPGA with the multi-die structure is laid out, the signal connection relations between the sub netlists corresponding to the FPGA dies need to be considered and formed, and the essence is that the signal connection relations between the FPGA dies need to be formed by using connection paths between the FPGA dies.
Therefore, according to the method and the device, mutual traction points are respectively selected on the two FPGA bare chips according to the connection relation between the two sub-netlists corresponding to the two FPGA bare chips and the connection path formed by the silicon connection layer between the two FPGA bare chips, and initial layout is carried out on the FPGA bare chips by utilizing the force-oriented layout algorithm model based on the IO ports at the initial positions on the FPGA bare chips and the traction action of the mutual traction points according to the sub-netlists corresponding to the FPGA bare chips.
The method for layout by using the force-oriented layout algorithm model comprises the following specific steps: regarding the layout positions of the logic units in the sub netlist as nodes, establishing a signal relationship between the nodes into a point-to-point edge relationship, and establishing a force-directed layout algorithm model according to the sub netlist; solving a force guidance layout algorithm model under the traction action of an IO port to obtain the position of each node in a force balance state; breaking the force balance state under the traction action of the mutual traction points, and solving the force-oriented layout algorithm model again to obtain an initial layout structure; and uniformly spreading the initial layout structure until iteration reaches an iteration termination condition, and finishing the initial layout.
4. And after the initial layout is finished, the IO ports at the initial positions on all the FPGA bare chips are released from being laid out to be in an undistributed state, the mutual traction points are used as fixed points, the FPGA bare chips are re-laid out by utilizing the force-guided layout algorithm model, and the layout positions of the IO ports on the FPGA bare chips are re-determined according to the re-laid structure. The method for re-determining the layout position of the IO port comprises the following steps: and arranging the IO ports on the FPGA bare chip at the position with the shortest connecting line of the sub netlist corresponding to the FPGA bare chip according to the structure of the re-layout of the FPGA bare chip to obtain the layout position of the IO ports on the FPGA bare chip.
It should be noted that, in the present application, an initial position of an IO port is given, then the layout of the IO port is released, and then the layout position of the IO port is determined again, but in actual operation, even if there is no initial position of the IO port, the method can be implemented, but for an FPGA, the IO port is an interaction point between the FPGA and the outside, and is an important design point, and the initial position of the IO port directly affects the final result quality, and if there is no initial position of the IO port, the final layout effect may be poor, so the present application first gives the initial position of the IO port, and then iterates step by step until a better solution is reached, and a better layout effect is achieved.
When the initial layout is performed on the multi-die structure FPGA in step 3, there are various initial layout modes, mainly the following three types:
firstly, selecting mutual traction points on all FPGA dies and then initially laying out, specifically:
(1) and for any group of preset connection relations between the two sub netlists corresponding to the two FPGA bare chips, selecting logic unit layout positions connected through the silicon connection layer on the two FPGA bare chips respectively as connection points to form a group of connection points for forming the preset connection relations.
For any mth FPGA bare chip and nth FPGA bare chip, after the logic unit layout position is selected as the mth connection point on one mth FPGA bare chip, because the mth connection point and one logic unit layout position on the nth FPGA bare chip have fixed connection positions through the silicon connection layer, the logic unit layout position connected with the mth connection point on the other nth FPGA bare chip through the silicon connection layer is correspondingly determined to be the nth connection point on the nth FPGA bare chip, and the mth connection point and the nth connection point form a preset connection relation.
In selecting the connection points, the connection points are typically selected on the FPGA die by manual assignment assisted by software tools, and the selection logic includes, but is not limited to, random selection or according to a predetermined selection order. Wherein, the preset selection sequence is as follows: taking a predetermined position on the FPGA bare chip as a starting point, and sequentially arranging the FPGA bare chip in a determinant structure along the transverse direction and the longitudinal direction of the FPGA bare chip; or, taking a predetermined position on the FPGA bare chip as a starting point, and sequentially arranging the S-shaped structures along the transverse direction and the longitudinal direction of the FPGA bare chip; or, starting from a predetermined position on the FPGA die, the order of the ring structures from outside to inside or from inside to outside along the clockwise or counterclockwise direction.
(2) And respectively selecting connection point leading-out ends on the two FPGA bare chips according to the group of connection points and adding virtual stress points to form a group of virtual stress points. For a set of connection points formed by the mth connection point on the mth FPGA die and the nth connection point on the nth FPGA die, a set of virtual stress points is added to the set of connection points, as shown in fig. 5: an mth virtual stress point (m 'in the figure) corresponding to the mth connection point is added at the connection point leading-out end closest to the mth connection point (m in the figure) on the mth FPGA die, an nth virtual stress point (n' in the figure) corresponding to the nth connection point (n in the figure) is added at the connection point leading-out end closest to the mth virtual stress point on the nth FPGA die, and the mth virtual stress point and the nth virtual stress point form a group of virtual stress points.
(3) And initially arranging the FPGA bare chips by utilizing a force guiding arrangement algorithm model based on the IO port on each FPGA bare chip and the traction action of the virtual stress point on the FPGA bare chips on the corresponding connection point according to the sub netlist corresponding to each FPGA bare chip.
Secondly, selecting mutual traction points according to the FPGA dies which are already laid out on the FPGA dies which are not already laid out, and then initially laying out, specifically:
and for the first FPGA bare chip, performing initial layout on the first FPGA bare chip based on an IO port on the first FPGA bare chip by using a force-oriented layout algorithm model according to a sub netlist corresponding to the first FPGA bare chip, wherein logic units with connection relations between the sub netlists corresponding to other FPGA bare chips on the first FPGA bare chip are arranged at a preferred position and form a connection point on the first FPGA bare chip. The arrangement logic may be arranged randomly or according to a predetermined order, and the definition of the predetermined order may refer to step (1) in the first case, which is not described in detail herein.
For the (i + 1) th FPGA bare chip, determining the layout position of a logic unit connected with the connection point on the (i) th FPGA bare chip through a silicon connection layer on the (i + 1) th FPGA bare chip as the connection point connected with the (i) th FPGA bare chip which is already laid out on the (i + 1) th FPGA bare chip, selecting a connection point leading-out end which is closest to the (q) th connection point on the (i + 1) th FPGA bare chip according to the (q) th connection point connected with the (p) th connection point on the (i + 1) th FPGA bare chip and adding a virtual stress point corresponding to the (p) th connection point to the (i + 1) th FPGA bare chip according to a sub-netlist corresponding to the (i + 1) th FPGA bare chip, and initially laying out the (i + 1) th FPGA bare chip on the basis of the traction action of the virtual stress point on the corresponding connection point and the traction action of an IO port by using a stress-oriented layout algorithm model, wherein the initial value of the i is 1. The adding manner of the virtual stress point may refer to step (2) in the first case, and is not described in detail in this application. And when the (i + 1) th FPGA bare chip is laid out, the connection points connected with the sub netlists corresponding to the subsequent FPGA bare chips on the (i + 1) th FPGA bare chip are arranged at the optimal positions, and the subsequent FPGA bare chips comprise the (i + 2) th FPGA bare chip to the Nth FPGA bare chip which are not laid out.
In this application, the first FPGA die may be any one of the FPGAs in the multi-die structure, and for the ith FPGA die that has been laid out, the (i + 1) th FPGA die corresponding to the first FPGA die may be a die closest to the ith FPGA die in the layout position, and it is common to take the (i + 1) th FPGA die as a die adjacent to the ith FPGA die. Or, the common i +1 th FPGA die is the one FPGA die which corresponds to the sub netlist having the most connection relation with the sub netlist corresponding to the i FPGA die and which is not laid out yet. Of course, the (i + 1) th FPGA die may also be a randomly selected one, which is not limited in this application.
Thirdly, selecting mutual traction points on all FPGA dies according to the time sequence of the preset connection relation among the FPGA dies and then initially laying out, specifically:
(1) and determining a timing key index of the predetermined connection relation for any group of predetermined connection relations between two sub netlists corresponding to the two FPGA bare chips, wherein the longer the time delay of the predetermined connection relation is, the higher the corresponding timing key index is.
The time sequence key index of the predetermined connection relationship can be determined in a time sequence analysis mode, specifically: and determining the time allowance of each group of preset connection relations through a static time sequence analysis STA based on the time sequence constraint condition, wherein the longer the time delay of the preset connection relations is, the smaller the corresponding time allowance is, determining the corresponding key index according to the time allowance of each group of preset connection relations, and the smaller the time allowance of the preset connection relations is, the higher the corresponding time sequence key index is.
(2) And determining the link time delay of each connection path formed by the layout positions of the logic units connected through the silicon connection layers in the two FPGA bare chips. Each connection path may have a different routing distance, or different devices may be disposed on the path, so that each connection path has a different link delay, which may be determined by a timing analysis method, and is not described in detail herein.
(3) And respectively selecting the layout positions of the logic units connected through the silicon connection layer on the two FPGA bare chips as connection points to form a group of connection points for forming the predetermined connection relation according to the time sequence key index of the predetermined connection relation and the link time delay of each connection path between the two FPGA bare chips. The link time delay of a connection path between a group of connection points corresponds to the time sequence key index of the predetermined connection relationship, and the higher the time sequence key index of the predetermined connection relationship is, the shorter the link time delay of the corresponding connection path is.
When the logic unit layout positions are respectively selected on the two FPGA bare chips to form a group of connection points, one logic unit layout position is actually selected on one FPGA bare chip to form one connection point, and the logic unit layout position has a fixed connection relation with one logic unit layout position on the other corresponding FPGA bare chip, so that the other corresponding connection point on the other FPGA bare chip can be determined immediately. The logic selected when the layout position of the logic unit is selected as the connection point on one of the FPGA dies may refer to the logic (1) in the first case, and details of this application are omitted.
(4) And (3) selecting connection point leading-out ends on the two FPGA bare chips respectively according to the group of connection points to add virtual stress points to form a group of virtual stress points, wherein the adding mode of the virtual stress points can refer to the step (2) in the first case, and the description is omitted in the application.
(5) And initially arranging the FPGA bare chips by utilizing a force guiding arrangement algorithm model based on the IO port on each FPGA bare chip and the traction action of the virtual stress point on the FPGA bare chips on the corresponding connection point according to the sub netlist corresponding to each FPGA bare chip.
No matter what kind of initial layout method is adopted, the method adopts the quadratic algorithm when the initial layout and the IO port are released from being laid out again, and the principle of the quadratic algorithm is introduced as follows:
(a) and (4) building a Quadratic netlist model.
In the placement netlist, all logic cell placement positions can be regarded as nodes, and the signal relationship among all nodes is established as a point-to-point edge relationship. As shown in FIG. 6, there are 5 nodes in the netlist, namely A, B, C, D, E, and signal 1 is output from node A to 4 destinations on node B, C, D, E. During modeling, signal 1 is converted into edge 1, edge 2, edge 3 and edge 4 in the graph, and a point- > edge- > point model is formed. Thus, when the layout is based on the wire length as the constraint condition, the shortest wire length from the source end a to the destination end B, C, D, E of the signal 1 can be equivalently regarded as the shortest sum of the side lengths of the side 1, the side 2, the side 3 and the side 4. Then the layout optimization goal is to minimize the sum of the lengths of all edges in the netlist for the entire netlist.
As shown in FIG. 6, assume node A (x)1,y1)，B(x2,y2) If the sizes of the nodes A and B are ignored, and the weight of the edge 1 is assumed to be 1, the length of the edge 1 is
Figure GDA0003361105050000111
Length of side 1The expression (c) can know that the length of the edge 1 is positively correlated with the expression (x)2-x1)2+(y2-y1)2I.e. length is in (x)2-x1)2+(y2-y1)2Taking the minimum value is to obtain the minimum value.
(b) And constructing a solving matrix.
For the entire netlist, assuming n nodes, the optimization objective function can be equivalent to:
Figure GDA0003361105050000112
from the quadratic property of the objective function, the minimum value is obtained when its partial derivative is 0, i.e.:
Figure GDA0003361105050000113
in the form of written matrix equations AX ═ B and AY ═ B. To illustrate, as shown in FIG. 7, assuming A, B, E, F are 4 fixed points in the netlist, wherein the X coordinates of A, B are all 10, the X coordinates of E, F are all 40, and C, D is the layout target point, the positions need to be determined so that the line length of the whole netlist is minimal. The objective function in the X-direction can be established as:
φ＝(xc-10)2+2(xc-10)2+(xd-xc)2+(xd-40)2+2(xd-40)2
for the target function respectively at xc、xdThe partial derivative is obtained by the above calculation:
Figure GDA0003361105050000114
Figure GDA0003361105050000121
obtaining a minimum value from its partial derivative as 0 to obtain a matrix equation
Figure GDA0003361105050000122
Solved and obtained xc＝16,xdIn this case, the net length is set to 34, i.e., the minimum value. The x-seat of the node C can be determined during layoutThe X coordinate of node D is denoted as 16 and the Y coordinate solves for the similar X direction.
Also in the above example, solving for the X coordinate of node C to be 16 and the X coordinate of D to be 34, then, as seen from node C, the fixed point A, B can be considered to produce a leftward pulling force on C in the X direction. The movable point D pair C can be considered to generate a rightward pulling force in the X direction, and the magnitude is as follows: forceright＝wcd(xd-xc) 1 (34-16) ═ 18. It can be seen that point C is in a force balance state in the X direction, and similarly, D is also in a force balance state. After the netlist structure is built by the force model, when the position of the movable point is changed in the layout, the target node can be added with a fixed force according to the force balance model.
(c) A method for spreading a congested area.
The logic unit positions obtained by the method for obtaining the extreme value according to the partial derivative of the quadratic function have logic unit overlapping to a large extent, and the premise condition of legal layout is that the logic units cannot be overlapped. Therefore, the solved result needs to be expanded, so that the continuous overlapping is reduced.
As shown in fig. 8, there are 1, 2, 3, 4, 5 nodes in the 5 blocks from left to right in sequence, and it is assumed that the maximum capacity of each block in the figure is 3 nodes. The dotted line in the figure is used as a cutting line, and if the number of nodes in unit squares on the left and right sides of the cutting line is the same, a plurality of nodes need to be moved from the left side to the right side of the cutting line or from the right side to the left side of the cutting line. Assuming that the movement from the left to the right of the cut line is positive, how the equation can be established:
Figure GDA0003361105050000123
wherein L isnRepresenting the number of nodes to the left of the cutting line, RnRepresenting the number of nodes to the right of the cutting line, LcRepresenting the sum of the volumes of the squares to the left of the cutting line, RcRepresents the sum of the volumes of the squares to the right of the cut line and P represents the number of nodes that need to be moved to the right. Can be derived from the equation
Figure GDA0003361105050000124
Namely, it is
Figure GDA0003361105050000125
Wherein T iscRepresenting the sum of the capacities of all the squares.
Assuming that the capacity of a square is proportional to the length of the square, we can convert the movement of the node into the movement of the square edge where the cutting line is located, as shown in fig. 8. Assuming that the right movement is positive, the movement of the square edge on which the cutting line is located
Figure GDA0003361105050000126
Where P is the number of nodes that need to be moved to the right, WbIs the width of a single square grid, CbThe capacity of a single square. Assuming the width of the square is 1, then
Figure GDA0003361105050000127
Figure GDA0003361105050000128
According to the solution result, the square edge where the cutting line is located needs to be moved to the left
Figure GDA0003361105050000129
Distance.
In calculating XmThen, the squares representing the left and right sides of the cut line need to be compressed or expanded by a distance XmAnd equivalently, the nodes on the left side and the right side of the cutting line stretch respectively according to the frame. That is, the equation may hold for the node to the left of the cut line:
Figure GDA0003361105050000131
the node to the right of the cut line may be formed as an equation
Figure GDA0003361105050000132
Where min represents the x coordinate of the left boundary of the full row of tiles, max represents the x coordinate of the right boundary of the full row of tiles, LlRepresenting a cutting lineSum of lengths of squares on the left, LrRepresenting the sum of the lengths of the squares to the right of the cutting line, xoriRepresenting the original x-coordinate value, x, of the nodenewRepresenting the new coordinates of the required nodes. Through the above equation, the target position of the node can be obtained, and if the positive direction is represented by the rightward direction, it can be obtained that the node needs to move the distance x rightwardnew-xori。
By the method, the cutting line is sequentially moved to the right by one square grid, and the new positions of all the nodes based on node density balance can be obtained by recalculation. After a plurality of iterations, the nodes in the target range can be pulled more uniformly. According to the force model described above, if a node needs to be moved a certain distance in the netlist, how to equivalently think that a force is applied in the moving direction to bring the node to a new equilibrium state. As shown in fig. 9, point D is originally in a force equilibrium state of a, B, and C, and it is now necessary to move D to the position of D ', a fixed point E may be added to the right of point D to generate a force pulling D toward D ', i.e., a pulling force of f ═ D ' -D |. At point E, the weight of the force added can be considered to be
Figure GDA0003361105050000133
Wherein w represents the weight of the link between D, E, LdeRepresenting D, E distance in the X direction.
Based on the layout method, in the example shown in fig. 5, when the mth FPGA die layout is solved, the mth virtual stress point pulls the mth connection point to approach to the mth virtual stress point, and when the nth FPGA die layout is solved, the nth virtual stress point pulls the nth connection point to approach to the nth virtual stress point. Therefore, when the multiple bare chips are separately arranged, the points with the connection relation among the bare chips can be pulled close to one direction, and the purpose of optimizing the connection relation among the bare chips is achieved.
Therefore, the layout method for the multi-die FPGA provided in the present application has been described above, and in order to make the skilled person have a clearer understanding of the physical connection relationship between the PFGA dies and thus better understand the layout method of the present application, the present application describes a structure of the multi-die FPGA in detail as follows, please refer to fig. 10, where the multi-die FPGA includes, in addition to the silicon connection layer 1 and the plurality of dies, a substrate 4 disposed below the silicon connection layer 1, and actually further includes a package housing packaged outside the substrate 4, the silicon connection layer 1 and the FPGA dies for protecting each component, and further includes pins and the like connected to the substrate for signal extraction.
Each FPGA bare chip is provided with a connection point leading-out end 2, the interior of each FPGA bare chip also comprises a logic unit, and the connection point leading-out end 2 is connected with the logic unit in the FPGA bare chip through a top layer metal wire in a redistribution layer (RDL layer). In practical application, the logic unit in the FPGA die includes a conventional logic unit and a silicon stacking connection point 5, the conventional logic unit is a CLB, a PLBs, an IOB, a BRAM, a DSP, a PC, etc., and the silicon stacking connection point is a special logic unit designed specifically inside the die for meeting the signal interconnection requirement between the dies. All logic cells have an interconnection resource distributed around the logic cells, and the logic cells are connected via the interconnection resource such that the silicon stack connection point 5 is connected to other conventional logic cells. And the silicon stack connection point is connected with the connection point leading-out terminal 2 through a top layer metal wire in the RDL layer.
The micro-convex ball grows on the FPGA bare chip, the connection point leading-out end 2 is connected with the silicon connection layer 1 through the micro-convex ball and is connected to other FPGA bare chips through a cross bare chip connection wire 3 inside the silicon connection layer 1, and the micro-convex ball structure at the bottom of the FPGA bare chip can be seen in figure 10. Micro convex balls grow on one side of the silicon connecting layer 1, which is far away from the FPGA bare chip, and the silicon connecting layer 1 is connected with the substrate 4 through the micro convex balls. In addition, a through silicon via 6 is further formed in the silicon connection layer 1, and the IOB on the FPGA bare chip is connected to the substrate 1 through the through silicon via 6 on the silicon connection layer 1 so as to finally lead out a signal.
The above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiments. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.

Claims (10)

1. A layout method of an FPGA with an IO automatic allocation multi-die structure comprises a silicon connection layer and a plurality of FPGA dies stacked on the silicon connection layer, wherein each FPGA die is provided with a plurality of connection point leading-out ends connected with internal signal paths of the FPGA dies, and the connection point leading-out end in each FPGA die is connected with the connection point leading-out end of any other FPGA die through a cross-die connection line in the silicon connection layer to realize interconnection among the FPGA dies, and the method comprises the following steps:
the method comprises the steps of obtaining a user input netlist, cutting the user input netlist into a plurality of connected sub netlists according to the number of logic resources contained in each FPGA bare chip, wherein the sub netlists are in one-to-one correspondence with the FPGA bare chips, and the number of the logic resources on each FPGA bare chip meets the logic resource requirements of the corresponding sub netlists;
arranging IO ports on the FPGA bare chips at initial positions according to the sub netlist corresponding to each FPGA bare chip;
selecting mutual traction points on the two FPGA bare chips according to the connection relation between the two sub netlists corresponding to the two FPGA bare chips and a connection path formed by the silicon connection layer between the FPGA bare chips, and performing initial layout on the FPGA bare chips by utilizing a force-oriented layout algorithm model based on the IO port on each FPGA bare chip and the traction action of the mutual traction points according to the sub netlist corresponding to each FPGA bare chip; the method comprises the following steps: for any group of preset connection relations between two sub netlists corresponding to two FPGA bare chips, randomly selecting or selecting a logic unit layout position on one mth FPGA bare chip as an mth connection point according to a preset selection sequence, determining a logic unit layout position on the other nth FPGA bare chip connected with the mth connection point through the silicon connection layer as an nth connection point on the nth FPGA bare chip, forming the preset connection relation by the mth connection point and the nth connection point, and respectively selecting connection point leading-out ends on the two FPGA bare chips according to a group of connection points and adding virtual stress points to form a group of virtual stress points; according to the sub-netlist corresponding to each FPGA bare chip, performing initial layout on the FPGA bare chip by utilizing a force-oriented layout algorithm model based on an IO port on each FPGA bare chip and the traction action of a virtual stress point on the FPGA bare chip on a corresponding connection point;
and the IO ports at the initial positions on all the FPGA bare chips are released from being laid out to be in an undisposed state, the FPGA bare chips are re-laid by utilizing a force-oriented layout algorithm model, and the layout positions of the IO ports on the FPGA bare chips are determined according to the re-laid structure.
2. The method of claim 1, wherein determining the layout position of the IO port on the FPGA die according to the re-laid out structure comprises:
and arranging the IO ports on the FPGA bare chip at the position where the connection line of the sub netlist corresponding to the FPGA bare chip is shortest according to the re-arranged structure of the FPGA bare chip to obtain the arrangement position of the IO ports on the FPGA bare chip.
3. The method of claim 1, wherein the arranging the IO ports on the FPGA die in an initial position comprises:
randomly arranging at least one IO port on the FPGA bare chip at an initial position by using an IO EDITOR software tool;
or manually arranging at least one IO port on the FPGA bare chip at an initial position according to any sequence by using an IO EDITOR software tool;
or randomly arranging at least one IO port on the FPGA bare chip at an initial position according to an IO automatic arrangement algorithm.
4. The method according to claim 1, wherein the predetermined picking order is: taking a predetermined position on the FPGA bare chip as a starting point, and sequentially arranging the FPGA bare chip in a determinant structure along the transverse direction and the longitudinal direction of the FPGA bare chip; or, taking a predetermined position on the FPGA bare chip as a starting point, and sequentially arranging the S-shaped structures along the transverse direction and the longitudinal direction of the FPGA bare chip; or, starting from a predetermined position on the FPGA die, the order of the ring structures from outside to inside or from inside to outside along the clockwise or counterclockwise direction.
5. The method of claim 1, wherein mutual pulling points are respectively selected on the two FPGA dies according to the connection relationship between the two sub netlists corresponding to the two FPGA dies and the connection paths formed by the silicon connection layers between the FPGA dies, and the FPGA dies are initially laid out by using a force-oriented layout algorithm model according to the sub netlist corresponding to each FPGA die based on the pulling action of the IO port and the mutual pulling points on each FPGA die, and the method comprises the following steps:
determining a time sequence key index of a preset connection relation for any group of preset connection relations between two sub netlists corresponding to two FPGA bare chips, wherein the longer the time delay of the preset connection relation is, the higher the corresponding time sequence key index is;
determining link time delay of each connection path formed by logic unit layout positions connected through the silicon connection layer in the two FPGA bare chips;
selecting logic unit layout positions connected through the silicon connection layer on the two FPGA bare chips respectively as connection points to form a group of connection points for forming the preset connection relation according to the time sequence key index of the preset connection relation and the link time delay of each connection path between the two FPGA bare chips; the link time delay of the connection path between the group of connection points corresponds to the time sequence key index of the preset connection relation, and the higher the time sequence key index of the preset connection relation is, the shorter the link time delay of the corresponding connection path is;
respectively selecting connection point leading-out ends on the two FPGA bare chips according to the group of connection points and adding virtual stress points to form a group of virtual stress points;
and according to the sub netlist corresponding to each FPGA bare chip, performing initial layout on the FPGA bare chips by utilizing a force guide layout algorithm model based on the IO port on each FPGA bare chip and the traction action of the virtual stress point on each FPGA bare chip on the corresponding connection point.
6. The method of any one of claims 1-5, wherein adding virtual stress points to selected contact point outlets on two FPGA dies according to the set of contact points to form a set of virtual stress points comprises:
for a group of connection points formed by an mth connection point on an mth FPGA die and an nth connection point on an nth FPGA die, adding an mth virtual stress point corresponding to the mth connection point at a connection point leading-out end closest to the mth connection point on the mth FPGA die, adding an nth virtual stress point corresponding to the nth connection point at a connection point leading-out end closest to the mth virtual stress point on the nth FPGA die, and forming a group of virtual stress points by the mth virtual stress point and the nth virtual stress point.
7. The method of claim 1, wherein mutual pulling points are respectively selected on the two FPGA dies according to the connection relationship between the two sub netlists corresponding to the two FPGA dies and the connection paths formed by the silicon connection layers between the FPGA dies, and the FPGA dies are initially laid out by using a force-oriented layout algorithm model according to the sub netlist corresponding to each FPGA die based on the pulling action of the IO port and the mutual pulling points on each FPGA die, and the method comprises the following steps:
for a first FPGA bare chip, initially laying out the first FPGA bare chip on the basis of an IO port on the first FPGA bare chip by utilizing a force-guided layout algorithm model according to a sub netlist corresponding to the first FPGA bare chip, wherein logic units with connection relations between the sub netlists corresponding to other FPGA bare chips on the first FPGA bare chip are arranged at a preferred position and form a connection point on the first FPGA bare chip;
for the (i + 1) th FPGA bare chip, determining the layout position of the logic unit on the (i + 1) th FPGA bare chip connected with the connection point on the first i FPGA bare chips through the silicon connection layer as the connection point of the (i + 1) th FPGA bare chip connected with the first i FPGA bare chips, for any p-th connection point, selecting a connection point leading-out end closest to the q-th connection point on the (i + 1) -th FPGA die according to the q-th connection point connected with the p-th connection point on the rest FPGA dies, adding a virtual stress point corresponding to the p-th connection point, and initially arranging the (i + 1) th FPGA bare chip by utilizing a force-guided layout algorithm model according to the sub netlist corresponding to the (i + 1) th FPGA bare chip based on the traction action of the virtual force application point on the (i + 1) th FPGA bare chip on the corresponding connection point and the traction action of the IO port, wherein the starting value of i is 1.
8. The method of claim 7, wherein the (i + 1) th FPGA die is an FPGA die adjacent to the (i) th FPGA die.
9. The method according to claim 7, wherein the i +1 th FPGA die is the FPGA die corresponding to the sub-netlist having the most connection relation with the sub-netlist corresponding to the i-th FPGA die.
10. The method of claim 1, wherein the initial placement of the FPGA dies according to the corresponding sub-netlist of each FPGA die using a force-directed placement algorithm model based on the pulling action of the IO port and the mutual pulling point on each FPGA die comprises:
regarding the layout positions of the logic units in the sub netlist as nodes, establishing a signal relationship between the nodes into a point-to-point edge relationship, and establishing a force-oriented layout algorithm model according to the sub netlist;
solving the force-oriented layout algorithm model under the traction action of the IO port to obtain the position of each node in a force balance state;
breaking the force balance state under the traction action of the mutual traction points, and solving the force-oriented layout algorithm model again to obtain an initial layout structure;
and uniformly spreading the initial layout structure until iteration reaches an iteration termination condition.
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CN112329367A (en) * 2020-12-02 2021-02-05 国微集团(深圳)有限公司 Logic design cutting method and system based on graph convolution neural network
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102375902A (en) * 2010-08-20 2012-03-14 雅格罗技（北京）科技有限公司 Layout method for heterogeneous field programmable gate array (FPGA)
CN103345458A (en) * 2013-06-24 2013-10-09 北京工业大学 Multi-FPGA interconnection structure and logic partitioning method oriented to high-performance computing
CN106528921A (en) * 2016-09-27 2017-03-22 北京深维科技有限公司 Method for implementing regional constraint in FPGA (Field Programmable Gate Array) chip layout
EP3333735A1 (en) * 2016-12-12 2018-06-13 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Method and computer program for determining a placement of at least one circuit for a reconfigurable logic device
EP3336727A1 (en) * 2016-12-19 2018-06-20 Menta System and method for defining a programmable logic architecture

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8418115B1 (en) * 2010-05-11 2013-04-09 Xilinx, Inc. Routability based placement for multi-die integrated circuits
CN102033987A (en) * 2010-11-30 2011-04-27 中国人民解放军信息工程大学 Method for distributing layout regions for FPGA (Field Programmable Gate Array) meta-components
CN105808795A (en) * 2014-12-29 2016-07-27 京微雅格（北京）科技有限公司 FPGA chip global placement optimization method based on temporal constraint
US10713406B2 (en) * 2015-11-30 2020-07-14 The Regents Of The University Of California Multi-die IC layout methods with awareness of mix and match die integration
CN108287932B (en) * 2017-01-10 2021-09-21 上海复旦微电子集团股份有限公司 Overall FPGA automatic layout method based on analysis method
CN107729704A (en) * 2017-11-27 2018-02-23 中科亿海微电子科技（苏州）有限公司 The method of three-dimensional FPGA device layout optimization based on heat emulation

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102375902A (en) * 2010-08-20 2012-03-14 雅格罗技（北京）科技有限公司 Layout method for heterogeneous field programmable gate array (FPGA)
CN103345458A (en) * 2013-06-24 2013-10-09 北京工业大学 Multi-FPGA interconnection structure and logic partitioning method oriented to high-performance computing
CN106528921A (en) * 2016-09-27 2017-03-22 北京深维科技有限公司 Method for implementing regional constraint in FPGA (Field Programmable Gate Array) chip layout
EP3333735A1 (en) * 2016-12-12 2018-06-13 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Method and computer program for determining a placement of at least one circuit for a reconfigurable logic device
EP3336727A1 (en) * 2016-12-19 2018-06-20 Menta System and method for defining a programmable logic architecture

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
FPGA快速布局布线算法的研究与实现;周文豪;《中国优秀硕士学位论文全文数据库（电子期刊） 信息科技辑》;20141115;全文 *

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