CN116227409A - Layout method and system suitable for multi-core grains on active substrate - Google Patents
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Abstract
The invention relates to a layout method suitable for multi-core grains on an active substrate. Comprising providing an active substrate having a configurable routing network, and n die to be laid out onto the active substrate; and (3) configuring the planned layout positions of the n cores based on a secondary linear programming layout method for the n cores to be laid out and k fixed IO ports distributed on the periphery of the configurable wiring network, and reconfiguring the planned layout positions of the n cores based on a rapid simulated annealing method until a layout target position state is reached. The invention can obtain high-quality core particle layout, reduce the cost of layout and improve the efficiency and reliability of layout.
Description
Technical Field
The present invention relates to a layout method, and more particularly, to a layout method and system for multi-core particles on an active substrate.
Background
As chip fabrication processes approach physical limits, the push to moore's law begins to become increasingly difficult. In recent years, in order to maintain the development speed of the chip, the cost of a single chip is higher and higher, but the obtained economic benefit is lower and lower. In the background of the development of the industry, advanced packaging technology of isomerically integrated 3D chips has become one of the best ways to continue moore's law.
Advanced packaging technology of 3D chips can place core grains with different properties, which are manufactured by different processes, in the same package. Therefore, in packaging, a good core layout can improve the performance of the packaging system and reduce the power consumption, area and cost of the packaging system.
For the layout of multiple die on an active substrate, the layout methods commonly used today include partition-based layout algorithms, as well as heuristic layout algorithms, wherein,
the layout algorithm based on division is that the whole core particle to be laid out is formed into a hypergraph (Hyper-graph), and the layout problem is converted into a minimum segmentation problem (min-cut program) of the hypergraph; the partition-based layout algorithm, although fast, does not have ideal layout results.
For heuristic layout algorithms, genetic algorithms, simulated annealing algorithms, etc. may be included in general, and in particular, optimal solutions are obtained by continually random search and iterative processes. In the solving process, in order to ensure the quality of the optimal solution, a long iterative process is required. As the number of kernels increases, the heuristic algorithm becomes increasingly difficult to adapt.
In summary, it is difficult to meet the layout requirements of the multi-core on the active substrate by the existing layout method.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a layout method and a layout system suitable for multi-core grains on an active substrate, which can obtain high-quality core grain layout, reduce the layout cost and improve the layout efficiency and reliability.
According to the technical scheme provided by the invention, the layout method suitable for the multi-core grains on the active substrate comprises the following steps:
providing an active substrate with a configurable wiring network and n core grains to be laid out on the active substrate, wherein the configurable wiring network comprises a substrate track wire net and a plurality of transposition connecting circuits, wherein the substrate track wire net is prepared on the active substrate, the transposition connecting circuits are used for connecting the core grains into the substrate track wire net, and one core grain is connected with a transposition connecting circuit in an adapting way for a plurality of core grains laid out on the active substrate;
for n cores to be laid out and k fixed IO ports distributed on the periphery of the configurable wiring network, configuring the planned layout positions of the n cores based on a quadratic linear programming layout method, wherein the optimization target of the quadratic linear programming layout method is to minimize the estimated linear programming interconnection net bus length, and the linear programming interconnection net bus length comprises the interconnection net lengths between the cores and the fixed IO ports;
the planned layout positions of n core grains are configured by a secondary linear programming layout method to serve as initial positions, the planned layout positions of n core grains are reconfigured based on a rapid simulated annealing method until a layout target position state is reached, wherein,
when the layout target position state is reached, a core particle is distributed to a target transposition connecting circuit, and the core particle corresponds to the transposition connecting circuit one by one;
when the planned layout positions of the N core grains are reconfigured by adopting the rapid simulated annealing method, the initial positions of the N core grains are subjected to random transformation of N times of positions, and the standard deviation between the lengths of the simulated annealing bus wires obtained by the random transformation of the N times of core grain positions is configured as the initial temperature of the rapid simulated annealing method.
When the positions of n core grains are configured based on the quadratic linear programming layout method, the method comprises the following steps:
establishing a wire mesh coordinate system for a substrate track wire mesh on an active substrate;
randomly initializing the positions of n core particles on a substrate track wire mesh based on the established wire mesh coordinate system;
based on the positions of n core particles on the substrate track wire net after random initialization, calculating the bus length of the linear programming interconnection wire net in the current state;
determining planning initial positions of n core particles on a substrate track wire net based on the calculated linear planning interconnection wire net bus length;
and rationalizing the planning initial positions of the n core grains to obtain the planning layout positions of the n core grains.
The substrate track net comprises a plurality of transverse track lines and longitudinal track lines which are distributed in a staggered way, wherein,
the crossing joint points of the transverse track lines and the longitudinal track lines form network line nodes of a substrate track line network, and each network line node is provided with a crossing signal transmission circuit for configuring a signal transmission direction;
when the wire network coordinate system is established, the crossing signal transmission circuit at the lower left corner of the substrate track wire network is taken as an origin, the horizontal right is taken as the x axis of the wire network coordinate system, the vertical upward is taken as the y axis of the wire network coordinate system, the distance between adjacent transverse track wires is taken as the unit length of the y axis, and the distance between adjacent longitudinal track wires is taken as the unit length of the x axis.
For the length of the linear programming interconnection network bus in the current state, the following steps are:
where f (x, y) is the linear programming interconnect net bus length, (x) i ,y i ) Is the position coordinate of the ith core particle, (x) j ,y j ) Is the position coordinate of the jth core particle, (x' m ,y′ m ) For the position coordinate of the mth fixed IO port, W ij The number of interconnected network wires between the ith core particle and the jth core particle, W im Is the number of interconnected wires between the ith core particle and the mth fixed IO port.
When determining the planning initial positions of n core particles on the substrate track wire net, for minimizing the estimated linear planning interconnection wire net bus length, the following steps are:
wherein ,
to derive the interconnect net bus length f (x, y), Q is the quadratic coefficient matrix obtained by expanding the interconnect net bus length f (x, y), d x 、d y And respectively obtaining a first order coefficient matrix of x and a first order coefficient matrix of y after the lengths f (x, y) of the interconnection network buses are unfolded.
When rationalizing the planning initial positions of n core grains, the method comprises the following steps:
ordering the corresponding x-axis coordinates of the n core particles from small to large, and after ordering, ordering the core particles before
The core grains are placed on the left half of the substrate track net, and the rest core grains are placed on the right half of the substrate track net;
sorting the corresponding y-axis coordinates of the n core particles from small to large, so that after sorting, the first half of the core particles of each half are placed on the upper half of the substrate track net, and the rest are placed on the lower half; until n core particles are all in the effective positions of the substrate track net and are not overlapped with each other.
When the initial temperature of the rapid simulated annealing method is configured, the simulated annealing bus wire length is calculated and determined based on the half perimeter of the smallest rectangle containing the wire mesh.
When the planned layout positions of the n core grains are reconfigured by adopting the rapid simulated annealing method, the method comprises the following steps:
determining a current simulated annealing temperature during rapid simulated annealing, and performing a core particle position adjustment step on the n core particles at the current simulated annealing temperature, wherein,
in each core particle position adjustment step, core particle position adjustment is performed for the same number of times; after each time of core position adjustment, determining cost function increment based on n pieces of core position information, so as to determine a position layout acceptance state after current position adjustment based on the cost function increment;
after the position adjustment step of each core particle is completed, updating the rapid simulated annealing temperature based on the position layout receiving state of each position adjustment until the rapid simulated annealing termination condition is met.
When the length of the simulated annealing bus network line is configured as a cost function, the cost function is:
wherein C is a cost function, (n) 1 ,n 2 ,…n i ,…n z ) For net, for the ith net n i Has n iw The number of vertices of the graph is,
for net n i Is the first vertex coordinate of (a);
delta C=C (S ') -C (S) is added to the cost function C, wherein C (S') is a cost function value based on n core particle position states S 'after position adjustment, C (S) is a cost function value based on n core particle position states S before position adjustment, and the position states S and S' are two position states adjacent to n core particles;
if the cost function increment delta C is less than or equal to 0, the position layout accepting state is configured to accept the new position layout; if ΔC >0, then exp (- ΔC/T) is taken as the probability of accepting the position state S';
if exp (- ΔC/T) is greater than the acceptance probability threshold, the position layout acceptance state is configured to accept as a new position layout.
The acceptance probability threshold is a random number which is randomly generated and is located in a range of 0-1.
When the rapid simulated annealing temperature is updated, the following steps are:
wherein ,Tnew To quickly simulate the annealing temperature after updating, T old For the rapid simulated annealing temperature before the update, α is the rapid simulated annealing temperature T before the update old And then the acceptance rate of the step of adjusting the position of the core particle is adjusted.
For the acceptance rate alpha, the annealing temperature T is rapidly simulated before updating old In the next pellet position adjustment step, the number of accepted pellet position adjustments is divided by the rapid simulated annealing temperature T prior to updating old Total number of adjustments of the lower pellet position.
In each pellet position adjustment step, the pellet position adjustment is performed n times 2 。
The simulated annealing termination condition includes that the updated rapid simulated annealing temperature is not more than one thousandth of the initial temperature.
A layout system suitable for multi-core grains on an active substrate comprises a layout processor, wherein,
and carrying out layout on the active substrate and n core grains to be laid out on the active substrate by a layout processor based on the method until one core grain is distributed to a target transposition connecting circuit.
The invention has the advantages that: when the core particles are laid out on the active substrate, the planned layout positions of the n core particles are firstly configured based on a secondary linear programming layout method, the planned layout positions of the n core particles are configured as initial positions by the secondary linear programming layout method, and the planned layout positions of the n core particles are reconfigured based on a rapid simulated annealing method until a layout target position state is reached, so that high-quality core particle layout can be obtained, the cost of layout is reduced, and the efficiency and reliability of layout are improved.
Drawings
FIG. 1 is a flow chart of one embodiment of the present invention for placing a core particle on an active substrate.
FIG. 2 is a schematic diagram of an embodiment of the invention after random initialization of n kernels.
Fig. 3 is a schematic representation of one embodiment of the planned initial position of n cores of the present invention.
FIG. 4 is a schematic diagram of an embodiment of the present invention for obtaining a planned layout position after rationalizing.
Reference numerals illustrate: 100-fixed IO port, 110-core.
Detailed Description
The invention will be further described with reference to the following specific drawings and examples.
In order to obtain a high quality layout of the die 110, reduce the cost of the layout, and improve the efficiency and reliability of the layout, in one embodiment of the present invention, the layout method for the die 110 on the active substrate includes:
providing an active substrate with a configurable routing network and n core particles 110 to be laid out on the active substrate, wherein the configurable routing network comprises a substrate track wire net prepared on the active substrate and a plurality of transposition connecting circuits for connecting the core particles 110 to the substrate track wire net, and for a plurality of core particles 110 laid out on the active substrate, one core particle 110 is connected with a transposition connecting circuit in an adapting way;
for n cores 110 to be laid out and k fixed IO ports 100 distributed on the periphery of the configurable wiring network, the planned layout positions of the n cores 110 are configured based on a quadratic linear programming layout method, wherein the optimization objective of the quadratic linear programming layout method is to minimize the estimated linear programming interconnection net bus length, and the linear programming interconnection net bus length comprises the interconnection net lengths between the cores 110 and the fixed IO ports 100;
the planned layout positions of the n core grains 110 are configured by the secondary linear programming layout method as initial positions, and the planned layout positions of the n core grains 110 are reconfigured based on the rapid simulated annealing method until reaching a layout target position state, wherein,
when the layout target position state is reached, a core particle 110 is distributed to a target transposition connecting circuit, and the core particle 110 and the transposition connecting circuit are in one-to-one correspondence;
when the planned layout positions of the N core grains 110 are reconfigured by adopting the rapid simulated annealing method, the initial positions of the N core grains 110 are subjected to random transformation of N times of positions, and the standard deviation between the lengths of the simulated annealing bus wires obtained by the random transformation of the positions of the N core grains 110 is configured as the initial temperature of the rapid simulated annealing method.
Specifically, the active substrate and the core 110 may all take the form of a conventional chip, where the active substrate includes at least one configurable routing network thereon, and the core 110 may take the form of a conventional chip. The layout of the plurality of core grains 110 on the active substrate specifically means that the plurality of core grains 110 realize the required connection by using the configurable wiring network on the active substrate, so that the required data interaction between any two core grains 110 can be performed, and the form of the data interaction can be selected according to the actual requirement, so that the actual application scene can be satisfied.
The configurable wiring network on the active substrate may generally include a substrate track network prepared on the active substrate, a channel for data interaction transmission may be formed by using the substrate track network, and the transposed connection circuit is adaptively connected with the substrate track network and can realize the adaptive connection with the core particles 110 after alignment, at this time, the core particles 110 may be connected to the substrate track network through the transposed connection circuit, that is, the data interaction between two corresponding core particles 110 in the connected substrate track network may be realized. The transposed connection circuit generally needs to be in a form adapted to the core particle 110, i.e. can be connected with the core particle 110 in an adapting manner, so that the core particle 110 is connected to the substrate track network, and the transposed connection circuit can be in a conventional form, specifically, can meet the requirement of being connected with the core particle 110 in an adapting manner, and is connected to the substrate track network. Generally, a core 110 is in one-to-one correspondence with a transfer connection, i.e., a core 110 can only be connected to the substrate track net through a transfer connection.
In order to realize data interaction with the outside, k fixed IO ports 100 are further arranged on the active substrate, connection between the substrate track net and the outside can be realized by using the fixed IO ports 100, and the specific conditions of the types and the number k of the fixed IO ports 100 can be selected according to actual needs so as to meet the requirement of data interaction between the configurable wiring network on the active substrate and the outside.
In fig. 2-4, an embodiment of the fixed IO ports 100 is shown, where k is 4, and the fixed IO ports 100 are generally located on the periphery of the substrate track net, and of course, the fixed IO ports 100 may be other numbers, that is, k may also take other values. In addition, the embodiment of 5 core particles 110 is shown, where n is 5, and of course, the core particles 110 may be other numbers. T in fig. 2 to 4 is a transposed connection circuit, and in general, the transposed connection circuit may be distributed in an array.
When the plurality of core grains 110 are laid out, specifically, when the core grains 110 meet the condition of adapting connection with the fixed IO port 100, the core grains 110 are distributed to corresponding transposed connection circuits, and the transposed connection circuit corresponding to the core grains 110 is the target transposed connection circuit. In addition, when laying out a plurality of pellets 110, the state in which any of the pellets 110 is connected with the fixed IO end block 100 in an appropriate manner, and the corresponding connection state between the pellets 110 and other pellets 110 are all known initial conditions.
Fig. 1 shows a flow of the present invention for the layout of the multi-core particles 110, specifically, the positions of n core particles 110 in the substrate track net are configured by adopting a quadratic linear programming layout method, so as to obtain the planned layout positions; when the quadratic linear programming layout method is adopted, the optimization goal is to minimize the estimated linear programming interconnection net bus length, which includes the interconnection net length between the core grains 110 and the fixed IO ports 100.
The process of configuring the planned layout positions of the n core particles 110 using the quadratic linear planning layout method will be described in detail.
In one embodiment of the present invention, when the positions of the n core grains 110 are configured based on the quadratic linear programming layout method, the method includes:
establishing a wire mesh coordinate system for a substrate track wire mesh on an active substrate;
randomly initializing the positions of n core particles 110 on the substrate track wire mesh based on the established wire mesh coordinate system;
based on the positions of n core particles 110 on the substrate track wire net after random initialization, calculating the bus length of the linear programming interconnection wire net in the current state;
determining planning initial positions of n cores 110 on the substrate track wire network based on the calculated linear planning interconnection wire network bus length;
the planned initial positions of the n core particles 110 are rationalized to obtain planned layout positions of the n core particles.
To facilitate determining the position of the core particle 110, a wire mesh coordinate system needs to be established. In fig. 2-4, an embodiment of a substrate track net is shown, specifically:
the substrate track net comprises a plurality of transverse track lines and longitudinal track lines which are distributed in a staggered way, wherein,
the crossing joint points of the transverse track lines and the longitudinal track lines form network line nodes of a substrate track line network, and each network line node is provided with a crossing signal transmission circuit for configuring a signal transmission direction;
when the wire network coordinate system is established, the crossing signal transmission circuit at the lower left corner of the substrate track wire network is taken as an origin, the horizontal right is taken as the x axis of the wire network coordinate system, the vertical upward is taken as the y axis of the wire network coordinate system, the distance between adjacent transverse track wires is taken as the unit length of the y axis, and the distance between adjacent longitudinal track wires is taken as the unit length of the x axis.
In fig. 2 to 4, the transverse track lines are track lines distributed transversely, the longitudinal track lines are track lines distributed longitudinally, the transverse track lines are perpendicular to the longitudinal track lines, the transverse track lines are parallel to each other, and the longitudinal track lines are parallel to each other.
When the longitudinal track lines and the transverse track lines are distributed in a staggered manner, the crossed joint points of one longitudinal track line and one transverse track line after being crossed form network line nodes of the substrate track network. In order to meet the transmission of information, each network line node is provided with a cross signal transmission circuit, the cross signal transmission circuit adopts a configurable switch mode, namely, the cross signal transmission circuit can realize that signals are kept to be transmitted transversely or signals transmitted transversely are changed into longitudinal transmission, or the signals transmitted longitudinally are kept to be transmitted longitudinally or the signals transmitted longitudinally are changed into transverse transmission, and the cross signal transmission circuit configures the signal transmission direction, so that the signals can reach the required positions after being transmitted along the longitudinal track line and/or the transverse track line. Specifically, the information is transmitted in the transverse direction, i.e. in the transverse track line, and the information is transmitted in the longitudinal direction, i.e. in the longitudinal track line.
For the case of the substrate track net, when the net coordinate system is established, the intersection signal transmission circuit at the lower left corner of the substrate track net is taken as an origin, the horizontal right is taken as the x axis of the net coordinate system, the vertical upward is taken as the y axis of the net coordinate system, the distance between adjacent transverse track lines is taken as the unit length of the y axis, and the distance between adjacent longitudinal track lines is taken as the unit length of the x axis. Generally, the distance between adjacent transverse track lines is the same and the distance between adjacent longitudinal track lines is the same.
In fig. 2 to fig. 4, the positions of the 4 fixed IO ports 100 are (4, 0), (8, 0), (0, 8) and (8, 8), respectively, fig. 2 to fig. 4 only show one embodiment of the fixed IO ports 100, the actual position distribution of the fixed IO ports 100 may be selected according to the actual needs, and in fig. 2 to fig. 4, one fixed IO port 100 is connected with a cross signal transmission circuit, so that the adaptive connection between the fixed IO port 100 and the substrate track network can be realized.
After the network coordinate system is established, the n core particles 100 can be placed in the range of the network coordinate system in a random initialization mode, and after random initialization, the coordinate positions of the n core particles 100 in the network coordinate system can be generated or obtained.
Specifically, based on the positions of n core particles 110 on the substrate track wire net after random initialization, calculating the bus length of the linear programming interconnection wire net in the current state;
for the length of the linear programming interconnection network bus in the current state, the following steps are:
where f (x, y) is the linear programming interconnect net bus length, (x) i ,y i ) Is the position coordinate of the ith core particle 110, (x) j ,y j ) Is the position coordinate of the jth core particle 110, (x' m ,y′ m ) For the m-th fixed IO port 100 position coordinates, W ij Is the number of interconnected wires, W, between the ith core particle 110 and the jth core particle 110 im Is the number of interconnected wires between the ith core 110 and the mth fixed IO port 100.
As can be seen from the above description, since the connection state between any core particle 110 and the fixed IO end block 100 and other core particles 110 is the initial condition, the number W of interconnection net wires can be determined ij Number of interconnected net wires W im . In one embodiment of the invention, the number of interconnected network lines W ij For example, if the ith die 110 has two leads with only two pins connected to pins of the jth die 110, the interconnection net number W ij The value is 2.
In one embodiment of the present invention, the planned initial positions of the n cores 110 on the substrate track wire are determined based on the calculated linear planned interconnect wire mesh bus length.
For the above-described linear programming interconnection net bus length f (x, y), it can be translated into:
where X is a column vector in equation 1 consisting of the abscissas of all the core particles 110, and Y is a column vector in equation 1 consisting of the ordinates of all the core particles 110. X is X T Transpose of column vector X, Y T Is the transpose of the column vector Y. Q is a coefficient matrix composed of the quadratic coefficients expanded by the formula 1, and is a real symmetric matrix. d, d x 、d y Respectively a coefficient matrix composed of primary coefficients of x and y of the abscissa after the expansion of the formula 1, d x 、d y Are column vectors, and D is the sum of the constants of equation 1 after expansion.
In one embodiment of the present invention, when determining the planned initial positions of n core particles 110 on the substrate track wire net, for minimizing the estimated linear programming interconnection wire net bus length, there are:
wherein ,
to derive the interconnect net bus length f (x, y), Q is the quadratic coefficient matrix obtained by expanding the interconnect net bus length f (x, y), d x 、d y And respectively obtaining a first order coefficient matrix of x and a first order coefficient matrix of y after the lengths f (x, y) of the interconnection network buses are unfolded.
As can be seen from the above description, since X and Y in the formula 2 are independent of each other, the formula 3 can be obtained by deriving the formula 2, and thus, the position of each core particle 110, i.e., the planned initial positions of the n core particles, can be obtained according to the formula 3. Derivation of interconnect net bus length f (x, y)
When y is constant, i.e. +.>
When Qx+d is obtained x =0; similarly, in->
Qy+d can be obtained y ＝0。
In one embodiment of the present invention, the planned initial positions of the n core grains 110 are rationalized to obtain the planned layout positions of the n core grains.
Specifically, when the planned initial positions of the n core particles 110 are rationalized, the method includes:
the corresponding x-axis coordinates of the n cores 110 are ordered from small to large, after ordering, the front is followed
The individual core particles 110 are placed on the left half of the substrate track wire mesh, and the remaining core particles 110 are placed on the right half of the substrate track wire mesh;
sorting the corresponding y-axis coordinates of the n core particles 110 from small to large, after sorting, placing the first half of the core particles 110 on the upper half of the substrate track net, and placing the rest on the lower half; until all n cores 110 are in active position in the substrate track net and do not overlap each other.
In the case of a specific implementation of the method,
is a rounding operation. After rationalization, a quadratic linear programming layout of the n cores 110 is achieved. The effective position of the substrate track line net is specifically the position where the connection circuit (marked as T) is placed in fig. 2 to 4. Further, for a determined active substrate, the substrate track line net on the active substrate may be determined accordingly, and thus, the left half, right half, upper half, and lower half of the substrate track line net may be determined accordingly.
In one embodiment of the present invention, the reconfiguring the planned layout positions of the n core particles 110 by using the rapid simulated annealing method includes:
determining a current simulated annealing temperature during rapid simulated annealing, and performing a core particle position adjustment step on the n core particles at the current simulated annealing temperature, wherein,
in each core particle position adjustment step, core particle position adjustment is performed for the same number of times; after each time of core position adjustment, determining cost function increment based on n pieces of core position information, so as to determine a position layout acceptance state after current position adjustment based on the cost function increment;
after the position adjustment step of each core particle is completed, updating the rapid simulated annealing temperature based on the position layout receiving state of each position adjustment until the rapid simulated annealing termination condition is met.
From the above description, after the secondary linear programming layout is performed, the planned layout positions of the n core grains 110 need to be reconfigured by using the rapid simulated annealing method, and when the planned layout positions are reconfigured, the initial positions of the rapid simulated annealing method are the planned layout positions obtained by the secondary linear programming layout. Further, configuring an initial temperature of the rapid simulated annealing method based on an initial position of the rapid simulated annealing method, wherein N times of position random transformation are performed on N core grains 110 when the initial temperature of the rapid simulated annealing method is configured; generally, N is 10. The N-time position random transformation may be specifically to exchange the positions of any two core grains 110, or randomly move one core grain 110 to an empty transposed connection circuit, where the empty transposed connection circuit is a transposed connection circuit that is not overlapped with other core grains 110.
The simulated annealing bus wire length is determined based on the half perimeter calculation of the smallest rectangle containing the wire mesh at the time of initial temperature configuration. A net generally refers to a net where the start points of multiple interconnect lines are the same port, the interconnect lines form a net, and the core at which the ports are located is the net end point.
When the rapid simulated annealing is performed, the determined current simulated annealing temperature is the determined initial temperature, namely, when the rapid simulated annealing is performed, the rapid simulated annealing starts from the determined initial temperature; and the initial position of the rapid simulated annealing is the planned layout position of the configuration.
After determining the initial position, in the rapid simulated annealing, the n core grains 110 at the initial position of the rapid simulated annealing need to be subjected to position adjustment, i.e., a plurality of core grain position adjustment steps need to be performed, and each core grain position adjustment step corresponds to a current simulated annealing temperature, i.e., a corresponding core grain position adjustment step is performed at a current simulated annealing temperature. In each of the core position adjustment steps, the same number of core position adjustments are performed, and in one embodiment of the present invention, each of the core position adjustment steps, n 2 Secondary position adjustment.
After each core particle position adjustment, determining a position layout acceptance state through cost function increment; in the process of n 2 After secondary position adjustment, the step of adjusting the position of the core particle is completed, and n can be determined 2 Secondary position adjustment corresponding position layoutAnd (5) receiving the state, and taking the state as a temperature updating condition of the rapid simulated annealing.
From the above description, n is performed for n core particles 110 at each current simulated annealing temperature 2 Secondary position adjustment. In the specific implementation, there are only two cases for each position adjustment: 1) A transposed link circuit that randomly shifts the positions of two cores 110, 2) one core 110 to a null. The details of the vacant transfer connection circuit can be referred to the above description, and will not be repeated here.
For a core position adjustment step, after each core position adjustment, a cost function increment needs to be determined, where the cost function increment is the difference between the cost function values before and after the position adjustment for n cores 110. For the distribution positions of the n core particles 110 on the substrate track line after the position adjustment, determining a position layout receiving state after the current position adjustment based on the cost function increment, for example, after the initial position is obtained from the rapid simulated annealing configuration to perform the first position adjustment, calculating the cost function value after the position adjustment and the cost function value of the initial position, wherein the difference value between the cost function value after the position adjustment and the cost function value of the initial position is the cost function increment; of course, the current simulated annealing temperature at this time is the initial temperature.
Determining whether the position layout of the n core grains 110 after the first position adjustment is accepted based on the cost function increment, and if so, determining that the position layout is suitable for one time, otherwise, determining that the position layout is not suitable for one time; from the above description, it is also necessary to carry out n at the initial temperature 2 -1 shot position adjustment, each shot position adjustment, the case of shot position adjustment and the case of cost function increment are referred to above. The step of adjusting the position of the core in other cases is described with reference to the description herein, and so on, and is not illustrated herein.
In one embodiment of the present invention, when the length of the simulated annealing bus network line is configured as a cost function, the cost function is:
wherein C is a cost function, (n) 1 ,n 2 ,…n i ,…n z ) For net, for the ith net n i Has n iw The number of vertices of the graph is,
for net n i Is the first vertex coordinate of (a);
for the increment of the cost function, Δc=c (S ') -C (S), where C (S') is a cost function value based on n core position states S 'after position adjustment, C (S) is a cost function value based on n core position states S before position adjustment, and the position states S and S' are two position states adjacent to n cores 110;
if the cost function increment delta C is less than or equal to 0, the position layout accepting state is configured to accept the new position layout; if ΔC >0, then exp (- ΔC/T) is taken as the probability of accepting the position state S';
if exp (- ΔC/T) is greater than the acceptance probability threshold, the position layout acceptance state is configured to accept as a new position layout.
Specifically, the acceptance probability threshold is a random number which is randomly generated and is located in a range of 0 to 1. The position states S and S' are two adjacent position states of the n core particles 110, specifically, two position states at the initial temperature and the first position adjustment, or the position states after the first position adjustment and the second position adjustment, and the rest are not illustrated herein.
For wire meshes, reference is made to the above description. When the positions of the core particles 110 on the substrate track wire mesh are determined, the number of wire meshes and the vertex coordinates of each wire mesh can be determined, and then the cost function C and the cost function increment Δc can be determined according to the above formula. In the above formula, (x) ni1 ,y ni1 ) For net n i The remaining vertex coordinates may refer to the first vertexThe description of the coordinates of the points is not repeated here.
In one embodiment of the present invention, when the rapid simulated annealing temperature is updated, there are:
wherein ,Tnew To quickly simulate the annealing temperature after updating, T old For the rapid simulated annealing temperature before the update, α is the rapid simulated annealing temperature T before the update old And then the acceptance rate of the step of adjusting the position of the core particle is adjusted.
Specifically, the acceptance rate α is a rapid simulated annealing temperature T prior to updating old In the next pellet position adjustment step, the number of accepted pellet position adjustments is divided by the rapid simulated annealing temperature T prior to updating old Total number of adjustments of the lower pellet position.
As can be seen from the above description, in a core position adjustment step, n is required 2 The sub-core 110 position adjustment, the position layout acceptance state of each core position adjustment is either accepted as a new position layout or not accepted as a new position layout, and therefore, the rapid simulated annealing temperature T before updating old When n is performed 2 Secondary position adjustment, at said n 2 In the sub-position adjustment, if n 'times of position adjustment are accepted as a new position layout, the acceptance rate α=n'/n 2 。
In one embodiment of the present invention, the simulated annealing termination condition includes the updated rapid simulated annealing temperature not being greater than one thousandth of the initial temperature. When the simulated annealing termination condition is satisfied, that is, when the layout target position state is reached, there are: a core 110 is allocated to a transposed connection of a target, and the core 110 and the transposed connection are in one-to-one correspondence. Of course, the simulated annealing termination condition may also be other conditions, and may be specifically selected as required, so as to achieve the desired rapid simulated annealing.
As can be seen from the above description, the number of iterations is smaller and the running time is faster when the positions of the n cores 110 are reconfigured by the rapid simulated annealing method. Compared with a layout algorithm based on analysis, the method provided by the invention has the advantages that the planning layout position obtained based on the secondary linear planning layout method is rapidly optimized by adding the rapid simulated annealing step, so that a higher-quality result can be obtained, and the position constraint condition of the chip on the active substrate can be met. The position constraint is the effective position mentioned above, that is, the position where the transposed connection circuit shown in fig. 2-4 is located.
In summary, a layout system suitable for multi-die on an active substrate is provided, which in one embodiment of the invention includes a layout processor, wherein,
for the active substrate and n die 110 to be laid out onto the active substrate, the layout processor lays out based on the method described above until a die 110 is assigned to a target transposed connection circuit.
In specific implementation, the layout processor can adopt the existing common computer equipment, and the type of the layout processor can be selected according to actual needs so as to meet the required layout processing. The layout processor can implement the layout of the n die 110 on the active substrate, and the specific layout method and process are referred to above and will not be described herein.
Claims (15)
1. A layout method for multi-core particles on an active substrate, the layout method comprising:
providing an active substrate with a configurable wiring network and n core grains to be laid out on the active substrate, wherein the configurable wiring network comprises a substrate track wire net and a plurality of transposition connecting circuits, wherein the substrate track wire net is prepared on the active substrate, the transposition connecting circuits are used for connecting the core grains into the substrate track wire net, and one core grain is connected with a transposition connecting circuit in an adapting way for a plurality of core grains laid out on the active substrate;
for n cores to be laid out and k fixed IO ports distributed on the periphery of the configurable wiring network, configuring the planned layout positions of the n cores based on a quadratic linear programming layout method, wherein the optimization target of the quadratic linear programming layout method is to minimize the estimated linear programming interconnection net bus length, and the linear programming interconnection net bus length comprises the interconnection net lengths between the cores and the fixed IO ports;
the planned layout positions of n core grains are configured by a secondary linear programming layout method to serve as initial positions, the planned layout positions of n core grains are reconfigured based on a rapid simulated annealing method until a layout target position state is reached, wherein,
when the layout target position state is reached, a core particle is distributed to a target transposition connecting circuit, and the core particle corresponds to the transposition connecting circuit one by one;
when the planned layout positions of the N core grains are reconfigured by adopting the rapid simulated annealing method, the initial positions of the N core grains are subjected to random transformation of N times of positions, and the standard deviation between the lengths of the simulated annealing bus wires obtained by the random transformation of the N times of core grain positions is configured as the initial temperature of the rapid simulated annealing method.
2. The layout method for multi-core particles on an active substrate according to claim 1, wherein when the positions of n core particles are configured based on the quadratic linear programming layout method, comprising:
establishing a wire mesh coordinate system for a substrate track wire mesh on an active substrate;
randomly initializing the positions of n core particles on a substrate track wire mesh based on the established wire mesh coordinate system;
based on the positions of n core particles on the substrate track wire net after random initialization, calculating the bus length of the linear programming interconnection wire net in the current state;
determining planning initial positions of n core particles on a substrate track wire net based on the calculated linear planning interconnection wire net bus length;
and rationalizing the planning initial positions of the n core grains to obtain the planning layout positions of the n core grains.
3. The method of claim 2, wherein the substrate track net comprises a plurality of transverse track lines and longitudinal track lines which are distributed in a staggered manner, wherein,
the crossing joint points of the transverse track lines and the longitudinal track lines form network line nodes of a substrate track line network, and each network line node is provided with a crossing signal transmission circuit for configuring a signal transmission direction;
when the wire network coordinate system is established, the crossing signal transmission circuit at the lower left corner of the substrate track wire network is taken as an origin, the horizontal right is taken as the x axis of the wire network coordinate system, the vertical upward is taken as the y axis of the wire network coordinate system, the distance between adjacent transverse track wires is taken as the unit length of the y axis, and the distance between adjacent longitudinal track wires is taken as the unit length of the x axis.
4. The method of claim 2, wherein the linear programming interconnection net bus length in the current state is:
where f (x, y) is the linear programming interconnect net bus length, (x) i ,y i ) Is the position coordinate of the ith core particle, (x) j ,y j ) Is the position coordinate of the jth core particle, (x' m ,y′ m ) For the position coordinate of the mth fixed IO port, W ij The number of interconnected network wires between the ith core particle and the jth core particle, W im Is the number of interconnected wires between the ith core particle and the mth fixed IO port.
5. The method of claim 4, wherein when determining the planned initial positions of the n cores on the substrate track wire net, for minimizing the estimated bus length of the linear programming interconnection wire net, there are:
wherein ,
to derive the interconnect net bus length f (x, y), Q is the quadratic coefficient matrix obtained by expanding the interconnect net bus length f (x, y), d x 、d y And respectively obtaining a first order coefficient matrix of x and a first order coefficient matrix of y after the lengths f (x, y) of the interconnection network buses are unfolded.
6. A layout method for multi-core particles on an active substrate according to claim 3, wherein the rationalizing of the planned initial positions of n core particles comprises:
ordering the corresponding x-axis coordinates of the n core particles from small to large, and after ordering, ordering the core particles before
The core grains are placed on the left half of the substrate track net, and the rest core grains are placed on the right half of the substrate track net;
sorting the corresponding y-axis coordinates of the n core particles from small to large, so that after sorting, the first half of the core particles of each half are placed on the upper half of the substrate track net, and the rest are placed on the lower half; until n core particles are all in the effective positions of the substrate track net and are not overlapped with each other.
7. The method of any one of claims 1 to 6, wherein the initial temperature of the rapid simulated annealing method is configured to simulate the annealing bus wire length, and the method is based on a half perimeter calculation of a minimum rectangle containing the wire mesh.
8. The method of claim 7, wherein the reconfiguring the planned layout positions of the n cores by using the rapid simulated annealing method comprises:
determining a current simulated annealing temperature during rapid simulated annealing, and performing a core particle position adjustment step on the n core particles at the current simulated annealing temperature, wherein,
in each core particle position adjustment step, core particle position adjustment is performed for the same number of times; after each time of core position adjustment, determining cost function increment based on n pieces of core position information, so as to determine a position layout acceptance state after current position adjustment based on the cost function increment;
after the position adjustment step of each core particle is completed, updating the rapid simulated annealing temperature based on the position layout receiving state of each position adjustment until the rapid simulated annealing termination condition is met.
9. The method of claim 8, wherein when the simulated annealing bus line length is configured as a cost function, the cost function is:
wherein C is a cost function, (n) 1 ,n 2 ,…n i ,…n z ) For net, for the ith net n i Has n iw The number of vertices of the graph is,
for net n i Is the first vertex coordinate of (a);
delta C=C (S ') -C (S) is added to the cost function C, wherein C (S') is a cost function value based on n core particle position states S 'after position adjustment, C (S) is a cost function value based on n core particle position states S before position adjustment, and the position states S and S' are two position states adjacent to n core particles;
if the cost function increment delta C is less than or equal to 0, the position layout accepting state is configured to accept the new position layout; if ΔC >0, then exp (- ΔC/T) is taken as the probability of accepting the position state S';
if exp (- ΔC/T) is greater than the acceptance probability threshold, the position layout acceptance state is configured to accept as a new position layout.
10. The method of claim 9, wherein the probability threshold is a random number randomly generated and located between 0 and 1.
11. The method of claim 9, wherein updating the rapid simulated annealing temperature comprises:
wherein ,Tnew To quickly simulate the annealing temperature after updating, T old For the rapid simulated annealing temperature before the update, α is the rapid simulated annealing temperature T before the update old And then the acceptance rate of the step of adjusting the position of the core particle is adjusted.
12. The method of claim 11, wherein the acceptance rate α is a rapid simulated annealing temperature T before updating old In the next pellet position adjustment step, the number of accepted pellet position adjustments is divided by the rapid simulated annealing temperature T prior to updating old Total number of adjustments of the lower pellet position.
13. The method of claim 8, wherein the number of times the position of the core particle is adjusted in each core particle position adjustment step is n 2 。
14. The method of claim 8, wherein the simulated annealing termination condition comprises a updated rapid simulated annealing temperature of no more than one thousandth of an initial temperature.
15. A layout system suitable for multi-core grains on an active substrate comprises a layout processor, wherein,
a layout processor for an active substrate and n dice to be laid out on the active substrate, the layout processor laying out the dice based on the method of any one of the preceding claims 1 to 14 until a die is assigned to a target transposed connection.
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| CN116560005A (en) * | 2023-07-12 | 2023-08-08 | 中诚华隆计算机技术有限公司 | Core particle implementation method and system based on optical interconnection |
| CN116560005B (en) * | 2023-07-12 | 2023-09-08 | 中诚华隆计算机技术有限公司 | Core particle implementation method and system based on optical interconnection |
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