KR20130071331A - Method for automatically synthesizing tile routing structures for designing field programalbe gate array routing architecture - Google Patents

Abstract

PURPOSE: A method for automatically synthesizing a tile wiring structure for FPGA(Field Programmable Gate Array) wiring structure design is provided to automatically synthesize the tile wiring structure in order that an FPGA efficiently wires. CONSTITUTION: Shortest paths of a first tile and a second tile are searched(S130). A wiring pattern is searched corresponding to a search result of the shortest paths. Wiring patterns of first to third tiles are formed corresponding to the search result of the shortest paths. Third tiles are located on the shortest paths. The first to third tiles include the same wiring pattern. [Reference numerals] (AA) Start; (BB, EE, FF, II) No; (CC, DD, GG, HH) Yes; (JJ) End; (S110) Receive wiring structure specifications; (S115) Complex bundle wiring structure?; (S120) Configure a tile wiring graph; (S125) Convert into two point-to-point connection request using the minimum spanning tree; (S130) Search the shortest path on the tile wiring graph; (S135) Generate a bundle structure; (S140) Compose a simple bundle wiring structure; (S145) Bundle wiring structure to be composed is remained?; (S150) Wiring connection requested?; (S155) Configure a 3D wiring grid graph; (S160) Project a cell block and an existing wiring; (S165) Perform a time wiring device; (S170) Wiring connection request remained?

Description

FIELD OF AUTOMATICALLY SYNTHESIZING TILE ROUTING STRUCTURES FOR DESIGNING FIELD PROGRAMALBE GATE ARRAY ROUTING ARCHITECTURE}

The present invention relates to a semiconductor device, and more particularly, to a method for automatically synthesizing a wiring structure of an FPGA.

Field Programmable Gate Arrays (FPGAs) are semiconductor devices that contain programmable metal wiring and programmable logic elements to enable field implementation of desired functionality. In an FPGA, each logical element is arranged in a simple XY form to form a fabric of the matrix FPGA. Programmable logical elements may include AND, OR, XOR, NOT, and the like. Unlike ASICs, FPGAs have the advantage of short development time, error correction in the field, and low initial development cost because the connection of logic elements can be implemented by user's design.

Increasing functional requirements for FPGAs have increased the complexity of FPGAs. For example, FPGAs are provided with various processors, memory, high-performance Intellectual Property (IP), and high-speed I / O. As a result, the wiring structure of the FPGA is complicated and the wiring delay time is increased. Therefore, there is a need for a design tool that automatically synthesizes a wiring structure for improving FPGA performance by reducing wiring delay time of the FPGA.

An object of the present invention is to provide a method for automatically synthesizing a wiring structure so that the FPGA can perform efficient wiring.

According to an embodiment of the present disclosure, a method of automatically synthesizing a wiring structure of a field programmable gate array may include: searching for a shortest path between a first tile and a second tile; Searching for a wiring pattern according to the shortest path search result; And forming a wiring pattern of first to third tiles according to the wiring pattern search result, wherein the third tile is tiles located on the shortest path, and the first to third tiles are the same wiring. A method of automatically synthesizing a wiring structure to include a pattern.

According to one or more exemplary embodiments, a method of automatically synthesizing a tile wiring structure for a field programmable gate array wiring structure design includes: forming a three-dimensional wiring grid graph; Setting different weights according to directions on the 3D wiring grid graph; Projecting cell blocks of pad tiles onto the 3D wiring grid graph; Setting additional weights on the 3D wiring grid graph based on the projected cellblocks; And forming a wiring pattern on the logic tile and the pad tile based on the weight and the additional weight, wherein the set additional weight is closer to the projected cell blocks in the 3D wiring grid graph. It is a method of automatically synthesizing the wiring structure set to a high level.

According to the present invention, there is provided a method for automatically synthesizing a wiring structure through which tiles having the same wiring pattern can realize a desired connection relationship. Thus, there is provided a wiring synthesis method with reduced cost and improved performance.

1 shows a hierarchical wiring structure of an FPGA.
2 shows an example of horizontal double wiring.
3 shows a tile structure for horizontal double wiring according to an embodiment of the present invention.
4 shows an example in which the tiles of FIG. 3 are repeatedly connected.
5 shows an example of a composite wiring structure in which horizontal / vertical wiring is mixed.
6 illustrates a tile structure for the wiring structure of FIG. 5 according to an exemplary embodiment of the present invention.
FIG. 7 illustrates a wiring structure implemented by repeating the tile of FIG. 6.
8 is a block diagram showing the structure of an FPGA tile.
9 is a flowchart illustrating a method of automatically synthesizing a wiring structure of an FPGA tile block.
10 shows an example of horizontal double wiring.
11 is a view illustrating a bundle structure for horizontal double wiring according to an exemplary embodiment of the present invention.
12A through 12C illustrate a step of synthesizing a horizontal double wire bundle according to an exemplary embodiment of the present invention.
13 shows an example of a horizontal hex wiring.
14 shows the synthesis result of the horizontal hex wiring according to an embodiment of the present invention.
FIG. 15 shows an example of repeating the horizontal hex wiring tile of FIG. 14.
16 is a block diagram illustrating a structure of a tile having various horizontal / vertical bundles according to an embodiment of the present invention.
FIG. 17 shows an embodiment of a tile having double wiring in up / down / left / right directions.
18 shows a tile wiring model according to an embodiment of the present invention.
19 illustrates a connection diagram of a tile wiring graph and a wiring structure according to an exemplary embodiment of the present invention.
20A and 20B illustrate a shortest distance searching method according to an embodiment of the present invention.
FIG. 21 shows a connection diagram between two points of a tile wiring graph and a wiring structure in which the search area is bounded by the tile wiring graph of FIG. 19.
22 illustrates a shortest path search result on a wiring graph according to an exemplary embodiment of the present invention.
23 shows bundles extracted from the shortest path according to an embodiment of the present invention.
24 is a view illustrating a location allocation of a bundle in a tile according to an embodiment of the present invention.
25 is a view illustrating a synthesized tile wiring structure according to an embodiment of the present invention.
FIG. 26 illustrates an embodiment in which the tiles of FIG. 25 are repeatedly arranged.
27 shows the tile structure of the FPGA.
28 shows a wiring structure of a block memory tile.
29 shows the wiring structure of the pad tile.
30 is a view illustrating a tile wiring grid according to an embodiment of the present invention.
FIG. 31 illustrates a three-dimensional tile wiring grid graph in which the tile wiring grid of FIG. 30 is modified in three dimensions.
32 is a graph illustrating a projection of a cell block and a conventional wiring structure onto a three-dimensional wiring grid graph according to an embodiment of the present invention.
33 shows an example of the wiring failure of the back wiring due to the wiring.
34 is a view illustrating a weight setting method near a cell area according to an embodiment of the present invention.
35 shows an embodiment in which wiring is successful by adjusting the weight.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention. .

1 shows a hierarchical wiring structure of the FPGA 100. Referring to FIG. 1, the hierarchical wiring structure of the FPGA 100 includes a single wiring R01, a double wiring R02, a hex wiring R03, and the like. The single wiring R01 is a wiring directly connected to one logic block and adjacent adjacent logic blocks. The double wiring R02 is a wiring directly connected to logic blocks two blocks apart in the up / down / left / right directions. The hex wire R03 is a wire directly connected to logic blocks 6 blocks apart in the up / down / left / right directions, and a terminal connectable to the third blocks may be provided.

The FPGA 100 includes logic blocks and tile blocks having a programmable wiring structure. The structure of the FPGA is formed by repeatedly placing logical blocks and tile blocks by a desired capacity.

2 to 4 show examples of wiring structures for double wiring and double wiring. 2 to 4, when the double wiring shown in FIG. 2 is implemented, the wiring structure shown in FIG. 3 may be formed in the tile block. As shown in FIG. 4, a desired wiring structure may be formed through simple repetition of tiles having the wiring structure shown in FIG. 3.

5 to 7 show an example in which three tile blocks are connected through a double wiring. When the dual wiring shown in FIG. 5 is implemented, the wiring structure shown in FIG. 6 and the wiring structure shown in FIG. 3 may be formed in the tile blocks. As shown in FIG. 7, the desired wiring structure may be formed through repetition of the wiring structures illustrated in FIGS. 3 and 6.

The present invention receives the connection relationships of the wiring structures shown in FIG. 2 or 5, and through the automatic synthesis of the tiles shown in FIG. 3 or 6, the wiring structure of the FPGA shown in FIGS. It provides a method to be formed. In addition, in the present invention, when a wiring structure of a PAD / IP (Intellectual Property) tile block including IP hardware such as a pad or a block memory and a multiplier is synthesized, the wiring structure is synthesized so that tiles having a predetermined wiring structure can be connected. It provides a way to be.

8 shows the structure of an FPGA tile (Configurable Logic Block, T [0,1]). The function block 110 of the tile T [0,1] implements the logic of the circuit. In the case of an SRAM type FPGA, the function block 110 includes a look-up table, a mux, a flip-flop, and the like.

The switch box 120 includes a plurality of switches. The switch box 120 may receive programming information from the outside and implement a desired connection through a plurality of switches. The metal wires include horizontal wires 130 and 140 above and below the switch box and vertical wires 150 and 160 on the left and right sides.

9 is a flowchart illustrating an operation of a tile synthesizer according to an embodiment of the present invention. By way of example, tile wiring structures are synthesized according to the flowchart shown in FIG. 9.

Referring to FIG. 9, in step S110, the tile synthesizer receives a wiring structure specification. In step S115, it may be determined whether the received wiring structure specification is a composite bundle wiring structure. According to the determination result, if the composite bundle wiring structure is not, in step S140, the simple bundle wiring structure may be synthesized.

According to the determination result, in the case of the composite bundle wiring structure, the tile wiring graph may be configured in step S120. In step S125, the configured tile wiring graph may be converted into a two-point connection request using the minimum extension tree. In operation S130, the shortest path may be searched on the tile wiring graph to be converted. In operation S135, the bundle structure may be generated based on the shortest path search result. In operation S140, a simple bundle wiring structure may be synthesized.

In operation S145, it may be determined whether a bundle wiring structure to be synthesized remains. According to the determination result, when the bundle wiring structure to be synthesized remains, the operation of step S115 is performed. According to the determination result, if there is no bundle wiring structure to be synthesized, it may be determined whether there is a wiring connection request in step S150. If there is no wiring connection request, the tile wiring structure synthesizing operation is terminated.

If there is a wiring connection request, in step S155, a 3D wiring grid graph may be constructed. In operation S160, the cell block and the existing wiring may be projected onto the configured 3D wiring grid graph. In step S165, the tile wiring machine is performed based on the three-dimensional wiring grid graph. In step S170, it may be determined whether a wire connection request remains. If a wire connection request remains, the operation of step S165 is performed. If no wiring connection request remains, the tile wiring structure synthesizing operation ends. Hereinafter, the method of synthesizing the tile wiring structure of FIG. 9 will be described in detail.

10 to 12 illustrate a tile wiring structure for horizontal double wiring and horizontal double wiring according to an exemplary embodiment of the present invention. By way of example, for the sake of brevity, the components of the tile blocks and the reference numbers thereof are omitted.

10 to 12, the horizontal double wire R02 is connected only in the horizontal direction. This wiring structure is called a simple bundle wiring structure. The simple bundle wiring may include one bundle 200 shown in FIG. 11. The double wiring R02 starting from the port P1 of the tile T [0,1] shown in FIG. 2 passes through the tile T [1,1] to the port (T [2,1]) of the tile (T [2,1]). Connected to P2). In the case of the horizontal wiring, the stage number is allocated based on the left tile and in the case of the vertical wiring, the stage number is increased while proceeding to the right (upper). For example, the first to third stage numbers are assigned to the tiles T [0, 1], T [1, 1], and T [2, 1] of FIG. 10, respectively.

The number of stages of the double line R02 shown in FIG. 10 is 3, and tracks such as Equation 1 are allocated to the bundle 200 for implementing the double line R02.

According to Equation 1, the first and second tracks are allocated to the bundle 200 of FIG. 11. The horizontal double wire structure is implemented in tracks assigned to the double wire bundle in each stage order. For example, as shown in FIG. 12A, a first stage in which a first track is connected to the port P1 is implemented. As shown in FIG. 12B, a second stage is implemented in which wiring lines are connected starting from the first track and changing from the offset change point 201 to the second track. As shown in FIG. 12C, a third stage to which the second track and the port P2 are connected is implemented.

13 shows an example of a horizontal hex wiring. Referring to FIG. 13, the horizontal hex wiring R03 includes a port P1 of the tile T [0,1], a port P2 of the tile T [2,1], and a tile T [5,1]. ]) Is connected to port P3. The wiring structure shown in FIG. 14 is synthesized in the same manner as described with reference to FIGS. 10 to 12. When six tiles shown in FIG. 14 are connected in a horizontal direction, the horizontal hex wiring R03 shown in FIG. 15 is implemented.

16 illustrates a structure of a tile including a plurality of bundles according to an embodiment of the present invention. Referring to FIG. 16, an FPGA disc includes various types of bundles 220, 230, 240, 250, 260, 270, 280, and 290 for implementing various types of wiring, and each bundle 220, 230. , 240, 250, 260, 270, 280, and 290 may include tracks based on Equation 1. Through the tracks based on Equation 1, the wiring structure can be synthesized.

17 illustrates an example of a tile including dual wires in up, down, left, and right directions according to an exemplary embodiment of the present invention. Referring to FIG. 17, through the wiring structure illustrated in FIG. 17, tiles positioned in upper / lower / left / right and double wirings may be formed and connected to each other.

In the case of the complex wiring structure in which the horizontal and vertical wirings shown in FIG. 5 are mixed, it is impossible to implement a single bundle wiring structure. Thus, the wiring structure may include a plurality of bundle structures.

As shown in FIG. 18, the present invention provides a tile wiring model in which the elements necessary for synthesizing the wiring structure in one tile are simplified and represented in a graph form. In the tile wiring model, a circle is a connection point for wiring elements such as wiring tracks and ports. In the tile wiring model, the connecting line means a connection relationship between each wiring element. PN refers to all ports located north of the switch box. PS refers to all ports located south of the switch box. PW refers to all ports located west of the switch box. PE refers to all ports located east of the switch box. HN indicates horizontal wiring tracks assigned to the north of the switch box. HS refers to the horizontal wiring tracks assigned to the south of the switch box. VW refers to the vertical wiring tracks assigned to the west of the switch box. VE refers to the vertical wiring tracks assigned to the east side of the switch box.

19 illustrates a tile wiring graph according to an embodiment of the present invention.

5, 18, and 19, the tile synthesizer receives the wiring structure specification to be synthesized. An example in which a wiring connection request is expressed by a tile wiring graph constructed using the tile wiring model of FIG. 18 is shown in FIG. 19. The tile wiring graph is a graph in which the tile wiring model is composed of a two-dimensional array.

20 illustrates a method of searching for the shortest path based on the connection request shown in FIG. 19. 19 and 20, in order for the wiring structure to be generated to be realized with a minimum track, ports P1, P2, and P3 having a connection request are determined as connection points, and a Manhattan distance to the connection lines connecting the connection points. A complete graph is formed with a weight of (manhattan distance). The complete graph is shown in FIG. 20A. Based on the formed graph, a minimum spanning tree is formed, and several two-point connection requests are formed. The connection request formed is shown in FIG. 20B.

21 to 22 show a result of removing regions other than the bounding boxes of each of the two-point connection requests shown in FIG. 20B from the tile wiring graph shown in FIG. 19. The tile synthesizer can obtain a brief result through the process of FIG. 21. 21 to 22, the tile synthesizer may apply the graph shortest path algorithm to the shortest path between two connection points in the tile wiring graph. The tile synthesizer can find the shortest path R20 shown in FIG. 22.

Among the connection points associated with the wiring track located on the shortest path R20, when the same type of continuous connection points are divided and bundled, a vertical bundle 290 and a horizontal bundle 240 are generated as shown in FIG. 22. Coordinates are adjusted so that the tracks are connected when the connection point 300 between the bundles 240 and 290 of FIG. 22 is extracted and the wiring track is assigned to each bundle as shown in FIG. 25.

FIG. 23 shows two bundles 240 and 290 extracted from the shortest path of the tile wiring graph, and the two bundles are assigned positions to the bundles as shown in FIG. 24 according to the type of connection points constituting the bundles. do. When the bundles of FIG. 24 are synthesized by the method of synthesizing the simple bundle interconnection structure described above, the final tile interconnection structure is synthesized as shown in FIG. 25. If the synthesized tiles are arranged in 3x3, a wiring structure like the wiring structure specification shown in Fig. 26 can be formed.

As shown in FIG. 27, the PAD / IP tile is implemented in a one-dimensional array unlike a logic tile in a two-dimensional array. A PAD / IP (Intellectual Property) tile block is a tile that includes IP hardware such as pads or block memories and multipliers. The pad tiles are arranged in one row or one column at the east / west / south / north edge of the FPGA chip, and the block memory tiles are inserted one row in the middle of the structure of the logic tiles.

The wiring structure of the PAD / IP tile may include tile wirings connected to or passing through bundle wirings and logic tiles between block memory tiles in the same row or column as the block memory tiles shown in FIG. 28.

FIG. 29 illustrates a wiring structure of an east pad tile 500_1 as an example among four pad tile shapes of east / west / south / north. The wiring structure of the pad tile is also composed of bundle wiring between the pad tiles and tile wirings connected to the logic tile on the left side.

In the case of bundle wiring of PAD / IP tiles, the position of each wiring may be arbitrarily determined. In the case of the wiring connected to the logic tile, since the wiring of the logic tile is already determined, the wiring structure should be formed in consideration of the position of each wiring to be connected. Therefore, the bundle interconnection structure between the PAD / IP tiles is synthesized using the bundle interconnection generation algorithm illustrated in FIGS. 10 to 26, and based on the result, the interconnections connected to the logic tile are connected using the tile interconnector.

The wiring grid shown in FIG. 30 is introduced so that the signal lines input in the mesh form are connected in the tile space. The wiring grid is a grid including virtual grid lines where wirings may be located by dividing the wiring space in the tile based on the minimum distance between the wirings. The tile wiring is only on the grid and includes an X-grid for vertical wiring and a Y-grid for horizontal wiring.

The wiring grid shown in FIG. 30 may be modeled with the three-dimensional tile wiring grid graph shown in FIG. 31. The X / Y axis of the tile wiring grid graph is the same as the X / Y axis of the wiring grid of FIG. 30, and the Z axis has a magnitude of two. The three-dimensional tile wiring grid graph includes a plane π 00 and a plane π 01. Horizontal wirings are assigned to the plane pi, and vertical wirings are assigned to the plane pi01. Plane π00 includes only horizontal connectors and plane π01 includes only vertical connectors. Z-direction connecting lines to which respective corresponding connecting points of the planes π00 and π01 are connected are allocated. Ports of each cell to be wired are mapped to connection points. Weights are assigned to each connection point and the connection lines. Based on the assigned weights, the length and shape of the wires can be adjusted.

After the bundle wirings are formed, tile wirings are formed. Therefore, in order to prevent the tile wiring from invading the regions of the bundle wirings and the regions occupied by the cell blocks, connection points and connecting lines corresponding to the regions of the existing wirings and the cell blocks are blocked as shown in FIG. 32.

In addition, when the wiring path is meandering, the readability of the circuit is reduced, so that the connection lines in the Z direction are assigned a greater weight than the connection lines in the X / Y direction in order to minimize the bending of the wiring line. As illustrated in FIG. 33, the first wiring R11 and the second wiring R12 may be formed before the third wiring R13. When the first and second wirings are wired close to the cell port P5 to be connected to the third wiring R13, the minimum space necessary for the connection of the third wiring R13 is not secured and the wiring fails. In order to reduce the wiring failure according to the wiring order, as the closer to the cell block region as shown in the X / Y connecting line weight graph of FIG. Do not let go.

The result of applying the connection point weights shown in FIG. 34 is shown in FIG. 35. As shown in FIG. 35, the first wiring R21 and the second wiring R22 are allocated to a low-weight grid that is far from the cell block. Therefore, space for the third wiring is secured, and the wiring of the third wiring R33 is successful.

On the three-dimensional wiring grid graph constructed based on the application of the weights of FIGS. 31 to 34, the tile interconnector finds and wires the shortest path having the smallest sum of weights among the ports to be connected. The shortest path search method is a method of backtracking connection points on a path whose minimum sum of weights is reached when the graph is searched in the width-first search method starting from the starting point on the wiring grid graph and reaching the target point. This creates the wiring lines connecting the connection points on the shortest path.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the following claims.

100: FPGA
R01, R02, R03: Wirings
P1, P2, P3, P4, P5: Ports
110: function block
120: switch box
130, 140, 150, 160: horizontal and vertical wires
200: bundle
π00, π01: planes

Claims (2)

A method of automatically synthesizing tile interconnect structures for field programmable gate array interconnect design,
Searching for the shortest path of the first tile and the second tile;
Searching for a wiring pattern according to the shortest path search result; And
Forming a wiring pattern of the first to third tiles according to the wiring pattern search result;
The third tile is tiles located on the shortest path,
And the first to third tiles include the same wiring pattern. A method of automatically synthesizing tile interconnect structures for field programmable gate array interconnect design,
Forming a three-dimensional wiring grid graph;
Setting different weights according to directions on the 3D wiring grid graph;
Projecting cell blocks of pad tiles onto the 3D wiring grid graph;
Setting additional weights on the 3D wiring grid graph based on the projected cellblocks; And
Forming a wiring pattern on the logic tile and the pad tile based on the weight and the additional weight;
And the set additional weight is set higher in the grid close to the projected cell blocks in the 3D wiring grid graph.

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