CN104318025A - Octilinear Steiner minimal tree VLSI (very large scale integration) obstacle-avoiding wiring unit - Google Patents
Octilinear Steiner minimal tree VLSI (very large scale integration) obstacle-avoiding wiring unit Download PDFInfo
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Abstract
The invention relates to an octilinear based fast VLSI (very large scale integration) obstacle-avoiding Steiner minimal tree wiring unit in the technical field of computer aided design of integrated circuits. The fast and efficient obstacle-avoiding octilinear Steiner minimal tree wiring unit is designed for the problem about global wiring in VLSI layout design. According to a chip pin set given in actual industrial production, the wiring unit is characterized in that firstly, an obstacle-free Euclid minimal spanning tree (MST) is constructed; secondly, two fast lookup tables in regard to edge information in the MST are generated, and the tables can provide a fast information acquisition function for subsequent steps; thirdly, the wiring unit selects some inflection points on an obstacle as relay nodes of barrier crossing edges in the MST by completing an efficient obstacle-avoiding strategy so as to convert the previous MST into an obstacle-avoiding octilinear tree; finally, by applying a shared-edge principle based refining strategy, the wiring unit generates a final obstacle-avoiding octilinear Steiner minimal tree wiring result.
Description
Technical field
The invention belongs to integrated circuit CAD technical field, be specifically related to a kind of based on the quick VLSI under anistree structure Steiner minimum tree around barrier wiring unit construction problem.
Background technology
VLSI (very large scale integrated circuit) (very large scale integration, VLSI) around the anistree structure Steiner minimum tree of barrier (Obstacle-avoiding Octilinear Steiner Minimal Tree in designing, OAOSMT) problem is at a chip surface, given one group of pin set and one group of barrier set, utilize 0o, 45o, 90o, and 135o metal wire builds the Steiner tree that connects all pins, and walk around all given barriers, make to connect up simultaneously and set the minimum combinatorial optimization problem of total length.
Since within 1966, having breathed out since smooth grid proposed first, Steiner tree in right angle has been widely used the various aspects of VLSI chip wiring problem.On the other hand, due to the sharply increase of VLSI chip density, many restructural assemblies have been embedded in modern chips, as IP kernel and macro block.And these assemblies can not be passed through in wiring process.Therefore, the more than ten years in the past, obtained around barrier right angle Steiner tree Construct question and studied widely, and achieved many achievements.But, due to wiring direction is restricted to by right-angle structure can only horizontal and vertical cabling, this has great restriction ability for the many key indexs optimizing chip, as total line length, congested and time delay index etc.Therefore, current wiring technique is just standing in a crossroad, and receives the extensive concern of many research institutions.The thing followed is, along with the continuous progress of VLSI chip manufacturing process, on-right angle structure obtains and develops rapidly.Particularly anistree structure, it is as one of outstanding on-right angle structure of performance, almost support by current all production technologies.In other words, 45o and 135o oblique line is successfully applied to anistree routing planes.Compared to right-angle structure, because anistree structure can packed wiring length greatly, thus reach to reach and optimize time delay, Inductance and Capacitance, the multinomial performance index such as congested.There are some researches show, compare with the Steiner tree under right-angle structure, anistree structure can compress via count 40% respectively, total line length 20%, chip area 11%.Therefore academia and industry member all start comprehensively to have put in the research work of anistree structure in recent years.But as far as we know, current research work still rests on the routing planes stage of clear mostly.Namely mostly first achievement supposes that routing planes clear exists, and then utilizes anistree structure optimization such as line length, time delay, congested in interior multinomial performance index.And under anistree structure, there is the situation of barrier, related ends does not almost have.Therefore, the Quick winding barrier wiring unit researched and developed under a kind of anistree structure just seems particularly urgent.
Summary of the invention
The object of this invention is to provide one and consider to there is barrier in VLSI (very large scale integrated circuit) loose routing problem, introduce the wiring unit construction problem of anistree structure Steiner minimum tree simultaneously.To optimize wiring tree overall length for target, and then such as time delay, the many index such as congested are optimized.The method is considered, around the structure of barrier Steiner minimum tree, to obtain outstanding solution scheme within the extremely short time from the overall angle of loose routing.
The present invention adopts following scheme to realize: the VLSI under a kind of anistree structure Steiner minimum tree, around barrier wiring unit, is characterized in that comprising the following steps:
Step S01: according to given one group of pin coordinate position, generate one group of Delaunay triangulation, then generates by related algorithm the MST that connects all pins;
Step S02: for all limits in MST, generates the look-up table of two writing edge link informations;
Step S03: based on look-up table, is converted to one around the anistree Steiner tree of barrier by the MST that the first step generates; This anistree Steiner tree introduces some flex points on barrier to reach the object around barrier;
Step S04: share principle based on limit, calculates the optimum syndeton of each node in the anistree Steiner tree of the 3rd step generation, to reach the target maximizing and share edge lengths.
Further, the related algorithm in described step S01 is Kruskal algorithm or Prim algorithm.
Further, described look-up table comprises the look-up table that two have recorded limit link information, and first table is called limit-barrier look-up table, and it records the set of the barrier that each anistree limit is passed through; Second table is called limit-line look-up table, and it have recorded the coordinate position of two points of line segments on each anistree limit.
Further, the generation step of described look-up table is as follows:
Step S41: check the in MST
ibar limit
p i p j , for each cabling mode
k, calculate two points of line segments
p i s k with
s k p jstarting point coordinate and terminal point coordinate, wherein,
p i ,
p j it is pin given on two chips;
Step S42: for each barrier
bif,
p i s k or
s k p j pass through
b, then will
bjoin relative set
b ijk , wherein
s k for P
iand P
jthis tower of puppet when connecting in anistree mode that;
Step S43: establish
l ijk for
b ijk the semi-perimeter sum of inner all barriers; Calculate each
b ijk corresponding
l ijk ; Then incite somebody to action
b ijk and
l ijk join in limit-barrier look-up table;
Step S44: check each
p i s k with
s k p j if there is 45o or 135o oblique line, then it to be turned clockwise 45o around initial point, thus form a new level or vertical line segment;
Step S45: record
p i s k with
s k p j coordinate figure to limit-line look-up table;
i=
i+ 1, if
i<n, return step S41, otherwise terminate.
Further, the described implementation around barrier comprises the following steps:
Step S51: check the in MST
ibar limit
p i p j if,
p i p j 0or
p i p j 1all barriers can be walked around, then elect wire laying mode as 0 or 1, investigate the i-th+1 limit; Otherwise enter step S52;
Step S52: if
p i p j 2or
p i p j 3all barriers can be walked around, enter step S53, otherwise enter step S54;
Step S53: if
l ij0 <
l ij1 , then selection mode 0 as a result.Otherwise selection mode 1 as a result; Return step S51 and investigate next limit;
Step S54: select
l ijk be worth minimum that as net result.Return step S51 and investigate next limit.
Further, the account form of described optimum syndeton comprises the following steps:
Step S61: in the anistree Steiner tree of surface sweeping, all limits are once, add up the number of degrees of each point, and other point being connected to this point is recorded as a set;
Step S62: for each some P, if its number of degrees are
d, then 4 are enumerated
d individual wiring combination; Select around barrier and the shortest optimum structure as P of line length, and calculate the shared edge lengths of this structure;
Step S63: according to the nonincremental order of shared edge lengths of each optimum structure to sorting a little;
Step S64: apply each optimum structure put in order in original anistree Steiner tree, until the cabling mode on all limits of anistree Steiner tree was updated.
First wiring unit of the present invention builds a MST based on one group of pin coordinate that production problem is given.The existence of barrier is not considered in the generation of this MST, and generates based on Delaunay triangulation, effectively raises the speed that MST generates.Secondly, the generation of two Fast Lookup Tables can regard a kind of pre-service to all pins and barrier as.Namely the information obtained may be needed by subsequent step in advance to calculate and be stored in table, instead of calculate respectively when subsequent step is used at every turn.This pretreatment strategy drastically increases the execution efficiency of wiring unit to subsequent step, because all limits and the interconnected information of barrier only need calculate once.In addition, MST is being converted to one in the process of the anistree Steiner tree of barrier, most implementation realizes by tabling look-up.And for getting around the limit of barrier, this wiring unit is reached object around barrier by the flex point on penetrate thing as the strategy of relaying by choosing.This can realize under the prerequisite of barrier by making this wiring unit, the target that the satisfied extra Steiner point chosen is minimum simultaneously.Finally, the refining strategy based on shared limit principle can utilize interconnection resource fully, with maximum sharing degree optimization wiring overall length, decreases the area of wiring area simultaneously, and then improves the multinomial performance index of chip.
Accompanying drawing explanation
Fig. 1 is based on the process flow diagram of a kind of quick VLSI under anistree structure Steiner minimum tree around barrier wiring unit.
Fig. 2 is four kinds of limit cabling selection mode figure under anistree structure.
Fig. 3 is barrier flex point selection strategy figure.
The wiring diagram example that Fig. 4 finally generates.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public embodiment.
The present invention first wiring unit, according to the coordinate position of one group of n pin given in production problem, builds one group of Delaunay triangulation based on line sweep algorithm.Because the limit of this group triangulation adds up to
o(n), therefore wiring unit can based on these triangulation limits, application Kruskal minimal spanning tree algorithm,
o (nlogn)time in construct one and connect the MST of all pins.Next, for all limits in MST, two Fast Lookup Tables that have recorded these limit link informations will be generated.Wherein first table is called as limit-barrier look-up table, and it have recorded the set of the barrier that each limit is passed through when being converted to anistree cabling in MST.Second table is called as limit-line look-up table, and it have recorded the coordinate position of two points of line segments when each limit in MST is converted to anistree cabling.These two tables all can provide information inquiry fast for the follow-up work of wiring unit.After look-up table generates, for the limit of each in MST, wiring unit, by inquiry limit-barrier look-up table, is found out the anistree cabling mode of one of not penetrate thing, and this MST limit is directly converted to this anistree limit.If the equal penetrate thing of all anistree cabling modes, this wiring unit then by selecting by the some flex points on penetrate thing as via node, thus reaches the object around barrier.Finally, for generate above around barrier anistree Steiner tree, this wiring unit shares principle based on limit, by calculating the optimum interconnection structure of each node, namely maximizing and sharing edge lengths, thus generates final around the minimum anistree Steiner tree wiring result of barrier.
Specifically be divided into following four steps:
1. according to given one group of pin coordinate position, generate one group of Delaunay triangulation, then apply Kruskal minimal spanning tree algorithm, generate the MST that connects all pins;
2., for all limits in MST, generate the look-up table of two writing edge link informations;
3., based on look-up table, the MST that the first step generates is converted to one around the anistree Steiner tree of barrier.This anistree Steiner tree introduces some flex points on barrier to reach the object around barrier;
4. share principle based on limit, calculate the optimum syndeton of each node in the anistree Steiner tree of the 3rd step generation, to reach the target maximizing and share edge lengths.
In order to allow those skilled in the art better understand the present invention, below in conjunction with accompanying drawing and experimental result, the present invention will be further described:
1. define 1 (pseudo-Steiner point) and suppose the tie point except pin, be called pseudo-Steiner point.S in Fig. 2
0, S
1, S
2and S
3be pseudo-Steiner point, in pseudo-Steiner point, comprise Steiner point.
Define 2 (0 selects) as shown in Fig. 2 (a), p
1(
x 1 ,
y 1 ) and p
2(
x 2 ,
y 2 ) be two end points of limit L, wherein
x 1 <
x 2 .The selection of the pseudo-Steiner point that limit L is corresponding as shown in Fig. 2 (b), from p
1first draw limit, Manhattan to s
0, then by s
0draw non-Manhattan limit to p-
2..Then be called 0 selection.
Shown in definition 3 (1 selects) Fig. 2 (c), from p
1first draw non-Manhattan structure limit to s
1, then from s
1draw structure limit, Manhattan to p
2, then 1 selection is called.
Shown in definition 4 (2 select) Fig. 2 (d), from p
1first draw vertical edge to s
2, then by s
2draw horizontal sides to p
2, then 2 selections are called.
Shown in definition 5 (3 select) Fig. 2 (e), from p
1first draw horizontal sides to s
3, then by s
3draw vertical edge to p
2, then 3 selections are called.
2.MST generation strategy:
In accessible plane, there is many MST developing algorithm.In order to improve formation efficiency, this wiring unit have employed a kind of construction strategy based on triangulation.It is first based on given one group of pin Coordinate generation one group of triangulation.Then Prim algorithm or Kruskal algorithm can be
o(nlogn)a MST is generated in time.
3. look-up table generates:
Under anistree plane, this wiring unit, for limits all in MST, generates the look-up table that two have recorded limit link information.First table is called limit-barrier look-up table, and it records the set of the barrier that each anistree limit is passed through.Second table is called limit-line look-up table, and it have recorded the coordinate position of two points of line segments on each anistree limit.
Suppose that problem is given
nindividual pin, then MST comprises
narticle-1, limit.Because there are four kinds of anistree cabling modes on every bar limit, therefore one co-exist in 4*(
n-1) the anistree limit of bar.For each anistree limit
p i p j k(
p i ,
p j be two pins,
kfor cabling mode), the present invention calculates
p i p j kthe all barriers passed through and be recorded as a set
b ijk , then will
l ijk value be set to the semi-perimeter sum of these barriers.All 4*(
n-1) group
b ijk and
l ijk constitute final limit-barrier look-up table.In addition each anistree limit
p i p j kby two points of line segments form (
p i s k ,
s k p j ), the present invention records the extreme coordinates of these two points of line segments respectively.These information on all limits constitute final limit-line look-up table.The detailed step that look-up table generates is as follows, initialization
i=1,
(1) the in MST is checked
ibar limit
p i p j , for each cabling mode
k, calculate two points of line segments
p i s k with
s k p jstarting point coordinate and terminal point coordinate.
(2) for each barrier
bif,
p i s k or
s k p j pass through
b, then will
bjoin relative set
b ijk .
(3) calculate each
b ijk corresponding
l ijk .Then incite somebody to action
b ijk and
l ijk join in limit-barrier look-up table.
(4) each is checked
p i s k with
s k p j if there is 45o or 135o oblique line, then it to be turned clockwise 45o around initial point, thus form a new level or vertical line segment.
(5) record
p i s k with
s k p j coordinate figure to limit-line look-up table.
i=
i+ 1, if
i<n, return (1), otherwise terminate.
Here have it is noted that for each barrier in second step at 2
b, the present invention investigates it, and and if only if
bat least one flex point is had to drop into
p i with
p j in the square boundary frame formed.Secondly, if there is 45o or 135o oblique line, the present invention is rotated to be level or perpendicular line in (4) step, and records the coordinate of new line segment.This can facilitate the calculating of subsequent step local and overall line length, because 45o or the 135o oblique line of overlap can be easy to identified when not changing length.
4., around barrier strategy: in this step, first the MST that early stage generates will be converted into an anistree Steiner rapidly and be set.The present invention checks each limit in MST
p i p j .By tabling look-up, if anistree limit
p i p j 0or
p i p j 1all barriers can be got around, then directly will
p i p j wire laying mode be chosen as 0 or 1 mode.Else if
p i p j 2or
p i p j 3can walk around all barriers, the present invention is then according to L
ij0and L
ij1size select.If
l ij0 <
l ij1 , then selection mode 0 as a result.Otherwise selection mode 1 as a result.If wire laying mode has all passed through barrier in 4, the present invention has then selected
l ijk be worth minimum that as wire laying mode.Detailed step is as follows, initialization
i=1,
(1) the in MST is checked
ibar limit
p i p j if,
p i p j 0or
p i p j 1all barriers can be walked around, then elect wire laying mode as 0 or 1, investigate the i-th+1 limit.Otherwise enter (2).
(2) if
p i p j 2or
p i p j 3all barriers can be walked around, enter (3), otherwise enter (4).
(3) if
l ij0 <
l ij1 , then selection mode 0 as a result.Otherwise selection mode 1 as a result.Return (1) and investigate next limit.
(4) select
l ijk be worth minimum that as net result.Return (1) and investigate next limit.
Obviously, barrier has been passed through on some limits in anistree Steiner tree.Therefore the present invention proposes and a kind of help these limits around barrier method and walk around all barriers.For each limit in anistree Steiner tree
p i p j k(
khere determine), if he has passed through barrier, the present invention has directly deleted this edge.Then to barrier set
b ijk according to
p i order to barrier centre distance non-decreasing sorts.Next, starting point is set
s=
p i .The present invention investigates one by one to the barrier after sequence, chooses a flex point from current barrier at every turn
cas via node, here
cto straight line in four flex points
sP j nearest that.Then the present invention calculates limit
sClink information, and to be added in two look-up tables.S is being connected to
cafterwards, the present invention will
cbe set to new
s, and continue to investigate next barrier, to the last a flex point selected is connected to
p j .
This may be performed for several times, until all barriers are walked around on all limits around barrier method.Fig. 3 is an example around barrier method.Fig. 3 (a) is original limit P
1p
23, it has passed through barrier B
1and B
2.After original limit is deleted, first the present invention investigates barrier B
1, because its distance P-
1nearer.Due to C
1b
1upper distance straight line P
1p
2nearest flex point, is therefore chosen as via node, and is connected to P
1(Fig. 3 (b)).Then the present invention investigates B
2, in Fig. 3 (c), C
2be connected to C
1because it is B
2upper distance straight line C
1p
2a nearest flex point.Finally, C
2be connected to P
2in Fig. 3 (d).Notice that the link information on all new limits all should be added in look-up table, because they are useful for follow-up refinement step.
5., for any one point in anistree Steiner tree, all there is an optimum syndeton in refining strategy: in fact.A kind of refining strategy based on shared limit principle is the present invention proposes based on this.By to all limits run-down in this smooth tree anistree, first the present invention obtains number of degrees of each point, and records other some set being connected to each point.Then for each some P, suppose that its number of degrees are
d, the present invention enumerates all 4
d kind of cabling array mode, and select and can walk around all barriers and the shortest that optimum structure as this point of line length.Next, the present invention calculates the length sharing limit in each some optimum structure, and according to the nonincremental order of this length to sorting a little.Finally according to the dot sequency after sequence, each optimum structure put is applied on original anistree Steiner tree, thus obtains final wiring tree.Detailed step is as follows:
(1) in the anistree Steiner tree of surface sweeping, the number of degrees of each point once, are added up in all limits, and other point being connected to this point is recorded as a set.
(2) for each some P, if its number of degrees are
d, then 4 are enumerated
d individual wiring combination.Select around barrier and the shortest optimum structure as P of line length, and calculate the shared edge lengths of this structure.
(3) according to the nonincremental order of shared edge lengths of each optimum structure to sorting a little.
(4) each optimum structure put is applied in order in original anistree Steiner tree, until the cabling mode on all limits of anistree Steiner tree was updated.
Have require emphasis at 3.The first, in step (2), judge whether a wiring combination can directly realize by tabling look-up around barrier, therefore very efficient.Secondly, in step (4), if certain the limit cabling mode of original anistree Steiner tree was updated, even if the optimum structure of then current point has different cabling modes to this edge, do not do any renewal rewards theory yet.Finally, the present invention is based on data statistics and find, most of degree of vertex is no more than 4 degree, and therefore, only need be optimized to 4 degree of summits just can obtain extraordinary effect, and operational efficiency is high.
5. wiring unit test
As shown in table 1, ind1-ind5 is the industrial test data set obtained from Synopsys.Rc01-rc12 is the standard testing data set around barrier problem.The wiring result that this wiring unit generates by the present invention contrasts with current 4 kinds of the most advanced wiring units.As can be seen from Table 1, compare with wiring unit 1-wiring unit 4, the present invention can obtain 19.29% respectively, the line length compression of 3.52%, 3.80%, 6.34%.
Table one connect up experimental result contrast
In addition, wiring unit of the present invention has very high treatment effeciency for practical wiring problem.Mainly contain three reasons.The first, all judgements operations in step 3 and step 4 all can realize by tabling look-up.The second, because that step one generation is a MST, therefore in step 2, most of barrier does not need all to investigate at every turn, because the square boundary frame that any two points are formed will be very little.3rd, in step 3 around the generative process of barrier anistree Steiner tree, the present invention only need investigate the limit having passed through barrier.Table 2 illustrates wiring unit of the present invention with other four kinds of wiring unit contrasts in processing speed.As can be seen from Table 2, wiring unit of the present invention is compared with other 4 kinds of wiring units, and processing speed is their 5.93 times respectively, 42.23 times, 2.35 times and 11.92 times.
To sum up, this wiring unit is all best in wiring overall length and processing speed.
Table 2 processing speed contrasts
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection domain of technical solution of the present invention.The foregoing is only preferred embodiment of the present invention, all equalizations done according to the present patent application the scope of the claims change and modify, and all should belong to covering scope of the present invention.
Claims (6)
1. the VLSI under anistree structure Steiner minimum tree, around a barrier wiring unit, is characterized in that comprising the following steps:
Step S01: according to given one group of pin coordinate position, generate one group of Delaunay triangulation, then generates by related algorithm the MST that connects all pins;
Step S02: for all limits in MST, generates the look-up table of two writing edge link informations;
Step S03: based on look-up table, is converted to one around the anistree Steiner tree of barrier by the MST that the first step generates; This anistree Steiner tree introduces some flex points on barrier to reach the object around barrier;
Step S04: share principle based on limit, calculates the optimum syndeton of each node in the anistree Steiner tree of the 3rd step generation, to reach the target maximizing and share edge lengths.
2. the VLSI under anistree structure Steiner minimum tree according to claim 1, around barrier wiring unit, is characterized in that: the related algorithm in described step S01 is Kruskal algorithm or Prim algorithm.
3. the VLSI under anistree structure Steiner minimum tree according to claim 1 is around barrier wiring unit, it is characterized in that: described look-up table comprises the look-up table that two have recorded limit link information, first table is called limit-barrier look-up table, and it records the set of the barrier that each anistree limit is passed through; Second table is called limit-line look-up table, and it have recorded the coordinate position of two points of line segments on each anistree limit.
4. the VLSI under anistree structure Steiner minimum tree according to claim 3, around barrier wiring unit, is characterized in that: the generation step of described look-up table is as follows:
Step S41: check the in MST
ibar limit
p i p j , for each cabling mode
k, calculate two points of line segments
p i s k with
s k p jstarting point coordinate and terminal point coordinate, wherein,
p i ,
p j it is pin given on two chips;
Step S42: for each barrier
bif,
p i s k or
s k p j pass through
b, then will
bjoin relative set
b ijk , wherein
s k for P
iand P
jthis tower of puppet when connecting in anistree mode that;
Step S43: establish
l ijk for
b ijk the semi-perimeter sum of inner all barriers; Calculate each
b ijk corresponding
l ijk ; Then incite somebody to action
b ijk and
l ijk join in limit-barrier look-up table;
Step S44: check each
p i s k with
s k p j if there is 45o or 135o oblique line, then it to be turned clockwise 45o around initial point, thus form a new level or vertical line segment;
Step S45: record
p i s k with
s k p j coordinate figure to limit-line look-up table;
i=
i+ 1, if
i<n, return step S41, otherwise terminate.
5. the VLSI under anistree structure Steiner minimum tree according to claim 1, around barrier wiring unit, is characterized in that: the described implementation around barrier comprises the following steps:
Step S51: check the in MST
ibar limit
p i p j if,
p i p j 0or
p i p j 1all barriers can be walked around, then elect wire laying mode as 0 or 1, investigate the i-th+1 limit; Otherwise enter step S52;
Step S52: if
p i p j 2or
p i p j 3all barriers can be walked around, enter step S53, otherwise enter step S54;
Step S53: if
l ij0 <
l ij1 , then selection mode 0 as a result;
Otherwise selection mode 1 as a result; Return step S51 and investigate next limit;
Step S54: select
l ijk be worth minimum that as net result;
Return step S51 and investigate next limit.
6. the VLSI under anistree structure Steiner minimum tree according to claim 1, around barrier wiring unit, is characterized in that: the account form of described optimum syndeton comprises the following steps:
Step S61: in the anistree Steiner tree of surface sweeping, all limits are once, add up the number of degrees of each point, and other point being connected to this point is recorded as a set;
Step S62: for each some P, if its number of degrees are
d, then 4 are enumerated
d individual wiring combination; Select around barrier and the shortest optimum structure as P of line length, and calculate the shared edge lengths of this structure;
Step S63: according to the nonincremental order of shared edge lengths of each optimum structure to sorting a little;
Step S64: apply each optimum structure put in order in original anistree Steiner tree, until the cabling mode on all limits of anistree Steiner tree was updated.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110032815A (en) * | 2019-04-19 | 2019-07-19 | 福州大学 | Octagonal steiner tree construction method based on cultural gene |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110663062A (en) * | 2017-06-02 | 2020-01-07 | 谷歌有限责任公司 | Guided traversal in triangular mesh compression |
| CN110663062B (en) * | 2017-06-02 | 2023-07-07 | 谷歌有限责任公司 | Guide traversal in triangle mesh compression |
| CN110032815A (en) * | 2019-04-19 | 2019-07-19 | 福州大学 | Octagonal steiner tree construction method based on cultural gene |
| CN110032815B (en) * | 2019-04-19 | 2022-05-10 | 福州大学 | Culture gene-based octagonal Steiner tree construction method |
| CN110795907A (en) * | 2019-09-30 | 2020-02-14 | 福州大学 | X-structure Steiner minimum tree construction method considering wiring resource relaxation |
| CN110795907B (en) * | 2019-09-30 | 2021-05-18 | 福州大学 | X-structure Steiner minimum tree construction method considering wiring resource relaxation |
| CN110689569A (en) * | 2019-12-10 | 2020-01-14 | 北京唯智佳辰科技发展有限责任公司 | Integrated circuit layout field identification and grid subdivision processing method and device |
| CN110689569B (en) * | 2019-12-10 | 2020-06-30 | 北京唯智佳辰科技发展有限责任公司 | Integrated circuit layout field identification and grid subdivision processing method and device |
| WO2021253684A1 (en) * | 2020-06-18 | 2021-12-23 | 福州大学 | Overall wiring method based on topology optimization and heuristic search |
| CN112883682A (en) * | 2021-03-15 | 2021-06-01 | 北京华大九天科技股份有限公司 | Method and apparatus for global routing of integrated circuits and storage medium |
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