CN104318025B - VLSI under anistree structure Steiner minimum trees is around barrier wiring unit - Google Patents
VLSI under anistree structure Steiner minimum trees is around barrier wiring unit Download PDFInfo
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Abstract
The present invention relates to a kind of quick VLSI based under anistree structure in integrated circuit CAD technical field around barrier Steiner minimum tree wiring units.The present invention for vlsi layout design in loose routing problem, devise it is a kind of rapidly and efficiently around barrier anise Steiner tree wiring units.According to the chip pin set given in actual industrial production, wiring unit builds an accessible Euclid minimum spanning tree first（MST）.Then, two Fast Lookup Tables on side information in MST are generated.The table can provide quick acquisition of information function for subsequent step.Next, wiring unit is by completing a kind of efficient some flex points on barrier strategy, selection barrier as the via node that barrier side is worn in MST, so that the MST of early stage is converted into one around barrier anise Steiner trees.Finally, by applying a kind of refining strategy based on shared side principle, the wiring unit will be generated final connects up result around the anistree Minimum Steiner tree of barrier.
Description
Technical field
The invention belongs to integrated circuit CAD technical field, and in particular to one kind is based on anistree structure
Quick VLSI under Steiner minimum trees is around barrier wiring unit construction problem.
Background technology
Around the anistree knot of barrier in super large-scale integration (very large scale integration, VLSI) design
Structure Steiner minimum trees (Obstacle-avoiding Octilinear Steiner Minimal Tree, OAOSMT) are asked
Topic is, in a chip surface, to give one group of pin set and one group of barrier set, utilizes 0o, 45o, 90o, and 135o gold
Belong to line and build the Steiner trees of all pins of connection, and bypass all given barriers, while so that wiring tree overall length
Spend minimum combinatorial optimization problem.
Smooth grid is breathed out since 1966 by since proposing first, right angle Steiner trees have been widely used VLSI
The various aspects of chip wiring problem.On the other hand, sharply increasing due to VLSI chip density, many restructural components are embedding
Enter into modern chips, such as IP kernel and macro block.And these components can not be crossed in wiring process.Therefore, in mistake
The more than ten years are gone, extensive research are had been obtained for around barrier right angle Steiner tree Construct questions, and achieve the achievement of many.So
And, due to right-angle structure by wiring direction limit only to can horizontal and vertical cabling, this refers to for optimizing many keys of chip
Indicate great restriction ability, such as total line length, congestion and time delay index.Therefore, current wiring technique is just stood at one ten
Word crossing, and receive the extensive concern of many research institutions.It follows that continuous with VLSI chip manufacturing process
Progressive, non-straight corner structure is developed rapidly.Particularly anistree structure, its as performance outstanding non-straight corner structure it
One, almost supported by current all production technologies.In other words, 45o and 135o oblique lines are successfully applied
In anistree routing planes.Compared to right-angle structure, due to anistree structure can great packed wiring length so that reach can be with
Reach the multinomial performance indexs such as optimization time delay, Inductance and Capacitance, congestion.There are some researches show with the Steiner tree phases under right-angle structure
Than anistree structure can compress via count 40%, total line length 20%, chip area 11% respectively.Therefore academia and industry in recent years
Boundary all starts comprehensively to have put into the research work of anistree structure.However, as far as we know, current research work is most
Remain in the routing planes stage of clear.Namely most achievement assumes initially that routing planes clear is present, and enters
And utilize the multinomial performance index including anistree structure optimization such as line length, time delay, congestion.And under anistree structure, existing
The situation of barrier, related ends almost do not have.Therefore, the Quick winding barrier wiring unit researched and developed under a kind of anistree structure just seems outstanding
To be urgent.
The content of the invention
Consider there is barrier in super large-scale integration loose routing problem it is an object of the invention to provide one kind,
The wiring unit construction problem of anistree structure Steiner minimum trees is introduced simultaneously.To optimize wiring tree overall length as target, and then cause
The many indexs such as time delay, congestion are optimized.This method considers minimum around barrier Steiner from the global angle of loose routing
The construction of tree, can obtain outstanding solution scheme within the extremely short time.
The present invention is realized using following scheme：A kind of VLSI under anistree structure Steiner minimum trees around barrier wiring unit, its
It is characterised by comprising the following steps：
Step S01：According to one group of given pin coordinate position, one group of Delaunay Triangulation is generated, is then passed through
Related algorithm generates the MST of all pins of connection；
Step S02：For all sides in MST, the look-up table of two writing edge link informations is generated；
Step S03：Based on look-up table, the MST that the first step is generated is converted to one around barrier anise Steiner trees；This eight
Angle Steiner trees introduce some flex points on barrier to reach the purpose around barrier；
Step S04：Based on side share principle, calculate the 3rd step generation anistree Steiner trees in each node most
Excellent attachment structure, to reach the target for maximizing shared edge lengths.
Further, the related algorithm in the step S01 is Kruskal algorithms or Prim algorithms.
Further, described look-up table includes two look-up tables that have recorded side link information, first table be referred to as side-
Hinder look-up table, it records the set for the barrier that each anistree side is passed through；Second table is referred to as side-line look-up table, and it is recorded
The coordinate position of two separated times section on each anistree side.
Further, the generation step of the look-up table is as follows：
Step S41：Check the in MSTiBar sideP i P j , for each cabling modek, calculate two separated time sectionsP i S k
WithS k P jStarting point coordinate and terminal point coordinate, wherein,P i ,P j For the pin given on two chips；
Step S42：For each barrierbIf,P i S k OrS k P j Pass throughb, then willbIt is added to relative set
{B ijk , whereinS k For PiAnd PjThis pseudo- tower when being connected in anistree mode that；
Step S43：IfL ijk ForB ijk Inner all barriers semi-perimeter sum；Calculate eachB ijk CorrespondingL ijk ；Then incite somebody to actionB ijk AndL ijk It is added in side-barrier look-up table；
Step S44：Check eachP i S k WithS k P j , it is if there is 45o or 135o oblique lines, then it is clockwise around origin
45o is rotated, so as to constitute a new horizontally or vertically line segment；
Step S45：RecordP i S k WithS k P j Coordinate value to side-line look-up table；i=i+ 1, ifi<n, return to step
S41, otherwise terminates.
Further, the implementation around barrier comprises the following steps：
Step S51：Check the in MSTiBar sideP i P j If,P i P j 0OrP i P j 1All barriers can be bypassed, then will
Wire laying mode elects 0 or 1 as, investigates i+1 bar side；Otherwise step S52 is entered；
Step S52：IfP i P j 2OrP i P j 3All barriers can be bypassed, into step S53, otherwise into step
S54；
Step S53：IfL ij0 < L ij1 , then selection mode 0 is as a result.Otherwise, selection mode 1 is as a result；Return
Step S51 investigates lower a line；
Step S54：SelectionL ijk That of value minimum is used as final result.Return to step S51 investigates lower a line.
Further, the calculation of the optimal attachment structure comprises the following steps：
Step S61：All sides once, count the number of degrees each put, and will be connected to the point in surface sweeping anise Steiner trees
Other points be recorded as one set；
Step S62：For each point P, if its number of degrees isd, then 4 are enumerated d Individual wiring combination；Select around barrier and line length most
The short optimum structure as P, and calculate the shared edge lengths of the structure；
Step S63：All points are ranked up according to the nonincremental order of shared edge lengths of each optimum structure；
Step S64：The optimum structure of each point of application is into original anistree Steiner trees in order, until anise
The cabling mode on all sides of Steiner trees is updated.
The wiring unit of the present invention is primarily based on one group of given pin coordinate of production problem and builds a MST.The life of the MST
Into not considering the presence of barrier, and generate based on Delaunay Triangulation, effectively raise the speed that MST is generated
Rate.Secondly, the generation of two Fast Lookup Tables can regard a kind of pretreatment to all pins and barrier as.In advance will
Subsequent step may need the information obtained to calculate and be stored in table, rather than distinguish when subsequent step is used every time
Calculate.This pretreatment strategy drastically increases execution efficiency of the wiring unit to subsequent step, because all sides and obstacle
Thing interconnection information need to only be calculated once.In addition, during MST to be converted to one around barrier anise Steiner trees, it is most of
Implementation procedure realized by tabling look-up.And for that can not get around the side of barrier, the wiring unit is crossed by choosing
Flex point on barrier reaches the purpose around barrier as the strategy of relaying.This will enable the wiring unit realizing around barrier
Under the premise of, while meeting the minimum target of the extra Steiner points chosen.Finally, the refining strategy based on shared side principle can
Sufficiently to utilize interconnection resource, with maximum sharing degree optimization wiring overall length, while the area of wiring area is reduced, and then
Improve the multinomial performance index of chip.
Brief description of the drawings
Fig. 1 is the flow chart around barrier wiring unit based on a kind of quick VLSI under anistree structure Steiner minimum trees.
Fig. 2 is four kinds of side cabling selection mode figures under anistree structure.
Fig. 3 is barrier flex point selection strategy figure.
The wiring diagram example that Fig. 4 is ultimately generated.
Embodiment
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Embodiment be described in detail.
Detail is elaborated in the following description to fully understand the present invention.But the present invention can with it is a variety of not
It is same as other manner described here to implement, those skilled in the art can do class in the case of without prejudice to intension of the present invention
Like popularization.Therefore the present invention is not limited by following public embodiment.
Present invention wiring unit first is scanned according to the coordinate position of the one group of n pin given in production problem based on line
Algorithm builds one group of Delaunay Triangulation.Because the side sum of this group of triangulation isO（n）, therefore wiring unit can be with base
In these triangulation sides, using Kruskal minimal spanning tree algorithms,O(nlogn)Time in construct one connection institute
There is the MST of pin.Next, for all sides in MST, two Fast Lookup Tables that have recorded these side link informations will be by
Generation.Wherein first table is referred to as side-barrier look-up table, and it have recorded every a line in MST and is worn when being converted to anistree cabling
The set of barrier more.Second table is referred to as side-line look-up table, and it have recorded in MST and to be converted to anise per a line and walk
The coordinate position of two separated time sections during line.The two tables can provide quick information inquiry for the follow-up work of wiring unit.
After look-up table generation, for every a line in MST, wiring unit searches out by inquiring about side-barrier look-up table and does not pass through barrier
A kind of anistree cabling mode, and by this MST while be converted directly into this it is anistree while.If all anistree cabling modes are passed through
Barrier, the wiring unit is then used as via node by some flex points for selecting to be crossed on barrier, so as to reach around barrier
Purpose.Finally, for above generating around barrier anise Steiner trees, the wiring unit is based on side and shares principle, each by calculating
The optimal interconnection structure of individual node, that is, maximize shared edge lengths, so as to generate final around the minimum anise Steiner tree cloth of barrier
Knot fruit.
It is specifically divided into following four step：
1. according to one group of given pin coordinate position, one group of Delaunay Triangulation is generated, is then applied
Kruskal minimal spanning tree algorithms, generate the MST of all pins of connection；
2. for all sides in MST, generate the look-up table of two writing edge link informations；
3. based on look-up table, the MST that the first step is generated is converted to one around barrier anise Steiner trees.The anise
Steiner trees introduce some flex points on barrier to reach the purpose around barrier；
4. sharing principle based on side, the optimal connection of each node in the anistree Steiner trees of the 3rd step generation is calculated
Structure, to reach the target for maximizing shared edge lengths.
In order to allow those skilled in the art to be better understood from the present invention, below in conjunction with the accompanying drawings and experimental result the present invention is done into
One step explanation：
1. defining 1 (pseudo- Steiner points) assumes the tie point in addition to pin, it is referred to as puppet Steiner points.In Fig. 2
S0, S1, S2And S3It is that Steiner points are included in pseudo- Steiner points, pseudo- Steiner points.
2 (0 selections) are defined as shown in Fig. 2 (a), p1(x 1 ,y 1 ) and p2(x 2 ,y 2 ) be side L two end points, whereinx 1
<x 2 .Shown in selection such as Fig. 2 (b) of the corresponding pseudo- Steiner points of side L, from p1First draw Manhattan side to s0, then by s0Draw Fei Manha
Side is to p2..Then it is referred to as 0 selection.
Define shown in 3 (1 selection) Fig. 2 (c), from p1First draw non-Manhattan structure side to s1, then from s1Draw Manhattan knot
Structure side is to p2, then referred to as 1 selection.
Define shown in 4 (2 selection) Fig. 2 (d), from p1First draw vertical edge to s2, then by s2Draw horizontal sides to p2, then it is referred to as
2 selections.
Define shown in 5 (3 selection) Fig. 2 (e), from p1First draw horizontal sides to s3, then by s3Draw vertical edge to p2, then it is referred to as
3 selections.
2.MST generation strategies：
In accessible plane, there are many MST developing algorithms.In order to improve formation efficiency, the wiring unit employs one kind
Construction strategy based on triangulation.It is primarily based on given one group of pin Coordinate generation, one group of triangulation.Then Prim
Algorithm or Kruskal algorithms can beO（nlogn）One MST of generation in time.
3. look-up table is generated：
Under anistree plane, the wiring unit is directed to all sides in MST, and generation two have recorded the lookup of side link information
Table.First table is referred to as side-barrier look-up table, and it records the set for the barrier that each anistree side is passed through.Second table is referred to as
Side-line look-up table, it have recorded the coordinate position of two separated times section on each anistree side.
Assuming that problem givennIndividual pin, then MST includen- 1 side.Because each edge has four kinds of anistree cabling modes,
Therefore one 4* is co-existed in（n-1）Bar anise side.For each anistree sideP i P j k（P i ,P j For two pins,kFor cabling side
Formula）, present invention calculatingP i P j kAll barriers for passing through and be recorded as a setB ijk , then willL ijk Value set
For the semi-perimeter sum of these barriers.All 4*（n-1）GroupB ijk AndL ijk Constitute final side-barrier look-up table.In addition
Each anistree sideP i P j kIt is made up of two separated time sections（P i S k ,S k P j ）, the end points of the invention that this two separated times sections are recorded respectively
Coordinate.It is all while these information constitute final while-line look-up table.The detailed step of look-up table generation is as follows, initializationi
=1,
(1) the in MST is checkediBar sideP i P j , for each cabling modek, calculate two separated time sectionsP i S k WithS k P j
Starting point coordinate and terminal point coordinate.
(2) for each barrierbIf,P i S k OrS k P j Pass throughb, then willbBe added to relative setB ijk }。
(3) calculate eachB ijk CorrespondingL ijk .Then incite somebody to actionB ijk AndL ijk It is added in side-barrier look-up table.
(4) each is checkedP i S k WithS k P j , if there is 45o or 135o oblique lines, then it is turned clockwise 45 around origin
O, so as to constitute a new horizontally or vertically line segment.
(5) recordP i S k WithS k P j Coordinate value to side-line look-up table.i=i+ 1, ifi<n, return（1）, otherwise tie
Beam.
Here have be noted that for each barrier in second step at 2 pointsb, the present invention investigates it, and and if only ifb
There is at least one flex point to drop intoP i WithP j The square boundary inframe of composition.Secondly, if there is 45o or 135o oblique lines, the present invention
（4）Step is rotated to be horizontally or vertically line, and records the coordinate of new line segment.This subsequent step can be facilitated local and
The calculating of overall line length, because overlapping 45o or 135o oblique lines can be easily identified out in the case where not changing length
Come.
4. around barrier strategy：In this step, the MST of early stage generation will be rapidly converted into an anise Steiner first
Tree.The present invention checks every a line in MSTP i P j .By tabling look-up, if anistree sideP i P j 0OrP i P j 1It can get around all
Barrier, then directly willP i P j Wire laying mode selection be 0 or 1 mode.Else ifP i P j 2OrP i P j 3All barriers can be bypassed
Hinder thing, it is of the invention then according to Lij0And Lij1Size select.IfL ij0 < L ij1 , then selection mode 0 is as a result.It is no
Then, selection mode 1 is as a result.It is of the invention then select if wire laying mode has all passed through barrier in 4L ijk Value minimum
That is used as wire laying mode.Detailed step is as follows, initializationi=1,
（1）Check the in MSTiBar sideP i P j If,P i P j 0OrP i P j 1All barriers can be bypassed, then by wiring side
Formula elects 0 or 1 as, investigates i+1 bar side.Otherwise enter（2）.
（2）IfP i P j 2OrP i P j 3All barriers can be bypassed, are entered（3）, otherwise into (4).
（3）IfL ij0 < L ij1 , then selection mode 0 is as a result.Otherwise, selection mode 1 is as a result.Return（1）Examine
Examine lower a line.
（4）SelectionL ijk That of value minimum is used as final result.Return（1）Investigate lower a line.
Obviously, barrier has been passed through on some sides in anistree Steiner trees.Therefore the present invention proposes one kind around barrier method
To help these sides to bypass all barriers.For every a line in anistree Steiner treesP i P j k（kIt is to determine herein
's）If he has passed through barrier, the present invention directly deletes this edge.Then to barrier setB ijk According toP i To barrier
The order of thing centre distance non-decreasing is hindered to sort.Next, setting starting pointS=P i .The present invention connects to one, barrier after sequence
One investigation, chooses a flex point from current barrier every timeCAs via node, hereCIt is that straight line is arrived in four flex pointsSP j Closest that.Then the present invention calculates sideSCLink information, and be added in two look-up tables.
S is connected toCAfterwards, the present invention willCIt is set to newS, and continue to investigate next barrier, to the last selection
Flex point is connected toP j 。
This may be performed for several times around barrier method, untill all sides bypass all barriers.Fig. 3 is one
Around the example of barrier method.Fig. 3 (a) is original side P1P23, it has passed through barrier B1And B2.After being deleted on original side, this hair
It is bright to primarily look at barrier B1, because it is apart from P1Closer to.Due to C1It is B1On apart from straight line P1P2Nearest flex point, thus it is selected
For via node, and it is connected to P1（Fig. 3 (b)）.Then the present invention investigates B2, in Fig. 3 (c), C2It is connected to C1Because it
It is B2On apart from straight line C1P2A nearest flex point.Finally, C2It is connected to P2In Fig. 3 (d).Note the connection on all new sides
Information should be all added into look-up table, because they are useful for follow-up refinement step.
5. refining strategy：In fact, for any one point in anistree Steiner trees, all there is an optimal connection
Structure.A kind of refining strategy based on shared side principle is proposed based on this present invention.By to all in this anistree smooth tree
Side run-down, the present invention obtains the number of degrees of each point first, and records the other point sets for being connected to each point.So
Afterwards for each point P, it is assumed that its number of degrees isd, the present invention enumerates all 4 d Kind of cabling combination, and select and can bypass institute
Have barrier and line length most short that as the point optimum structure.Next, the present invention, which calculates each, puts optimal knot
The length on side is shared in structure, and all points are ranked up according to the nonincremental order of the length.Finally according to the point after sequence
Sequentially, the optimum structure of each point is applied on original anistree Steiner trees, so as to obtain final wiring tree.In detail
Thin step is as follows：
（1）All sides once, count the number of degrees each put in surface sweeping anise Steiner trees, and by be connected to the point its
It, which puts, is recorded as a set.
（2）For each point P, if its number of degrees isd, then 4 are enumerated d Individual wiring combination.Select around barrier and line length is most short
One optimum structure as P, and calculate the shared edge lengths of the structure.
（3）All points are ranked up according to the nonincremental order of shared edge lengths of each optimum structure.
（4）The optimum structure of each point of application is into original anistree Steiner trees in order, until anistree Steiner
The cabling mode on all sides of tree is updated.
Have require emphasis at 3 points.First, in step（2）In, judge whether a wiring combination can directly pass through around barrier
Table look-up to realize, thus it is very efficient.Secondly, in step（4）In, if certain the side cabling side of original anistree Steiner trees
Formula is updated, even if then the optimum structure of current point has different cabling modes to this edge, any renewal is not done yet
Operation.Finally, the present invention is had found based on data statistics, and most of degree of vertex is no more than 4 degree, therefore, only need to be optimized to 4 degree
Summit just can obtain extraordinary effect, and operational efficiency is high.
5. wiring unit is tested
As shown in table 1, ind1-ind5 is the industrial test data set obtained from Synopsys.Rc01-rc12 is asked around barrier
The standard testing data set of topic.The wiring result that the present invention generates the wiring unit is entered with presently most advanced 4 kinds of wiring units
Row contrast.As it can be seen from table 1 compared with wiring unit 1- wiring units 4, the present invention can obtain 19.29%, 3.52% respectively,
3.80%, 6.34% line length compression.
The wiring experimental result contrast of table one
In addition, the wiring unit of the present invention has very high treatment effeciency for practical wiring problem.Mainly there are three reasons.
First, all judgements operation in step 3 and step 4 can be realized by tabling look-up.Second, because step one generation is
Most of barriers are not required to investigate every time in one MST, therefore step 2, because the rectangular bounding box that any two point is constituted
To be very small.3rd, for the generating process in step 3 around barrier anise Steiner trees, the present invention need to only be investigated and passed through
The side of barrier.Table 2 illustrates the wiring unit of the present invention with other contrasts of four kinds of wiring units in terms of processing speed.From table 2
As can be seen that the wiring unit of the present invention is compared with other 4 kinds of wiring units, processing speed is their 5.93 times, 42.23 respectively
Times, 2.35 times and 11.92 times.
To sum up, the wiring unit is optimal in terms of wiring overall length and processing speed.
The processing speed of table 2 is contrasted
Although the present invention is disclosed as above with preferred embodiment, it is not for limiting the present invention, any this area
Technical staff without departing from the spirit and scope of the present invention, may be by the methods and techniques content of the disclosure above to this hair
Bright technical scheme makes possible variation and modification, therefore, every content without departing from technical solution of the present invention, according to the present invention
Any simple modifications, equivalents, and modifications made to above example of technical spirit, belong to technical solution of the present invention
Protection domain.It the foregoing is only presently preferred embodiments of the present invention, all impartial changes done according to scope of the present invention patent
Change and modify, should all belong to the covering scope of the present invention.
Claims (3)
1. the VLSI under a kind of anistree structure Steiner minimum trees is around barrier wiring unit, it is characterised in that comprise the following steps：
Step S01：According to one group of given pin coordinate position, one group of Delaunay Triangulation is generated, then passes through correlation
Algorithm generates the MST of all pins of connection；
Step S02：For all sides in MST, the look-up table of two writing edge link informations is generated；
Step S03：Based on look-up table, the MST that the first step is generated is converted to one around barrier anise Steiner trees；The anise
Steiner trees introduce some flex points on barrier to reach the purpose around barrier；
Step S04：Principle is shared based on side, the optimal company of each node in the anistree Steiner trees of the 3rd step generation is calculated
Binding structure, to reach the target for maximizing shared edge lengths；
Related algorithm in the step S01 is Kruskal algorithms or Prim algorithms；
Described look-up table includes two look-up tables that have recorded side link information, and first table is referred to as side-barrier look-up table, and it remembers
The set for the barrier that the anistree side of each of record is passed through；Second table is referred to as side-line look-up table, and it have recorded each anistree side
Two separated times section coordinate position；
The calculation of the optimal attachment structure comprises the following steps：
Step S041：Scan all sides in anise Steiner trees and once, count the number of degrees each put, and the point will be connected to
Other points are recorded as a set；
Step S042：For each point P, if its number of degrees is d, 4 are enumerateddIndividual wiring combination；Select around barrier and line length is most short
One optimum structure as P, and calculate the shared edge lengths of the structure；
Step S043：All points are ranked up according to the nonincremental order of shared edge lengths of each optimum structure；
Step S044：The optimum structure of each point of application is into original anistree Steiner trees in order, until anise
The cabling mode on all sides of Steiner trees is updated.
2. the VLSI under anistree structure Steiner minimum trees according to claim 1 is around barrier wiring unit, it is characterised in that：
The generation step of the look-up table is as follows：
Step S021：Check i-th side P in MSTiPj, for each cabling mode k, calculate two separated time section PiSkWith
SkPjStarting point coordinate and terminal point coordinate, wherein, Pi, PjFor the pin given on two chips；
Step S022：For each barrier b, if PiSkOr SkPjB has been passed through, then b has been added to relative set { Bijk,
Wherein SkFor PiAnd PjThis pseudo- tower when being connected in anistree mode that；
Step S023：If LijkFor { BijkInner all barriers semi-perimeter sum；Calculate each { BijkCorresponding Lijk；So
Afterwards by { BijkAnd LijkIt is added in side-barrier look-up table；
Step S024：Check each PiSkAnd SkPj, if there is 45 ° or 135 ° of oblique lines, then it is turned clockwise around origin
45 °, so as to constitute a new horizontally or vertically line segment；
Step S025：Record PiSkAnd SkPjCoordinate value to side-line look-up table；I=i+1, if i<N, return to step S021, it is no
Then terminate.
3. the VLSI under anistree structure Steiner minimum trees according to claim 1 is around barrier wiring unit, it is characterised in that：
The implementation around barrier comprises the following steps：
Step S031：Check i-th side P in MSTiPjIf, PiPj0 or PiPj1 can bypass all barriers, then will wiring
Mode elects 0 or 1 as, investigates i+1 bar side；Otherwise step S032 is entered；
Step S032：If PiPj2 or PiPj3 can bypass all barriers, into step S033, otherwise into step S034；
Step S033：If Lij0<Lij1, then selection mode 0 is as a result, otherwise, selection mode 1 is as a result；Return to step
S031 investigates lower a line；
Step S034：Select LijkThat of value minimum is used as final result, and return to step S031 investigates lower a line.
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| CN110032815B (en) * | 2019-04-19 | 2022-05-10 | 福州大学 | Culture gene-based octagonal Steiner tree construction method |
| CN110795907B (en) * | 2019-09-30 | 2021-05-18 | 福州大学 | X-structure Steiner minimum tree construction method considering wiring resource relaxation |
| CN110689569B (en) * | 2019-12-10 | 2020-06-30 | 北京唯智佳辰科技发展有限责任公司 | Integrated circuit layout field identification and grid subdivision processing method and device |
| CN111814420B (en) * | 2020-06-18 | 2022-07-08 | 福州大学 | Overall wiring method based on topological optimization and heuristic search |
| CN112883682B (en) * | 2021-03-15 | 2022-04-29 | 北京华大九天科技股份有限公司 | Method and apparatus for global routing of integrated circuits and storage medium |
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