CN114386356A - Wiring method, device, equipment and storage medium for chip design - Google Patents

Wiring method, device, equipment and storage medium for chip design Download PDF

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Publication number
CN114386356A
CN114386356A CN202011112832.4A CN202011112832A CN114386356A CN 114386356 A CN114386356 A CN 114386356A CN 202011112832 A CN202011112832 A CN 202011112832A CN 114386356 A CN114386356 A CN 114386356A
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China
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line segment
wiring
target
end point
initial line
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陈越政
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Guangdong Oppo Mobile Telecommunications Corp Ltd
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Guangdong Oppo Mobile Telecommunications Corp Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Architecture (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The embodiment of the application discloses a wiring method, a wiring device, equipment and a storage medium for chip design; wherein the method comprises the following steps: wiring on the wiring layer according to the wiring information of wiring required by chip design to obtain an initial line segment; judging whether the routing space requirement of the routing layer is met between the initial line segment and the adjacent line segment to obtain a judgment result; and automatically processing the initial line segment according to the judgment result until a target line segment meeting the wiring distance requirement is obtained.

Description

Wiring method, device, equipment and storage medium for chip design
Technical Field
The embodiment of the application relates to a chip design technology, and relates to a wiring method, a wiring device, wiring equipment and a wiring storage medium for chip design.
Background
Some important clock signals always exist in the chip design process, Non-default routing rule (NDR) needs to be set in the chip rear end design process, signal transmission stability is guaranteed and wiring delay is reduced by increasing wiring width and wiring distance, and chip performance is improved. However, these important signal lines, which previously required the engineer to manually Design them, have also begun to intervene in the Electronic Design Automation (EDA) tool in recent years to solve this problem.
The method has the defect of long time consumption for manual wiring of engineers. Although the quality of the manual wiring by an engineer is guaranteed, the time taken for the manual wiring is long, and particularly in the case that the number of NDR wirings is hundreds or thousands, the design time may be too long, the chip flow delay may be delayed and the like in the chip design field with extremely high competition, which is very unacceptable.
For the existing EDA tool routing scheme, although the problem that the manual routing of engineers needs a long time is solved, the NDR routing work is handled by the tools, which is greatly different from the conventional normal routing design scheme, so that the metal wire segments customized by the tools may not meet the chip design requirements. This requires later engineers to manually correct these segments, which results in still longer chip design cycles.
Disclosure of Invention
In view of this, the wiring method, apparatus, device, and storage medium for chip Design provided in the embodiments of the present application can automatically obtain a target line segment without Design Rule Check (DRC) violation, that is, obtain a target line segment meeting the requirement of wiring pitch, so that later manual correction is not needed, and the chip Design period is further shortened. The wiring method, device, equipment and storage medium of the chip design provided by the embodiment of the application are realized as follows:
the wiring method for chip design provided by the embodiment of the application comprises the following steps: wiring on the wiring layer according to the wiring information of wiring required by chip design to obtain an initial line segment; judging whether the routing space requirement of the routing layer is met between the initial line segment and the adjacent line segment to obtain a judgment result; and automatically processing the initial line segment according to the judgment result until a target line segment meeting the wiring distance requirement is obtained.
The embodiment of the application provides a wiring arrangement of chip design, includes: the wiring module is used for wiring on the wiring layer according to the wiring information of wiring required by chip design to obtain an initial line segment; the judging module is used for judging whether the wiring space requirement of the wiring layer is met between the initial line segment and the adjacent line segment or not to obtain a judging result; and the processing module is used for automatically processing the initial line segment according to the judgment result until a target line segment meeting the wiring distance requirement is obtained.
The electronic device provided by the embodiment of the application comprises a memory and a processor, wherein the memory stores a computer program capable of running on the processor, and the processor executes the program to realize the wiring method of the chip design in the embodiment of the application.
A computer-readable storage medium provided in an embodiment of the present application stores thereon a computer program, and the computer program, when executed by a processor, implements a wiring method of a chip design according to an embodiment of the present application.
In the embodiment of the application, a wiring method for chip design is provided, wiring is performed on a wiring layer according to wiring information of wiring required by chip design, and after an initial line segment is obtained, a next metal line segment is not continuously generated, but whether the distance between the initial line segment and a neighboring line segment meets the wiring distance requirement is automatically checked; and then, automatically processing the initial line segment according to the detection result until a target line segment meeting the wiring distance requirement is obtained. That is, the wiring method of the chip design can automatically generate a target line segment meeting the wiring distance requirement; therefore, the target line segment which does not meet the requirement of the wiring distance is prevented from being introduced, so that an engineer does not need to manually correct the target line segment in the later period, and the chip design period is shortened.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application.
FIG. 1 is a schematic diagram of wiring for each layer of a chip;
fig. 2 is a schematic implementation flow diagram of a wiring method of a chip design provided in an embodiment of the present application;
fig. 3 is a schematic implementation flow diagram of a wiring method of a chip design provided in an embodiment of the present application;
fig. 4 is a schematic diagram of determining an available routing layer according to an embodiment of the present application;
FIG. 5 is a schematic diagram of the shape of an initial line segment provided by an embodiment of the present application;
FIG. 6 is a schematic diagram of an enclosure provided by an embodiment of the present application;
FIG. 7 is a schematic diagram of updating a previously obtained target line segment according to an embodiment of the present application;
FIG. 8 is a schematic diagram of an intersection of line segments provided in an embodiment of the present application;
fig. 9 is a schematic implementation flow diagram of a wiring method of a chip design provided in an embodiment of the present application;
FIG. 10 is a schematic diagram of a Manhattan link provided in accordance with an embodiment of the present application;
fig. 11 is a schematic view of coordinates of a start point and an end point of a to-be-connected line provided in the embodiment of the present application;
FIG. 12 is a schematic diagram of a preliminary layout shape of a wiring according to an embodiment of the present application;
FIG. 13 is a schematic diagram of a DRC check of routing provided by an embodiment of the present application;
FIG. 14 is a schematic diagram of metalB segment shape provided by the embodiments of the present application;
FIG. 15 is a schematic diagram of metalC causing the DRC of metalB provided by the embodiment of the present application;
FIG. 16 is a diagram of new metalB shape provided by the present application embodiment to solve the MetalC introduced DRC problem and determine the metalA shape;
FIG. 17 is a diagram illustrating a result of completing a wiring shape generating operation according to an embodiment of the present application;
FIG. 18 is a schematic diagram of a via add-on routing provided in an embodiment of the present application;
FIG. 19 is a schematic structural diagram of a wiring device of a chip design according to an embodiment of the present application;
fig. 20 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, specific technical solutions of the present application will be described in further detail below with reference to the accompanying drawings in the embodiments of the present application. The following examples are intended to illustrate the present application but are not intended to limit the scope of the present application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the application.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.
It should be noted that the terms "first \ second \ third" are used herein to distinguish similar or different objects and do not denote a particular order or importance to the objects, and it should be understood that "first \ second \ third" may be interchanged with a particular order or sequence where permissible to enable embodiments of the present application described herein to be practiced otherwise than as shown or described herein.
In chip design, the wiring metal layer usually has 4 to 15 layers, but is not limited thereto. The wiring directions of the same layer are consistent, and the wiring directions of two adjacent layers are vertical. For example, as shown in FIG. 1, the wiring direction of the Mn-th layer 102 is the longitudinal direction, and the wiring directions of the adjacent upper and lower two layers, i.e., the Mn-1-th layer 101 and the Mn + 1-th layer 103, are the lateral directions. This is the fundamental rule for wiring in chip design.
The inventor finds out in the process of research that: although EDA and other tools are used for chip design, DRC violations are often problematic as a result of the wiring made by these tools. For example, some of the designed line segments cannot meet the routing pitch requirements. Therefore, engineers need to manually correct the chip one by one in the later period, and the problem of long chip design period is still not effectively improved.
In view of this, the embodiments of the present application provide a wiring method for chip design, which can automatically complete wiring at one time, and the wiring result does not have the DRC violation problem, so that an engineer does not need to correct the wiring result at a later stage, thereby effectively improving the problem of a long chip design period.
The method can be applied to electronic equipment which can be a mobile phone, a tablet computer, a notebook computer or a desktop computer and is provided with information processing capability. The functions realized by the wiring method of the chip design can be realized by calling program codes through a processor in the electronic equipment, and the program codes can be saved in a computer storage medium. It is seen that the electronic device includes at least a processor and a storage medium.
Fig. 2 is a schematic implementation flow diagram of a wiring method of a chip design provided in an embodiment of the present application, and as shown in fig. 2, the method may include the following steps 201 to 203:
step 201, according to the connection information of the wiring required by the chip design, wiring is performed on the wiring layer to obtain an initial line segment.
The link information may include one or more sets of coordinates of start and end points to be linked. In some embodiments, the electronic device may implement step 201 through steps 301 to 303 of the following embodiments.
Step 202, judging whether the routing distance requirement of the routing layer is met between the initial line segment and the adjacent line segment, and obtaining a judgment result.
It is understood that a neighbor line segment refers to an existing metal line segment that is immediately adjacent to the original line segment on the same routing layer. That is, there are no other line segments between the neighbor line segment and the original line segment.
The corresponding routing pitch requirements may be the same or different for different routing layers. In some embodiments, the electronic device may obtain, by using a table lookup method, a routing distance requirement corresponding to a routing layer in which the initial line segment is located according to the identifier of the routing layer.
In some embodiments, if the distance between the initial line segment and any one of the neighboring line segments does not meet the requirement of the wiring distance, the obtained judgment result is that the requirement of the wiring distance is not met; and if the distance between the initial line segment and each adjacent line segment meets the requirement of the wiring distance, the obtained judgment result is that the requirement of the wiring distance is met.
And 203, automatically processing the initial line segment according to the judgment result until a target line segment meeting the wiring distance requirement is obtained.
Different judgment results, the way of automatically processing the initial line segment is different. For example, when the determination result is that the wiring pitch requirement is not satisfied, the electronic device may process the initial line segment through steps 306 and 307 of the following embodiments until the initial line segment (i.e., the target line segment) satisfying the wiring pitch requirement is obtained. For another example, when the determination result is that the wiring pitch requirement is satisfied, the electronic device may directly determine the initial line segment as the target line segment. Thus, the electronic device may repeat the above steps 201 to 203 until the wiring requirement required by the chip design is completed, i.e. the connection between the start point and the end point of each group is completed.
In the embodiment of the application, a wiring method for chip design is provided, wiring is performed on a wiring layer according to wiring information of wiring required by chip design, and after an initial line segment is obtained, a next metal line segment is not continuously generated, but whether the distance between the initial line segment and a neighboring line segment meets the wiring distance requirement is automatically checked; and then, automatically processing the initial line segment according to the detection result until a target line segment meeting the wiring distance requirement is obtained. That is, the wiring method of the chip design can automatically generate a target line segment meeting the wiring distance requirement; therefore, the target line segment which does not meet the requirement of the wiring distance is prevented from being introduced, so that an engineer does not need to manually correct the target line segment in the later period, and the chip design period is shortened.
Fig. 3 is a schematic flow chart illustrating an implementation of the wiring method for chip design provided in the embodiment of the present application, and as shown in fig. 3, the method may include the following steps 301 to 314:
step 301, obtaining coordinates of a starting point and a terminal point of a current wire to be connected from wire connection information of a wire required by chip design;
step 302, determining an available wiring layer according to the coordinates of the starting point and the coordinates of the end point.
The available wiring layers are wiring layers which can meet the requirement of connecting wires from a starting point to an end point. For example, as shown in fig. 4, assuming that the coordinates of the start point are (x1, y1), the coordinates of the end point are (x2, y2), x1 < x2, y1 < y2, and the wiring layer 401 and the wiring layer 402 are adjacent to each other, the wiring pitch requirements of both are s. At the start and stop points, the wiring may be routed in the lateral direction on the wiring layer 401 or in the vertical direction on the wiring layer 402. However, if wiring is routed laterally from the starting point (x1, y1) to (x2, y1), since the metal line segment 403 already exists between (x1, y1) and (x2, y1), it is obvious that the line segments from (x1, y1) to (x2, y1) cannot be reproduced, and longitudinal wiring is required at s from the metal line segment 403, which increases the wiring complexity and the number of vias between the starting point and the end point. If wiring is routed longitudinally to (x1, y2) at the starting point (x1, y1), there is no existing metal line segment between (x1, y1) and (x1, y2), nor other devices. Thus, wiring layer 402 may be made available as a wiring layer. This is, of course, only an example and should not be taken as limiting the scope of protection of the available routing layers.
For another example, assuming that the coordinates of the start point are (x1, y1) and the coordinates of the end point are (x2, y1), the wiring layer 401 can be used as an available wiring layer; similarly, assuming that the coordinates of the start point are (x1, y1) and the coordinates of the end point are (x1, y2), the wiring layer 402 can be made an available wiring layer.
Step 303, according to the coordinates of the starting point, the coordinates of the end point and the requirement of the routing width of the available routing layer, routing is performed on the available routing layer to obtain an initial line segment.
It can be understood that in the embodiment of the present application, the wiring is performed on the available wiring layer, so that the introduction of a new wiring problem can be avoided, thereby increasing the wiring speed and shortening the chip design cycle.
The segments of the wiring have a certain width. The wiring width requirements of different wiring levels may be the same or different. In some embodiments, the electronic device may obtain the routing width requirement of the routing layer by a table lookup method according to the identifier of the available routing layer.
In some embodiments, if the available routing layers are lateral routes, the length of the initial line segment may be the distance between the abscissa of the starting point and the abscissa of the ending point. In other embodiments, if the available routing layers are vertical routes, the length of the initial line segment may be the distance between the ordinate of the starting point and the ordinate of the ending point. As shown in fig. 5, the coordinates of the start point are (x1, y1), the coordinates of the end point are (x2, y2), x1 < x2, y1 < y2, and the wiring widths of the wiring layer 501 of the horizontal line wiring and the wiring layer 502 of the vertical line wiring are all w. Then, as shown in fig. 5, the initial line segment may be either line segment 503 or line segment 504.
It is understood that the length of the initial line segment is designed as the distance between the abscissa of the starting point and the abscissa of the end point, or as the distance between the ordinate of the starting point and the ordinate of the end point; the wiring rule is simple, and the number of metal line segments for connecting the starting point and the end point can be reduced as much as possible, so that the wiring speed is increased, and the chip design period is shortened.
Step 304, judging whether the routing space requirement of the available routing layer is met between the initial line segment and the adjacent line segment; if so, go to step 305; otherwise, go to step 306;
in some embodiments, the electronic device may implement step 304 by: determining surrounding areas of the initial line segments according to the wiring interval requirement, wherein the interval between each boundary of the surrounding areas and the corresponding parallel boundary of the initial line segments meets the wiring interval requirement; and judging whether a neighbor line segment crosses the boundary of the surrounding area or not to obtain the judgment result. For example, if no neighbor line segment crosses the boundary of the surrounding area, the obtained judgment result is that the routing distance requirement is met between the initial line segment and each neighbor line segment; similarly, if a neighbor line segment crosses the boundary of the surrounding area, the obtained judgment result indicates that the requirement of the wiring distance between the initial line segment and the neighbor line segment is not met.
For example, assume that the wiring pitch is required to be s or more in the pitch between two adjacent line segments. As shown in fig. 6, the surrounding area of the initial line segment 601 (shaded area in the figure) is 602, the distance between each boundary of the surrounding area 602 and the corresponding parallel boundary of the initial line segment is equal to s, and the line segment 603 is found to cross the boundary of the surrounding area 602 by judgment, so that it is determined that the routing distance requirement between the initial line segment and the neighboring line segment is not satisfied.
It should be noted that, for any newly generated line segment, the electronic device can determine whether the line segment and its neighboring line segment satisfy the requirement of the routing distance according to the above method.
Step 305, determining the initial line segment as a target line segment meeting the wiring distance requirement; then step 308 is entered;
step 306, automatically generating a new initial line segment.
For example, in some embodiments, the electronic device may implement step 306 through steps 908 through 910 of the following embodiments.
Step 307, automatically processing the new initial line segment according to a judgment result of whether the new initial line segment and the corresponding neighbor line segment meet the wiring distance requirement until a target line segment meeting the wiring distance requirement is obtained; step 308 is then entered.
It can be understood that, in the embodiment of the present application, if an initial line segment does not meet the requirement of the routing distance, a new initial line segment is automatically generated, whether the new initial line segment and a corresponding neighboring line segment meet the requirement of the routing distance is automatically determined, and the new initial line segment is automatically processed based on the requirement until a target line segment meeting the requirement of the routing distance is obtained; therefore, the DRC violation problem of each line segment obtained by automatic drawing of the electronic equipment can be avoided, and an engineer does not need to correct the line segment manually in the later period, so that the chip design period is shortened.
It should be noted that, in the embodiment of the present application, the method for automatically processing each generated line segment is the same, and finally, the target line segment meeting the requirement of the wiring pitch is obtained.
Step 308, determining whether the end point of the target line segment comprises the end point; if so, go to step 309; otherwise, step 310 is performed.
It is understood that, whether the end point of the currently obtained target line segment includes the end point is determined, so as to determine whether to continue to complete the wiring task between the current start point and the end point or to execute the wiring task between the start point and the end point of the next line to be connected. If the end point of the currently obtained target line segment comprises an end point, adding through holes to the two ends of the target line segment to complete the wiring task of the current connecting line; otherwise, the following step 310 is performed.
And 309, adding through holes at two ends of the target line segment, thereby completing the wiring task of the current to-be-wired line.
It can be understood that after the electronic device completes the wiring task of the current wire to be connected, the electronic device continues to complete the wiring task of the next wire to be connected according to the wiring information and the wiring method of the chip design described in the embodiment of the present application until the starting point and the ending point of each group are connected by the metal wire segment.
And 310, taking the coordinate of the end point as the position of the end point, and generating a vertical line segment of the target line segment on another available wiring layer.
It can be understood that, in the process of connecting the starting point and the end point through the wiring, the next line segment is planned by taking the coordinate of the end point as the end point position, so that the number of times of wiring in the process can be reduced as much as possible, and the chip design period is shortened.
And 311, processing the vertical line segment according to a judgment result of whether the wiring distance requirement of the other available wiring layer is met between the vertical line segment and the corresponding neighbor line segment until a target line segment meeting the wiring distance requirement of the other available wiring layer is obtained.
It is understood that the corresponding neighbor line segments in step 311 refer to neighbor line segments of the vertical line segment. As mentioned above, in the wiring process of chip design, the same method is used to automatically process each newly generated line segment, and finally the target line segment satisfying the wiring pitch requirement is obtained.
And step 312, updating the target line segment obtained at the previous time according to the target line segment obtained at present, so that the updated target line segment and the target line segment obtained at present are in an L shape.
It can be understood that the previously obtained target line segment and the currently obtained target line segment are perpendicular to each other, and the previously obtained target line segment is updated along with the currently obtained target line segment, so that the two perpendicular line segments are ensured to be always in an L shape. In this way, each line segment finally used for connecting the starting point and the end point has no redundant part, so that the total length of the connecting line between the two points is shortened while the wiring quality is improved.
For example, as shown in fig. 7, assume that the currently obtained target line segment is 701, the previously obtained target line segment is 702, and before the target line segment 702 is updated, the two line segments are T-shaped; after the update, both segments are L-shaped, and it is apparent that the length of the target segment 702 is shortened compared to before the update.
Step 313, determining whether an endpoint of a target line segment of the another available routing layer includes the endpoint; if so, go to step 314; otherwise, repeating the above steps 310 to 313 until a target line segment including the end point is obtained, and entering step 314.
It should be noted that, according to the target line segment of the other available wiring layer (i.e., the currently obtained target line segment), the target line segment of the available wiring layer (i.e., the previously obtained target line segment) is updated, so that the updated target line segment and the target line segment of the other available wiring layer are in an L shape. The execution sequence of the step (i.e., step 312) and the step 313 may be various, and the execution sequence of the two steps is not limited in the present application, and the step 312 may be executed first, the step 313 may be executed first, or the two steps may be executed in parallel.
And step 314, adding through holes at the nodes of the obtained target line segments to complete the connection between the starting point and the end point.
It should be understood that the term "node" refers to a point of intersection (meeting point) of two mutually perpendicular line segments. For example, as shown in fig. 8, target line segments 803 to 805 are needed for communication between a starting point 801 and an end point 802, wherein the target line segment 803 and the target line segment 804 are perpendicular to each other, and an intersection point is 811; the target line segment 804 and the target line segment 805 are perpendicular to each other, and the intersection point is 812; then, the electronic device may add vias at the intersections 811 and 812, respectively, to connect the target line segment 803 with the target line segment 804 and to connect the target line segment 804 with the target line segment 805.
Fig. 9 is a schematic flow chart illustrating an implementation of the wiring method for chip design provided in the embodiment of the present application, and as shown in fig. 9, the method may include the following steps 901 to 911:
step 901, obtaining coordinates of a starting point and an end point of a current wire to be connected from wire connecting information required by chip design;
step 902, determining an available wiring layer according to the coordinates of the starting point and the coordinates of the end point;
step 903, determining a manhattan connecting line with the least turning between the starting point and the end point according to the coordinates of the starting point and the end point;
and 904, determining the rectangular area determined by the Manhattan connecting line as a target area.
Before describing the manhattan link, the manhattan is a very busy block, a high building is erected, streets are vertical in a transverse screen mode, as shown in fig. 10, the site A reaches the site B, a straight path is not available, a detour is needed, and the detour needs to be horizontally and vertically carried out to reach the site B. For example, the paths from the point a to the point B include paths a, B, c, and d shown in fig. 10, and it can be seen that the paths a and d have the least turns and have only one right angle, so that the two paths are manhattan links. Similarly, the point a is understood as a starting point, and the point B is understood as an end point, so that in the chip design, the area surrounded by the two paths is the target area, i.e. the optimal wiring area.
Step 905, according to the coordinates of the starting point, the coordinates of the end point and the requirement of the wiring width, wiring is performed on the target area of the available wiring layer to obtain an initial line segment.
It can be understood that, routing on the target area of the available routing layer, rather than routing within the range beyond the target area, can minimize the connection distance between the final two points, thereby effectively improving the utilization rate of the routing layer.
In some embodiments, the width of the initial line segment satisfies the routing width requirement, and the length of the initial line segment is a distance between an abscissa of the starting point and an abscissa of the end point, or the length of the initial line segment is a distance between an ordinate of the starting point and an ordinate of the end point.
Step 906, judging whether the routing distance requirement of the available routing layer is met between the initial line segment and the adjacent line segment; if so, go to step 907; otherwise, go to step 908;
step 907, determining the initial line segment as a target line segment meeting the wiring distance requirement.
It should be noted that after obtaining the target line segment, the electronic device needs to perform the steps of determining whether the end point of the target line segment includes the end point, and the like, that is, perform steps 308 to 314 described in the above embodiment to complete the connection between the start point and the end point, and then perform the wiring task of the start point and the end point of the next line to be connected.
In some embodiments, where the end point of a target line segment does not include the end point, the electronic device may generate a vertical line segment of the target line segment on the target area of another available routing layer with the coordinates of the end point as an end point location.
It can be understood that line segments used for connecting the initial point and the terminal point are all deployed on the target area, so that the connecting distance between the two points can be shortest, and the utilization rate of the wiring layer is improved.
Step 908, determine the physical location relationship of the target neighbor line segment and the initial line segment that do not meet the routing distance requirement.
In some embodiments, the electronic device may first obtain shape information of the target neighbor line segment, and then determine a physical location relationship between the two line segments according to the shape information and the shape information of the initial line segment.
And a step 909, determining the translation direction and the translation distance of the initial line segment according to the physical position relationship.
In some embodiments, step 909 may be implemented as follows: and determining the translation distance and the translation direction according to the physical position relationship and the target area, so that the electronic equipment translates the initial line segment according to the translation direction, and then the translated initial line segment is in the target area of the available wiring layer.
It can be understood that, when the electronic device automatically processes each newly generated line segment, the line segment can be automatically processed according to the above steps, which has the advantage of minimizing the final connecting distance between two points, thereby improving the wiring quality.
And 910, translating the initial line segment according to the translation direction and the translation distance so as to enable the translated initial line segment and the target neighbor line segment to meet the requirement of the wiring distance, and taking the translated initial line segment as the new initial line segment.
911, automatically processing the new initial line segment according to the judgment result whether the new initial line segment and the corresponding neighbor line segment meet the wiring distance requirement, until obtaining the target line segment meeting the wiring distance requirement.
Similarly, here, after obtaining the target line segment, the electronic device needs to perform the steps of determining whether the end point of the target line segment includes the end point, that is, performing steps 308 to 314 of the above embodiment to complete the connection between the start point and the end point, and then performing the wiring task of the start point and the end point of the next line to be connected.
An exemplary application of the embodiments of the present application in a practical application scenario will be described below.
In the embodiment of the present application, in order to avoid the problem of too long chip design cycle caused by manual wiring, at the same time, the basic wiring capability of the EDA tool is fully utilized, such as: the method has the advantages that the command line is used for directly and automatically drawing the metal line segments, punching and judging the physical position relation of the metal line segments, and the like, so that the wiring automation is accelerated, the problem of introducing extra DRC violation is avoided, and the purposes of completing wiring at one time and avoiding later correction are achieved. The embodiment of the application provides a wiring method for chip design, which can comprise the following steps 1) to 8):
step 1), the rear end design completes the Floorplan stage work, and the coordinates (x1, y1) of the starting point and the coordinates (x2, y2) of the terminal point of the current to-be-wired are obtained according to the wiring information of the required wiring, as shown in fig. 11. Suppose x1 ≦ x2, y1 < y2, NDR requires a wiring width of w and a wiring pitch of s.
And 2) judging the available wiring layers near the starting point on the premise of meeting the NDR distance requirement.
Step 3) as shown in fig. 11, a rectangular region 111 determined from a Manhattan (Manhattan) connection line between coordinates, i.e., ((x1, y1) (x2+ w, y2+ w)), is preliminarily set as an optimal wiring region, i.e., the target region;
step 4) as shown in fig. 12, on the optimal wiring area 121 of the available wiring layers, the preliminary shape of the planned wiring is a segment metalA (i.e., the initial segment), i.e., ((x1, y1) (x2+ w, y1+ w));
step 5) as shown in fig. 13, it is judged whether the region 131 (i.e., the surrounding region), i.e., ((x1-s, y1-s) (x2+ w + s, y1+ w + s)) satisfies DRC, i.e., the wiring pitch requirement of the wiring layer object; if yes, executing step a); if not, executing step b);
step a) determining the segment shape as metalA (i.e., the target segment), i.e., (x1, y1) (x2+ w, y1+ w)); then, go to step 6);
and b) generating a new line segment shape according to the DRC feedback information by a method similar to the method of 6) b) and finally obtaining a proper shape, namely the target line segment is finally obtained.
Step 6) as shown in fig. 14, on another available wiring layer, the shape of a line segment metalB perpendicular to the line segment metalA is planned to ((x2, y1) (x2+ w, y2+ w)), and it is judged whether or not the region 141, i.e., ((x2-s, y1-s) (x2+ w + s, y2+ w + s)) satisfies DRC; if yes, executing the following step a); if not, the following step b) is executed, for example, as shown in fig. 15, a line segment metalC exists on the area 151 (i.e., the area 141 in fig. 14), where the line segment metalC is an example of the target neighbor line segment that does not satisfy the routing pitch requirement;
step a) as shown in fig. 14, the shape of the line segment metalB is determined as ((x2, y1) (x2+ w, y2+ w)), another target line segment.
Step b) if a segment metalC (an example of the target neighbor segment) exists in the region 151 as shown in fig. 15, a new segment metalB, i.e., a shape ((x 2-x) is generated according to the DRC feedback information as shown in fig. 160,y1)(x2-x0+ w, y1+ w)), the region 161 is determined, i.e., (x 2-x)0-s,y1-s)(x2-x0+ w + s, y1+ w + s)) whether or not the DRC is satisfied, the present operation is executed in a loop until a segment metalB (i.e., another target segment) satisfying the DRC is found, and the shape of the segment metalA is updated to a final state based on the segment metalB satisfying the DRC.
In some embodiments, the DRC feedback information may include shape information of the line segment metalC, and the physical positional relationship of the line segment metalB and the line segment metalC is determined according to the DRC feedback information and the shape information of the line segment metalB; from the physical positional relationship and the optimum wiring area, the translation distance and the translation direction required for translating the line segment metalB can be determined, as shown in FIG. 15, the translation distance is x0The translation direction is H pointing to K.
Step 7) repeating the operation method of step 6) until the connection from the starting point to the end point is finally completed, and the result is shown in fig. 17;
step 8) as shown in fig. 18, the respective wiring shape nodes are connected by the via holes, and the final wiring is completed.
In the embodiment of the application, the wiring method is provided, the wiring rule is simple, and the tool realization speed is high; and the wiring is finished without introducing DRC violation and subsequent complicated repair work.
In the embodiment of the application, the shortest Manhattan connection mode is combined with DRC inspection, and the method is converted into a wiring method which can be identified by a tool, so that the NDR wiring speed is accelerated, and the wiring quality is improved.
Based on the foregoing embodiments, the present application provides a wiring apparatus for chip design, where the apparatus includes modules and units included in the modules, and can be implemented by a processor; of course, the implementation can also be realized through a specific logic circuit; in implementation, the processor may be a Central Processing Unit (CPU), a Microprocessor (MPU), a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), or a Graphics Processing Unit (GPU), etc.
Fig. 19 is a schematic structural diagram of a wiring device designed for a chip according to an embodiment of the present application, and as shown in fig. 19, the device 190 includes a wiring module 191, a determining module 192, and a processing module 193, where:
the wiring module 191 is used for wiring on the wiring layer according to the wiring information of the wiring required by the chip design to obtain an initial line segment;
the judging module 192 is configured to judge whether the routing distance requirement of the routing layer is met between the initial line segment and the neighboring line segment, so as to obtain a judgment result;
and the processing module 193 is configured to automatically process the initial line segment according to the determination result until a target line segment meeting the requirement of the wiring distance is obtained.
In some embodiments, routing module 191 is configured to: acquiring coordinates of a starting point and a terminal point of the current wire to be connected from the wire connecting information; determining an available wiring layer according to the coordinates of the starting point and the coordinates of the end point; and according to the coordinates of the starting point, the coordinates of the end point and the wiring width requirement of the available wiring layer, wiring is carried out on the available wiring layer to obtain the initial line segment.
In some embodiments, routing module 191 is configured to: determining a Manhattan connecting line with the least turning between the starting point and the end point according to the coordinates of the starting point and the end point; determining a rectangular area determined by the Manhattan connecting line as a target area; and according to the coordinates of the starting point, the coordinates of the end point and the wiring width requirement, wiring is carried out on the target area of the available wiring layer to obtain the initial line segment.
In some embodiments, the width of the initial line segment satisfies the routing width requirement, and the length of the initial line segment is a distance between an abscissa of the starting point and an abscissa of the end point, or the length of the initial line segment is a distance between an ordinate of the starting point and an ordinate of the end point.
In some embodiments, the processing module 193 is configured to: automatically generating a new initial line segment under the condition that the judgment result is that the wiring distance between the initial line segment and the adjacent line segment is not satisfied; and automatically processing the new initial line segment according to the judgment result of whether the new initial line segment and the corresponding neighbor line segment meet the requirement of the wiring distance until the target line segment is obtained.
In some embodiments, the processing module 193 is configured to: determining the physical position relation between a target neighbor line segment which does not meet the requirement of the wiring distance and the initial line segment; determining the translation direction and the translation distance of the initial line segment according to the physical position relationship; and translating the initial line segment according to the translation direction and the translation distance so as to enable the translated initial line segment and the target neighbor line segment to meet the requirement of the wiring distance, and taking the translated initial line segment as the new initial line segment.
In some embodiments, the processing module 193 is configured to: and determining the translation distance and the translation direction according to the physical position relationship and the target area so as to enable the translated initial line segment to be in the target area of the available wiring layer.
In some embodiments, the routing module 191 is further configured to generate a vertical segment of the target segment on another available routing layer, with the coordinate of the end point as an end point location, in a case that the end point of the target segment does not include the end point; a processing module 193 configured to: processing the vertical line segment according to a judgment result of whether the wiring distance requirement of the other available wiring layer is met between the vertical line segment and the corresponding neighbor line segment or not until a target line segment meeting the wiring distance requirement of the other available wiring layer is obtained; the apparatus repeats the above steps in the case 190 that the end point of the target line segment of the other available routing layer does not include the end point, until the target line segment including the end point is obtained, and adds a via at the node of each target line segment through the routing module 191 to complete the connection between the start point and the end point.
In some embodiments, the routing module 191 is further configured to update the previously obtained target line segment according to the currently obtained target line segment, so that the updated target line segment and the currently obtained target line segment are in an L shape.
In some embodiments, the processing module 193 is configured to generate a vertical segment of the target line segment on the target area of the other available routing layer.
The above description of the apparatus embodiments, similar to the above description of the method embodiments, has similar beneficial effects as the method embodiments. For technical details not disclosed in the embodiments of the apparatus of the present application, reference is made to the description of the embodiments of the method of the present application for understanding.
It should be noted that, in the embodiment of the present application, the division of the module by the wiring device of the chip design shown in fig. 19 is schematic, and is only one logic function division, and there may be another division manner in actual implementation. In addition, functional units in the embodiments of the present application may be integrated into one processing unit, may exist alone physically, or may be integrated into one unit by two or more units. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit. Or may be implemented in a combination of software and hardware.
Correspondingly, as shown in fig. 20, in the electronic device 200 provided in the embodiment of the present application, the electronic device 200 may include: comprising a memory 201 and a processor 202, said memory 201 storing a computer program operable on the processor 202, said processor 202 implementing the steps in the methods provided in the embodiments described above when executing said program.
The Memory 201 is configured to store instructions and applications executable by the processor 202, and may also buffer data (e.g., image data, audio data, voice communication data, and video communication data) to be processed or already processed by the processor 202 and modules in the electronic device 200, and may be implemented by a FLASH Memory (FLASH) or a Random Access Memory (RAM).
It should be noted that, in the embodiment of the present application, if the decoding method is implemented in the form of a software functional module and sold or used as a standalone product, the decoding method may also be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing an electronic device to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, or an optical disk. Thus, embodiments of the present application are not limited to any specific combination of hardware and software.
The embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the steps in the wiring method of the chip design provided in the above-mentioned embodiment.
Embodiments of the present application provide a computer program product containing instructions, which when run on a computer, cause the computer to execute the wiring method of the chip design provided by the above method embodiments.
Here, it should be noted that: the above description of the storage medium and device embodiments is similar to the description of the method embodiments above, with similar advantageous effects as the method embodiments. For technical details not disclosed in the embodiments of the storage medium, the chip and the terminal device of the present application, reference is made to the description of the embodiments of the method of the present application for understanding.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" or "some embodiments" means that a particular feature, structure or characteristic described in connection with the embodiments is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" or "in some embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiment of the touch screen system is merely illustrative, for example, the division of the modules is only a logical functional division, and in actual implementation, there may be other division ways, such as: multiple modules or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or modules may be electrical, mechanical or other.
The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules; can be located in one place or distributed on a plurality of network units; some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, all functional modules in the embodiments of the present application may be integrated into one processing unit, or each module may be separately regarded as one unit, or two or more modules may be integrated into one unit; the integrated module can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as a removable Memory device, a Read Only Memory (ROM), a magnetic disk, or an optical disk.
Alternatively, the integrated units described above in the present application may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as independent products. Based on such understanding, the technical solutions of the embodiments of the present application may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing an electronic device to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a removable storage device, a ROM, a magnetic or optical disk, or other various media that can store program code.
The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments.
Features disclosed in several of the product embodiments provided in the present application may be combined in any combination to yield new product embodiments without conflict.
The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.
The above description is only for the embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (13)

1. A method of routing a chip design, the method comprising:
wiring on the wiring layer according to the wiring information of wiring required by chip design to obtain an initial line segment;
judging whether the routing space requirement of the routing layer is met between the initial line segment and the adjacent line segment to obtain a judgment result;
and automatically processing the initial line segment according to the judgment result until a target line segment meeting the wiring distance requirement is obtained.
2. The method of claim 1, wherein the wiring on the wiring layer according to the wiring information of the wiring required by the chip design to obtain the initial line segment comprises:
acquiring coordinates of a starting point and a terminal point of the current wire to be connected from the wire connecting information;
determining an available wiring layer according to the coordinates of the starting point and the coordinates of the end point;
and according to the coordinates of the starting point, the coordinates of the end point and the wiring width requirement of the available wiring layer, wiring is carried out on the available wiring layer to obtain the initial line segment.
3. The method of claim 2, wherein said routing on said available routing layer to obtain said initial line segment according to said coordinates of said starting point, said coordinates of said ending point and said routing width requirement of said available routing layer comprises:
determining a Manhattan connecting line with the least turning between the starting point and the end point according to the coordinates of the starting point and the end point;
determining a rectangular area determined by the Manhattan connecting line as a target area;
and according to the coordinates of the starting point, the coordinates of the end point and the wiring width requirement, wiring is carried out on the target area of the available wiring layer to obtain the initial line segment.
4. The method of claim 3, wherein the width of the initial line segment satisfies the routing width requirement, and wherein the length of the initial line segment is a distance between an abscissa of the starting point and an abscissa of the end point, or wherein the length of the initial line segment is a distance between an ordinate of the starting point and an ordinate of the end point.
5. The method of claim 3, wherein automatically processing the initial line segment according to the determination result until a target line segment satisfying the routing distance requirement is obtained comprises:
automatically generating a new initial line segment under the condition that the judgment result is that the wiring distance between the initial line segment and the adjacent line segment is not satisfied;
and automatically processing the new initial line segment according to the judgment result of whether the new initial line segment and the corresponding neighbor line segment meet the requirement of the wiring distance until the target line segment is obtained.
6. The method of claim 5, wherein automatically generating a new initial line segment comprises:
determining the physical position relation between a target neighbor line segment which does not meet the requirement of the wiring distance and the initial line segment;
determining the translation direction and the translation distance of the initial line segment according to the physical position relationship;
and translating the initial line segment according to the translation direction and the translation distance so as to enable the translated initial line segment and the target neighbor line segment to meet the requirement of the wiring distance, and taking the translated initial line segment as the new initial line segment.
7. The method of claim 6, wherein determining the translation direction and the translation distance of the initial line segment according to the physical position relationship comprises:
and determining the translation distance and the translation direction according to the physical position relationship and the target area so as to enable the translated initial line segment to be in the target area of the available wiring layer.
8. The method according to any one of claims 3 to 7, further comprising:
under the condition that the end point of the target line segment does not comprise the end point, taking the coordinate of the end point as an end point position, and generating a vertical line segment of the target line segment on another available wiring layer;
processing the vertical line segment according to a judgment result of whether the wiring distance requirement of the other available wiring layer is met between the vertical line segment and the corresponding neighbor line segment or not until a target line segment meeting the wiring distance requirement of the other available wiring layer is obtained;
and under the condition that the end point of the target line segment of the other available wiring layer does not comprise the end point, repeating the steps until the target line segment comprising the end point is obtained, and adding a through hole at the node of each target line segment to complete the connection between the starting point and the end point.
9. The method of claim 8, further comprising:
and updating the target line segment obtained at the previous time according to the currently obtained target line segment so that the updated target line segment and the currently obtained target line segment are in an L shape.
10. The method of claim 9, wherein generating the vertical line segment of the target line segment on another available routing layer comprises:
generating a vertical segment of the target line segment on the target area of the other available routing layer.
11. A wiring arrangement for chip design, comprising:
the wiring module is used for wiring on the wiring layer according to the wiring information of wiring required by chip design to obtain an initial line segment;
the judging module is used for judging whether the wiring space requirement of the wiring layer is met between the initial line segment and the adjacent line segment or not to obtain a judging result;
and the processing module is used for automatically processing the initial line segment according to the judgment result until a target line segment meeting the wiring distance requirement is obtained.
12. An electronic device comprising a memory and a processor, the memory storing a computer program operable on the processor, wherein the processor implements the method of any one of claims 1 to 10 when executing the program.
13. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1 to 10.
CN202011112832.4A 2020-10-16 2020-10-16 Wiring method, device, equipment and storage medium for chip design Pending CN114386356A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114781318A (en) * 2022-06-16 2022-07-22 飞腾信息技术有限公司 Module pin wiring method and device of chip, electronic equipment and storage medium
CN115081386A (en) * 2022-08-11 2022-09-20 飞腾信息技术有限公司 Wiring optimization method and device for integrated circuit and related equipment
CN115130424A (en) * 2022-07-01 2022-09-30 苏州浪潮智能科技有限公司 Automatic wiring method, device, equipment and medium for multilayer PCB

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114781318A (en) * 2022-06-16 2022-07-22 飞腾信息技术有限公司 Module pin wiring method and device of chip, electronic equipment and storage medium
CN114781318B (en) * 2022-06-16 2022-09-13 飞腾信息技术有限公司 Module pin wiring method and device of chip, electronic equipment and storage medium
CN115130424A (en) * 2022-07-01 2022-09-30 苏州浪潮智能科技有限公司 Automatic wiring method, device, equipment and medium for multilayer PCB
CN115130424B (en) * 2022-07-01 2024-01-23 苏州浪潮智能科技有限公司 Automatic wiring method, device, equipment and medium for multilayer PCB
CN115081386A (en) * 2022-08-11 2022-09-20 飞腾信息技术有限公司 Wiring optimization method and device for integrated circuit and related equipment

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