CN115081386B - Wiring optimization method and device for integrated circuit and related equipment - Google Patents
Wiring optimization method and device for integrated circuit and related equipment Download PDFInfo
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- CN115081386B CN115081386B CN202210962334.1A CN202210962334A CN115081386B CN 115081386 B CN115081386 B CN 115081386B CN 202210962334 A CN202210962334 A CN 202210962334A CN 115081386 B CN115081386 B CN 115081386B
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- G06F30/39—Circuit design at the physical level
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Abstract
The invention provides a wiring optimization method, an optimization device and related equipment of an integrated circuit, wherein the wiring optimization method comprises the following steps: determining a target wire, wherein the target wire is any wire with a time sequence violation in the integrated circuit; determining one wiring layer of the integrated circuit as a target wiring layer, wherein the target wiring layer is the wiring layer where the target wiring is located or any wiring layer on the top of the target wiring; determining whether a target wiring layer has a target area, wherein the target area is used for enabling the wiring pitch of target wirings wound inside the target wiring layer to be larger than the current wiring pitch of the target wirings; if the target wiring layer has the target area, the target wiring is rewound, and the target wiring is wound in the target area, so that the wiring distance of the target wiring after the target wiring is rewound is large, and the crosstalk of the target wiring can be reduced or eliminated.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a wiring optimization method, an optimization device and related equipment of an integrated circuit.
Background
The integrated circuit design comprises a front-end functional design stage and a back-end physical implementation stage. The front-end function design stage comprises logic design, synthesis and the like, and the back-end physical implementation stage comprises chip layout, clock synthesis, wiring and the like. In the wiring stage, the clock lines, the signal lines and other wires need to be reasonably wired to meet the requirements of chip area and the like. However, the current wiring method easily causes crosstalk between the wires, and affects the transmission effect of the wires on signals.
Disclosure of Invention
In view of the above, the present invention is directed to a method, an apparatus and a related device for optimizing wiring of an integrated circuit, so as to optimize the wiring more reasonably and avoid the influence of crosstalk between wirings on the transmission effect of signals.
In a first aspect, the present invention provides a wiring optimization method for an integrated circuit, including:
determining a target wire, wherein the target wire is any wire with a time sequence violation in the integrated circuit;
determining one wiring layer of the integrated circuit as a target wiring layer, wherein the target wiring layer is the wiring layer where the target wiring is located or any wiring layer on the top of the target wiring;
determining whether a target area exists in the target wiring layer, wherein the target area is used for enabling the wiring distance of the target wiring wound in the target wiring layer to be larger than the current wiring distance of the target wiring;
and if the target wiring layer has the target area, rewinding the target wiring and enabling the target wiring to be wound in the target area.
Optionally, if the target wiring layer does not have the target area, determining a next wiring layer of the integrated circuit as a target wiring layer; wherein the next target wiring level is on top of the previous target wiring level.
Optionally, the determining whether the target routing layer has the target area includes:
determining the area of the target wiring layer corresponding to the target routing as an initial area;
determining whether a target area exists within a preset distance around the starting area;
and if the target area exists in the peripheral preset distance, the target wiring layer has the target area.
Optionally, the determining whether a target area exists within a preset distance around the starting area includes:
determining a direction away from the starting area as a target direction;
dividing the area within the preset distance of the starting area into a plurality of sub-areas along the target direction;
determining whether a target sub-area exists in the plurality of sub-areas, wherein the wiring density in the target sub-area is less than a preset density, and the preset density is less than the current wiring density of the target wiring;
and if the target sub-region exists, the target region exists in the preset distance.
Optionally, if the target sub-region does not exist, determining another direction far away from the starting region as the target direction.
Optionally, the target direction is perpendicular to an extending direction of the target trace.
Optionally, the length of the sub-region is greater than or equal to the length of the target trace, and the width of the sub-region is at least greater than the sum of the width of the target trace and the current trace pitch of the target trace.
Optionally, the preset distance ranges from 45 μm to 55 μm; the preset density ranges from 25% to 35%.
Optionally, the rewinding the target trace includes:
according to the first preset constraint and the second preset constraint, rewinding is carried out on the target wiring; the first preset constraint is used for enabling the lowest wiring layer of the target routing to be the target wiring layer and enabling the target routing to be routed in the target area; the second preset constraint is used for enabling the wiring distance of the target wiring after the wire is rewound to be at least twice of the wiring distance of the target wiring before the wire is rewound.
In a second aspect, the present invention provides a wiring optimization apparatus for an integrated circuit, comprising:
the first processing unit is used for determining a target wire, wherein the target wire is any wire with a timing violation in the integrated circuit;
the second processing unit is used for determining one wiring layer of the integrated circuit as a target wiring layer, wherein the target wiring layer is the wiring layer where the target routing is located or any wiring layer on the top of the target routing;
and the third processing unit is used for determining whether a target area exists in the target wiring layer, wherein the target area is used for enabling the wiring distance of the target wiring wound in the target wiring layer to be larger than the current wiring distance of the target wiring, and if the target wiring layer exists in the target area, the target wiring is rewound, and the target wiring is wound in the target area.
In a third aspect, the present invention provides an electronic device comprising:
a memory for storing at least one set of instructions;
a processor for executing the at least one set of instructions to perform a method of wiring optimization for an integrated circuit as claimed in any one of the preceding claims.
In a fourth aspect, the invention provides a readable storage medium storing at least one set of instructions for causing a processor to perform a method of wiring optimization for an integrated circuit as described in any one of the above.
According to the wiring optimization method, the optimization device and the related equipment of the integrated circuit, after the target wiring with the timing sequence violation is determined, one wiring layer of the integrated circuit is determined as the target wiring layer, the target wiring layer is the wiring layer where the target wiring is located or any wiring layer on the top of the target wiring, if the target wiring layer has the target area, the target area is used for enabling the wiring distance of the target wiring which is wound inside the target wiring to be larger than the current wiring distance of the target wiring, the target wiring is rewound, the target wiring is wound inside the target area, the wiring distance of the target wiring after the target wiring is rewound is larger, the crosstalk of the target wiring can be reduced or eliminated, and the signal transmission effect of the target wiring is improved.
Drawings
The above and other objects, features and advantages of the present application will become more apparent by describing in more detail embodiments of the present application with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings, like reference numbers generally represent like parts or steps.
Fig. 1 is a schematic cross-sectional view of an integrated circuit.
Fig. 2 is a schematic top view of a wiring layer.
Fig. 3 is a flowchart of a method for optimizing routing of an integrated circuit according to an embodiment of the present invention.
Fig. 4 is a schematic top view of a target wiring layer according to an embodiment of the present invention.
Fig. 5 is a schematic top view of the target wiring layer shown in fig. 4 after a target trace is rerouted.
Fig. 6 is a schematic top view of the target wiring layer shown in fig. 4 after a plurality of target traces are rerouted.
Fig. 7 is a schematic diagram of a determination method of a target area according to an embodiment of the present invention.
Fig. 8 is a schematic diagram of another determination method of a target area according to an embodiment of the present invention.
Fig. 9 is a schematic diagram of another determination method of a target area according to an embodiment of the present invention.
Fig. 10 is a schematic top view of another target wiring layer according to an embodiment of the present invention.
Fig. 11 is a schematic structural diagram of a wiring optimization apparatus for an integrated circuit according to an embodiment of the present invention.
Fig. 12 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, fig. 1 is a schematic cross-sectional view of integrated circuits, each of which includes a plurality of wiring layers 20, typically metal layers, stacked one on another. Each wiring layer 20 includes a plurality of traces 201, with an insulating layer 21 between adjacent wiring layers 20, and the traces 201 of adjacent wiring layers 20 are electrically connected by vias 202 that penetrate the insulating layer 21.
As shown in fig. 2, fig. 2 is a schematic view of a top view structure of a wiring layer, in a plurality of wires 201 of the same wiring layer, if a distance d1 between adjacent wires 201 is smaller, a coupling capacitance between adjacent wires 201 is larger, so that signal crosstalk between adjacent wires 201 is larger, and further integrity of a signal transmitted by the wires 201 is influenced, and a transmission effect of the signal is influenced. The integrity of the signal is affected, which is liable to cause timing violation of the signal.
Based on this, the invention provides a wiring optimization scheme, which determines the traces with timing violation from the timing report of the integrated circuit, determines any trace with timing violation as a target trace, and reduces or eliminates the signal crosstalk of the target trace and reduces the timing violation by searching a target area in the wiring layer of the integrated circuit and optimizing the position of the target trace through the target area.
As an optional implementation of the disclosure of the present invention, an embodiment of the present invention provides a wiring optimization method for an integrated circuit, and as shown in fig. 3, fig. 3 is a flowchart of the wiring optimization method for the integrated circuit provided in the embodiment of the present invention, where the wiring optimization method for the integrated circuit includes:
s301: determining a target wire, wherein the target wire is any wire with a time sequence violation in the integrated circuit;
in the embodiment of the present invention, the trace refers to a conductive line connecting devices in an integrated circuit, and the trace is generally a metal line. In the design process of the integrated circuit, after the wiring of the integrated circuit is completed, the positions of the wirings, the connection relationship and the like are determined. The integrated circuit is then analyzed for timing, to determine whether the setup and hold times of the device clock signal meet the requirements, and to generate a timing report. The timing report records devices and their connected traces that do not meet the requirements of setup time or hold time. Based on this, in the embodiment of the present invention, the trace having the timing violation is determined from the timing report of the integrated circuit, and any trace having the timing violation is determined as the target trace.
It should be noted that, as shown in fig. 1, if a trace having a timing violation is formed by connecting a plurality of traces 201 respectively located in a plurality of wiring layers, the trace 201 with the longest length among the plurality of connected traces 201 is determined as a target trace 201a, and the wiring layer where the trace 201 with the longest length is located is determined as the wiring layer where the target trace 201a is located. Wherein the length and location information of the trace 201 can be obtained from timing reports and physical views of the integrated circuit design.
S302: determining one wiring layer of the integrated circuit as a target wiring layer, wherein the target wiring layer is the wiring layer where the target wiring is located or any wiring layer on the top of the target wiring;
in the embodiment of the present invention, referring to fig. 1, a wiring layer where a target trace 201a is located is determined as a target trace layer, and then other wiring layers on the top of the wiring layer where the target trace 201a is located are sequentially determined as target wiring layers according to a sequence from bottom to top. This is mainly due to timing considerations, because the routing layer is generally a metal layer, and the resistance of the metal layer is smaller the higher the metal layer is, the same trace length and the line delay is smaller, and the increased line delay generally exceeds the benefit of reducing or eliminating crosstalk the lower the metal layer is, therefore, in the embodiment of the present invention, the target routing layer is generally not lower than the routing layer where the target routing 201a is located.
S303: determining whether a target wiring layer has a target area, wherein the target area is used for enabling the wiring pitch of target wirings wound inside the target wiring layer to be larger than the current wiring pitch of the target wirings;
in the embodiment of the invention, the target wiring layer is checked based on the physical view of the integrated circuit design, and whether a target area exists in the target wiring layer is determined. As shown in fig. 4, fig. 4 is a schematic view of a top view structure of a target wiring layer according to an embodiment of the present invention, where the target wiring layer is a wiring layer where a target trace 201a is located, the target wiring layer has a target area a, and a trace pitch of the target area a is larger or a trace density of the target area a is smaller, so that after the target trace is routed in the target area a, a trace pitch of the target trace is larger than a current trace pitch of the target trace, and thus, a routing area of the target trace can be adjusted, a distance between the target trace and an adjacent trace can be increased, and signal crosstalk of the target trace can be improved. Where VSS represents a grounded trace or metal block in the routing layer.
S304: and if the target wiring layer has the target area, rewinding the target wiring, and enabling the target wiring to be wound in the target area.
In this embodiment of the present invention, if the target wiring layer has the target area a, as shown in fig. 5, fig. 5 is a schematic view of a top view structure of the target wiring layer shown in fig. 4 after a target wire is rewound, the target wire 201a is rewound, that is, the target wire 201a at the initial position is deleted, and the position of the target wire 201a is adjusted to the target area a, that is, the target wire 201a is wound in the target area a.
Because the target area a can make the wiring distance d2 of the target wiring 201a wound inside the target area a greater than the current wiring distance d1 of the target wiring 201a, the wiring distance of the target wiring 201a after re-winding can be made greater, and then the crosstalk of the target wiring 201a can be reduced or eliminated, which not only can improve the signal transmission effect of the target wiring 201a, but also can reduce timing violations and improve the performance of the integrated circuit. In addition, the trace distance d3 at the initial position of the target trace 201a also becomes larger, which also reduces or eliminates crosstalk between adjacent traces at the initial position, and improves the signal transmission effect.
In some embodiments of the present invention, if the target routing layer does not have a target area, a next routing layer of the integrated circuit is determined as the target routing layer, where the next target routing layer is located on top of a previous target routing layer. That is to say, if the target routing layer does not have a target area, the next routing layer of the integrated circuit is determined as the target routing layer according to the sequence from bottom to top, so that the target area which minimizes the line delay of the target routing can be found out more quickly.
Of course, the present invention is not limited to this, and in other embodiments, the routing layers may be sequentially selected from top to bottom, that is, the next target routing layer may also be located at the bottom of the previous target routing layer, as long as the target routing layer is the routing layer where the target routing is located or any routing layer on the top of the target routing.
In the embodiment of the present invention, after a target trace is rewound, or after it is determined that a target area of the target trace does not exist in a routing layer where the target trace is located in the integrated circuit and a routing layer on the top of the routing layer, a next trace with timing violation is determined as a target trace, and the steps of determining the target routing layer and the target area are repeated until all traces with timing violation in the integrated circuit are optimized, and then the process is ended.
As shown in fig. 6, fig. 6 is a schematic top view structure diagram of the target wiring layer shown in fig. 4 after the multiple target wires are rewound, where the multiple wires 201 in the target wiring layer are rewound and moved from the left area to the right area of the target wiring layer, so that the pitch of the multiple wires 201 is increased, and thus the wire layout of the whole wiring layer can be optimized, and the performance of the integrated circuit is improved.
In some embodiments of the present invention, determining whether a target routing layer has a target area comprises: determining a region of the target wiring layer corresponding to the target routing as an initial region; determining whether a target area exists within a preset distance around the starting area; and if the target area exists in the preset distance, the target wiring layer exists in the target area.
As shown in fig. 7, fig. 7 is a schematic diagram of a determination manner of a target area according to an embodiment of the present invention, where the target wiring layer is a wiring layer where a target wire 201a is located, and an area where the target wire 201a is located is an initial area B, and then it is determined whether a target area exists within a preset distance L around the initial area B, if a target area exists within the preset distance L around the initial area B, the target wiring layer has a target area, and if a target area does not exist within the preset distance L around the target area B, the target wiring layer does not have a target area.
On the basis of the foregoing embodiments, in some embodiments of the present invention, determining whether the target area exists within the preset distance around the start area includes: determining a direction far away from the starting area as a target direction; dividing the area within a preset distance of the starting area into a plurality of sub-areas along the target direction; determining whether a target sub-area exists in the plurality of sub-areas, wherein the wiring density in the target sub-area is less than a preset density, and the preset density is less than the current wiring density of the target wiring; and if the target sub-region exists, the target region exists in the preset distance.
As shown in fig. 8, fig. 8 is a schematic diagram of another determination method of a target area according to an embodiment of the present invention, a rightward direction X' along a start area B may be determined as a target direction, an area within a preset distance L from the start area B in the target direction is divided into a plurality of sub-areas C, and then whether a target sub-area exists in the plurality of sub-areas C is determined. The wiring density in the target sub-area is less than the preset density, and the preset density is less than the current wiring density of the target wiring. If the target sub-area exists, the target area exists in the preset distance L around the starting area B; if the target sub-region does not exist, the target region does not exist within the preset distance L on the right side of the start region B, and another direction away from the start region is determined as the target direction, as shown in fig. 9, fig. 9 is a schematic diagram of another determination method of the target region provided in the embodiment of the present invention, a direction X along the left side of the start region B is determined as the target direction, and then the subsequent steps of dividing the sub-region and the like are performed.
If the target sub-region does not exist within the preset distance L in each direction away from the starting region, the target wiring layer does not have the target region, the next wiring layer of the integrated circuit can be determined as the target wiring layer, and whether the target region exists in the next target wiring layer or not can be determined.
Fig. 8 and 9 only illustrate the target wiring layer as the wiring layer where the target routing is located, but not limited thereto, in other embodiments, as shown in fig. 10, fig. 10 is a schematic top view structure diagram of another target wiring layer provided in an embodiment of the present invention, where the target wiring layer is another wiring layer on top of the wiring layer where the target routing is located, and then an area corresponding to the target routing of the target wiring layer is determined according to an orthographic projection 201a' of the target routing in the target wiring layer, and is determined as a starting area B.
In some embodiments of the present invention, the target direction is perpendicular to the extending direction of the target trace. As shown in fig. 8 or fig. 9, if the extending direction of the target trace is the Y direction, the target direction is the right direction X' or the left direction X. Of course, if the extending direction of the target trace is the X direction, the target direction is the upward direction Y or the downward direction Y', which is not described herein again. Of course, in other embodiments, the target direction may also be the same as the extending direction of the target trace, and is not described herein again.
In some specific examples, a region where the start region B is located is defined as a start frame selection region, a step distance is defined as a constant B, where the step distance B is equal to a length of the frame selection region in a step direction, and then the frame selection region is sequentially stepped along a target direction to traverse the target wiring layer, where each frame selection region is a sub-region, after each frame selection region or sub-region is determined, an area of routing lines in the frame selection region or sub-region is obtained, and a density of routing lines in the frame selection region or sub-region is calculated, where the density of routing lines is equal to a ratio of the area of routing lines in the region to the area of the region. And if the routing density is less than the preset density, the frame selection area or the sub-area is the target sub-area. In some embodiments of the present invention, the predetermined density is in a range of 25% to 35%, optionally 30%. And when the traversal range exceeds the preset distance L, stopping traversal, replacing the target direction, and if the target directions of the target wiring layer are traversed, replacing the target wiring layer.
It should be noted that, if the traversal range exceeds the preset distance L, even if the pitch of the re-routed target trace is large, since the position of the re-routed target trace is far away from the initial position, a longer trace and more via holes need to be laid out to connect the target trace with other traces or devices, which may result in a longer line delay of the target trace and is not favorable for signal transmission.
It should be further noted that the size of the target area is the same as that of the frame selection area or sub-area, wherein the length of the frame selection area or sub-area is greater than or equal to the length of the target trace, and the width of the frame selection area or sub-area is at least greater than the sum of the width of the target trace and the current trace pitch of the target trace, so as to effectively select the frame selection area or sub-area capable of making the trace pitch of the target trace wound inside the frame selection area or sub-area greater than the current trace pitch of the target trace.
Of course, in practical applications, if the target wiring layer is below the 11 th wiring layer, the traversal range cannot exceed the preset distance L, but if the target wiring layer is above the 11 th wiring layer, the traversal range may appropriately exceed the preset distance L, which needs to be determined according to the material and manufacturing process of the wiring layers, for example, the resistances of the wiring layers with different materials in different processes are different, and the line delays are also different, so that it cannot be determined in a short time.
In some embodiments of the present invention, the predetermined distance L is in a range of 45 μm to 55 μm, and optionally 50 μm. Of course, if the target wiring layer is the 12 th or 13 th wiring layer, the preset distance L may be 70 μm; if the target wiring layer is the 14 th or 15 th wiring layer, the preset distance L may be 100 μm.
Based on any of the above embodiments, in some embodiments of the present invention, the rewinding the target trace includes: according to the first preset constraint and the second preset constraint, rewinding is carried out on the target wiring; the first preset constraint is used for enabling the lowest wiring layer of the target wiring to be a target wiring layer and enabling the target wiring to be wound in a target area; the second predetermined constraint is configured to cause the trace pitch of the re-routed target trace to be at least twice the trace pitch of the target trace before re-routing.
And carrying out routing area constraint on the target routing according to the determined target area, setting the lowest layer of routing of the target routing as a target routing layer where the target area is located, and setting the pitch of the target routing to be 2~3 times of the original pitch so as to prevent crosstalk in a new target area. After the target wiring is regulated, the original wiring must be deleted, otherwise, the wiring tool cannot perform the wiring again according to the constraint. After rewinding, the timing sequence needs to be evaluated again, and the timing sequence violation is repaired.
In the embodiment of the invention, for the wiring with crosstalk or timing sequence violation, the target area with sufficient wiring resources is searched, the target wiring is assigned to preferentially wire in the target area, and the multiple wiring intervals and the lowest wiring layer are arranged, so that the dense wiring around the target wiring can be avoided, and the timing sequence influence caused by crosstalk can be more efficiently optimized on the premise of not changing the design greatly under the condition of large number of the target wiring.
As an optional implementation of the disclosure, an embodiment of the present invention further provides a wiring optimization apparatus for an integrated circuit, as shown in fig. 11, where fig. 11 is a schematic structural diagram of the wiring optimization apparatus for an integrated circuit provided in the embodiment of the present invention, and the wiring optimization apparatus includes:
the first processing unit 101 is configured to determine a target trace, where the target trace is any trace in the integrated circuit where a timing violation exists;
the second processing unit 102 is configured to determine one wiring layer of the integrated circuit as a target wiring layer, where the target wiring layer is a wiring layer where the target trace is located or any wiring layer on the top of the target trace;
the third processing unit 103 is configured to determine whether a target wiring layer has a target area, where the target area is used to enable a wiring pitch of a target wire wound inside the target wiring layer to be greater than a current wiring pitch of the target wire, and re-wind the target wire and enable the target wire to be wound inside the target area if the target wiring layer has the target area.
In some embodiments of the present invention, if the target wiring layer does not have the target area, the second processing unit 102 is further configured to determine a next wiring layer of the integrated circuit as the target wiring layer; wherein the next target wiring level is on top of the previous target wiring level.
In some embodiments of the present invention, the third processing unit 103 determining whether the target wiring layer has the target area includes:
determining the position of the target wiring layer corresponding to the target routing as a starting area;
determining whether a target area exists within a preset distance around the starting area;
and if the target area exists in the peripheral preset distance, the target wiring layer has the target area.
In some embodiments of the present invention, the determining, by the third processing unit 103, whether the target area exists within the preset distance around the start area includes:
determining a direction far away from the starting area as a target direction;
dividing the area within a preset distance of the starting area into a plurality of sub-areas along the target direction;
determining whether a target sub-area exists in the plurality of sub-areas, wherein the wiring density in the target sub-area is less than a preset density, and the preset density is less than the current wiring density of the target wiring;
and if the target sub-region exists, the target region exists in the preset distance.
In some embodiments of the present invention, if there is no target sub-area, the third processing unit 103 determines another direction away from the starting area as the target direction.
In some embodiments of the present invention, the target direction is perpendicular to the extending direction of the target trace.
In some embodiments of the present invention, the length of the sub-area is greater than or equal to the length of the target trace, and the width of the sub-area is at least greater than the sum of the width of the target trace and the current trace pitch of the target trace.
In some embodiments of the present invention, the predetermined distance is in a range of 45 μm to 55 μm; the preset density range is 25% -35%.
In some embodiments of the present invention, the rewinding the target trace by the third processing unit 103 includes:
according to the first preset constraint and the second preset constraint, rewinding is carried out on the target wiring; the first preset constraint is used for enabling the lowest wiring layer of the target wiring to be a target wiring layer and enabling the target wiring to be wound in a target area; the second predetermined constraint is configured to cause the trace pitch of the re-routed target trace to be at least twice the trace pitch of the target trace before re-routing.
As another optional implementation of the disclosure, an embodiment of the present invention further provides an electronic device, as shown in fig. 12, where fig. 12 is a schematic structural diagram of the electronic device provided in the embodiment of the present invention, and the electronic device includes:
a memory 200 and a processor 210;
wherein, the memory 200 is connected with the processor 210 for storing programs;
the processor 210 is configured to implement the method for optimizing the wiring of the integrated circuit according to any of the embodiments by executing the program stored in the memory 200.
Specifically, the electronic device may further include: a bus, a communication interface 220, an input device 230, and an output device 240. The processor 210, the memory 200, the communication interface 220, the input device 230, and the output device 240 are connected to each other through a bus. Wherein:
a bus may comprise a path that transfers information between components of a computer system.
The processor 210 may be a general-purpose processor, such as a general-purpose Central Processing Unit (CPU), a microprocessor, etc., an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of programs according to the present invention. But may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components.
The processor 210 may include a main processor and may also include a baseband chip, modem, and the like. The memory 200 stores programs for executing the technical solution of the present invention, and may also store an operating system and other key services. In particular, the program may include program code including computer operating instructions. More specifically, memory 200 may include a read-only memory (ROM), another type of static storage device that may store static information and instructions, a Random Access Memory (RAM), another type of dynamic storage device that may store information and instructions, a magnetic disk storage, a flash, and so forth.
The input device 230 may include a means for receiving data and information input by a user, such as a keyboard, mouse, camera, scanner, light pen, voice input device, touch screen, pedometer, or gravity sensor, among others. Output device 240 may include equipment that allows output of information to a user, such as a display screen, a printer, speakers, and the like.
As another alternative implementation of the disclosure, the embodiment of the present invention may also provide a computer program product, which includes computer program instructions, and the computer program instructions, when executed by a processor, cause the processor to execute the steps in the wiring optimization method of the integrated circuit according to various embodiments of the present invention.
The computer program product may include program code for carrying out operations for embodiments of the present invention in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server.
As another alternative implementation of the disclosure, the embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to perform the steps in the wiring optimization method of the integrated circuit according to the various embodiments of the present invention.
In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (12)
1. A method for optimizing routing in an integrated circuit, comprising:
determining a target wire, wherein the target wire is any wire with a time sequence violation in the integrated circuit;
determining one wiring layer of the integrated circuit as a target wiring layer, wherein the target wiring layer is the wiring layer where the target wiring is located or any wiring layer on the top of the target wiring;
determining whether a target area exists in the target wiring layer, wherein the target area is used for enabling the wiring distance of the target wiring wound in the target wiring layer to be larger than the current wiring distance of the target wiring;
and if the target wiring layer has the target area, rewinding the target wiring, and enabling the target wiring to be wound in the target area.
2. The routing optimization method of claim 1, wherein if the target routing layer does not exist in the target area, determining a next routing layer of the integrated circuit as a target routing layer; wherein the next target wiring level is on top of the previous target wiring level.
3. The route optimization method of claim 1, wherein said determining whether a target area exists for the target routing layer comprises:
determining the area of the target wiring layer corresponding to the target routing as a starting area;
determining whether a target area exists within a preset distance around the starting area;
and if the target area exists in the peripheral preset distance, the target wiring layer has the target area.
4. The method of claim 3, wherein the determining whether the target area exists within a preset distance around the starting area comprises:
determining a direction away from the starting area as a target direction;
dividing the area within the preset distance of the starting area into a plurality of sub-areas along the target direction;
determining whether a target sub-area exists in the plurality of sub-areas, wherein the wiring density in the target sub-area is less than a preset density, and the preset density is less than the current wiring density of the target wiring;
and if the target sub-region exists, the target region exists in the preset distance.
5. The method of claim 4, wherein if the target sub-region does not exist, another direction away from the start region is determined as a target direction.
6. The wiring optimization method according to claim 4 or 5, wherein the target direction is perpendicular to an extending direction of the target trace.
7. The wiring optimization method according to claim 4, wherein the length of the sub-region is greater than or equal to the length of the target trace, and the width of the sub-region is at least greater than the sum of the width of the target trace and the current trace pitch of the target trace.
8. The wiring optimization method according to claim 4, wherein the predetermined distance is in a range of 45 μm to 55 μm; the preset density ranges from 25% to 35%.
9. The method of claim 1, wherein the rerouting the target trace comprises:
according to the first preset constraint and the second preset constraint, rewinding is carried out on the target wiring; the first preset constraint is used for enabling the lowest wiring layer of the target routing to be the target wiring layer and enabling the target routing to be routed in the target area; the second preset constraint is used for enabling the wiring distance of the target wiring after the wire is rewound to be at least twice of the wiring distance of the target wiring before the wire is rewound.
10. An apparatus for optimizing routing of an integrated circuit, comprising:
the first processing unit is used for determining a target wire, wherein the target wire is any wire with a timing violation in the integrated circuit;
the second processing unit is used for determining one wiring layer of the integrated circuit as a target wiring layer, wherein the target wiring layer is the wiring layer where the target routing is located or any wiring layer on the top of the target routing;
and the third processing unit is used for determining whether a target area exists in the target wiring layer, wherein the target area is used for enabling the wiring distance of the target wiring wound in the target wiring layer to be larger than the current wiring distance of the target wiring, and if the target wiring layer exists in the target area, the target wiring is rewound, and the target wiring is wound in the target area.
11. An electronic device, comprising:
a memory for storing at least one set of instructions;
a processor for executing the at least one set of instructions to perform a method of wiring optimization for an integrated circuit as claimed in any one of claims 1 to 9.
12. A readable storage medium storing at least one set of instructions for causing a processor to perform a method for wiring optimization of an integrated circuit as claimed in any one of claims 1 to 9.
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| CN117422042A (en) * | 2023-11-08 | 2024-01-19 | 广芯微电子（广州）股份有限公司 | Design method and device for comb-shaped winding barrier layer |
| CN117688899B (en) * | 2024-02-02 | 2024-05-24 | 深圳华强电子网集团股份有限公司 | Wiring analysis optimizing system based on high-density integrated circuit |
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| JP2004013552A (en) * | 2002-06-07 | 2004-01-15 | Fujitsu Ltd | Wiring design method for integrated circuit device, its system, and its program |
| CN110598235B (en) * | 2019-06-25 | 2023-04-18 | 眸芯科技（上海）有限公司 | Method and system for repairing time sequence violation in chip design |
| CN114386356A (en) * | 2020-10-16 | 2022-04-22 | Oppo广东移动通信有限公司 | Wiring method, device, equipment and storage medium for chip design |
| CN112347722B (en) * | 2020-11-12 | 2023-12-26 | 苏州盛科通信股份有限公司 | Method and device for efficiently evaluating chip Feed-through flow number of stages |
| CN112347732A (en) * | 2020-11-27 | 2021-02-09 | 北京百瑞互联技术有限公司 | Integrated circuit layered routing planning method, device, storage medium and equipment |
| CN113283212A (en) * | 2021-05-24 | 2021-08-20 | 海光信息技术股份有限公司 | Method and device for analyzing winding quality of integrated circuit, electronic equipment and storage medium |
| CN113221491A (en) * | 2021-05-27 | 2021-08-06 | 京微齐力(北京)科技有限公司 | Integrated circuit design method, device and equipment |
| CN114662446B (en) * | 2022-03-29 | 2024-05-03 | 东科半导体(安徽)股份有限公司 | Wiring optimization method for reducing dynamic power consumption |
| CN114781318B (en) * | 2022-06-16 | 2022-09-13 | 飞腾信息技术有限公司 | Module pin wiring method and device of chip, electronic equipment and storage medium |
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