AU2021106353A4 - A method for vlsi layout of hypertree structure - Google Patents
A method for vlsi layout of hypertree structure Download PDFInfo
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- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F30/347—Physical level, e.g. placement or routing
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Abstract
The present invention generally relates to a method for VLSI layout
of hyper tree structure comprises laying out a Hyper tree in a very small
space with any number of vertices to put out the Hyper tree on a plane in
the manner; imposing conditions for the plane; and changing direction in
which the nodes are placed depending on the structure of the tree to
minimize the Hyper tree structure of the VLSI layout.
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Description
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The present disclosure relates to a method for VLSI layout of hypertree structure to incorporate the prime aspects of the hypercube and binary tree.
Thompson created a formal model for VLSI graph layout to capture VLSI layout difficulties in a mathematical context. The model is based on Mead and Conway's VLSI design guidelines, and it is consistent with them. It's also comparable to the Manhattan wiring approach, which is frequently utilized. In the Thompson grid model, a graph layout is defined as an embedding within a two-dimensional grid. Horizontal and vertical tracks spaced by unit intervals make up a two-dimensional grid. An embedding that assigns nodes of G to points where horizontal and vertical tracks link, as well as an assignment of G's edges to grid pathways, characterises a graph G's layout. The routes on the layout are limited to grid tracks and cannot overlap for any length of time. Furthermore, nodes that are not next to each other may not be intersected by the paths.
Researcher proposed a planar representation of hyper tree network. They have proved the Identified theta mesh and the hyper tree are isomorphic. In comparison to the other, this representation will lower the number of crossings in a hyper tree VLSI layout. Hence, the planar representation of hyper tree network is an ideal network for VLSI layout.
Several academics have put forward VLSI layouts of tree-like machines in recent years. Researchers have provided a detailed description of the binary tree based layout algorithm. Researchers uses their algorithm in the act of foundation for X-tree and Hyper tree VLSI layout. They acquired the VLSI layout area O(ny'n) by modifying the algorithm. After a long gap, Researchers proposed a novel hyper tree representation to demonstrate that the hyper tree is planar. Using this model, we created an algorithm that reduces the VLSI layout area compared to Hyper tree's previous layout.
In the view of the forgoing discussion, it is clearly portrayed that there is a need to have a method for VLSI layout of hyper tree structure.
The present disclosure seeks to provide a method for VLSI layout of hyper tree structure for rapidly expandable multicomputer PC systems that integrates the facile enlargement of tree-like structures which has the conciseness of the hypercube structures.
In an embodiment, a method for VLSI layout of hyper tree structure is disclosed. The method includes laying out a Hyper tree in a very small space with any number of vertices to put out the Hyper tree on a plane in the manner. The method further includes imposing conditions for the plane. The method further includes changing direction in which the nodes are placed depending on the structure of the tree to minimize the Hyper tree structure ofthe VLSI layout.
In an embodiment, conditions for the plane comprises allowing only an n-dimensional hyper tree; assuming Thomson's VLSI computing model in the field analysis to have a single node or wire cross-over in the unit area, wherein one wire might cross each square's edge, bringing about a limit of four wires for every vertex; and depicting communications between vertices on a two-dimensional plane, horizontally or vertically.
In an embodiment, quantity of unit squares filled by wires and vertices rises to the all-out region.
In an embodiment, no corner connections are permitted.
An object of the present disclosure is to incorporate the prime aspects of the hypercube and binary tree.
Another object of the present disclosure is to integrate the facile enlargement of tree-like structures which has the conciseness of the hypercube structures.
Yet another object of the present invention is to deliver an expeditious and cost-effective method for VLSI layout of hyper tree structure.
To further clarify advantages and features of the present disclosure, a more particular description of the invention will be rendered by reference to specific embodiments thereof, which is illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. The invention will be described and explained with additional specificity and detail with the accompanying drawings.
These and other features, aspects, and advantages of the present disclosure will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein:
Figure lillustrates a flow chart of amethod for VLSI layout of hyper tree structure in accordance with an embodiment of the present disclosure; and Figure2illustrates a hyper tree structure of the VLSI layout in accordance with an embodiment of the present disclosure.
Further, skilled artisans will appreciate that elements in the drawings are illustrated for simplicity and may not have necessarily been drawn to scale. For example, the flow charts illustrate the method in terms of the most prominent steps involved to help to improve understanding of aspects of the present disclosure. Furthermore, in terms of the construction of the device, one or more components of the device may have been represented in the drawings by conventional symbols, and the drawings may show only those specific details that are pertinent to understanding the embodiments of the present disclosure so as not to obscure the drawings with details that will be readily apparent to those of ordinary skill in the art having benefit of the description herein.
For the purpose of promoting an understanding of the principles of the invention, reference will now be made to the embodiment illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended, such alterations and further modifications in the illustrated system, and such further applications of the principles of the invention as illustrated therein being contemplated as would normally occur to one skilled in the art to which the invention relates.
It will be understood by those skilled in the art that the foregoing general description and the following detailed description are exemplary and explanatory of the invention and are not intended to be restrictive thereof.
Reference throughout this specification to "an aspect", "another aspect" or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrase "in an embodiment", "in another embodiment" and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.
The terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process or method that comprises a list of steps does not include only those steps but may include other steps not expressly listed or inherent to such process or method. Similarly, one or more devices or sub-systems or elements or structures or components proceeded by "comprises...a" does not, without more constraints, preclude the existence of other devices or other sub-systems or other elements or other structures or other components or additional devices or additional sub-systems or additional elements or additional structures or additional components.
Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The system, methods, and examples provided herein are illustrative only and not intended to be limiting.
Embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings.
Referring to Figure 1, a flow chart of amethod for VLSI layout of hyper tree structure is illustrated in accordance with an embodiment of the present disclosure. At step 102, the method 100 includes laying out a Hyper tree in a very small space with any number of vertices to put out the Hyper tree on a plane in the manner.
At step 104, the method 100 includes imposing conditions for the plane.
At step 106, the method 100 includes changing direction in which the nodes are placed depending on the structure of the tree to minimize the Hyper tree structure ofthe VLSI layout.
In an embodiment, conditions for the plane includes allowing only an n-dimensional hyper tree. Then, assuming Thomson's VLSI computing model in the field analysis to have a single node or wire cross-over in the unit area, wherein one wire might cross each square's edge, bringing about a limit of four wires for every vertex. Thereafter, depicting communications between vertices on a two-dimensional plane, horizontally or vertically.
In an embodiment, quantity of unit squares filled by wires and vertices rises to the all-out region.
In an embodiment, no corner connections are permitted.
An object of the present disclosure is to incorporate the prime aspects of the hypercube and binary tree.
Figure 2 illustrates a hypertree structure of the VLSI layout in accordance with an embodiment of the present disclosure.A hypertree is one of the communication architecture for rapidly expandable multicomputer PC systems that integrates the facile enlargement of tree like structures which has the conciseness of the hypercube structures; in other words, it incorporates the prime aspects of the hypercube and binary tree. Both of these characteristics construct the design particularly appealing to multiprocessor networks, which can implement a complete system with a significant capacity of storage on a single VLSI chip. We discover a new topological representation of a hyper tree network. Resolving VLSI layout problems shows the significance of this representation. Using this representation, we have developed an algorithm for VLSI layout of k-dimensional hyper tree. The area of this layout is O(n , which is calculated using the Thompson formula.
The layout area is described most naturally as the "bounding-box" area around the layout, and is equal to the product of the number of vertical tracks as well as to the number of horizontal tracks containing a segment of the node or wire. Bisection width is an important attribute of graphs that influences the minimum layout area, according to Thompson. Thompson demonstrated that the layout area cannot be smaller than the square of the bisection width up to a constant factor. As a result, if the bisection width of a graph is known, a lower bound on the area can be easily derived. Since, the bisection width of hyper tree is constant, the lower bound for the area of VLSI layout of hyper tree is also constant.
The hyper tree is a full binary tree structure with an additional fault tolerance connection attached to every vertex. To put out this Hyper tree on a plane in the manner described, we devised an algorithm. The algorithm proposed in this capable of laying out a Hyper tree in a very small space with any number of vertices. The algorithm for designing the tree-like structure will be provided in this work, however, it has several restrictions. The limitations are due to the tree structure's complexity and are based on current VLSI masking and fabrication technologies. The following are the conditions imposed on the algorithm.
1. Only an n-dimensional Hyper tree is allowed.
2. Thomson's VLSI computing model has been assumed in the field analysis to have a single node or wire cross-over in the unit area. Furthermore, one wire might cross each square's edge, bringing about a limit of four wires for every vertex. The quantity of unit squares filled by wires and vertices rises to the all-out region.
3. Communications between vertices are only depicted on a two dimensional plane, horizontally or vertically. No corner connections are permitted.
The direction in which the nodes are placed changes depending on the structure of the tree. As a result, this approach minimizes the Hyper tree structure ofthe VLSI layout.
The drawings and the forgoing description give examples of embodiments. Those skilled in the art will appreciate that one or more of the described elements may well be combined into a single functional element. Alternatively, certain elements may be split into multiple functional elements. Elements from one embodiment may be added to another embodiment. For example, orders of processes described herein may be changed and are not limited to the manner described herein. Moreover, the actions of any flow diagram need not be implemented in the order shown; nor do all of the acts necessarily need to be performed. Also, those acts that are not dependent on other acts may be performed in parallel with the other acts. The scope of embodiments is by no means limited by these specific examples. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of embodiments is at least as broad as given by the following claims.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any component(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or component of any or all the claims.
Claims (4)
1. A method for VLSI layout of hyper tree structure, the method comprises:
laying out a Hyper tree in a very small space with any number of vertices to put out the Hyper tree on a plane in the manner; imposing conditions for the plane; and changing direction in which the nodes are placed depending on the structure of the tree to minimize the Hyper tree structure of the VLSI layout.
2. The method as claimed in claim 1, wherein conditions for the plane comprises:
allowing only an n-dimensional hyper tree; assuming Thomson's VLSI computing model in the field analysis to have a single node or wire cross-over in the unit area, wherein one wire might cross each square's edge, bringing about a limit of four wires for every vertex; and depicting communications between vertices on a two-dimensional plane, horizontally or vertically.
3. The method as claimed in claim 2, wherein quantity of unit squares filled by wires and vertices rises to the all-out region.
4. The method as claimed in claim 2, wherein no corner connections are permitted.
laying out a Hypertree in a very small space with any number of vertices to put out the Hypertree on 102 a plane in the manner 104 imposing conditions for the plane
changing direction in which the nodes are placed depending on the structure of the tree to 106 minimize the Hypertree structure of the VLSI layout
Figure 1
Figure 2
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| AU2021106353A AU2021106353A4 (en) | 2021-08-21 | 2021-08-21 | A method for vlsi layout of hypertree structure |
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