CN104424369B - The sequential evaluation method of netlist after a kind of FPGA mappings - Google Patents
The sequential evaluation method of netlist after a kind of FPGA mappings Download PDFInfo
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Abstract
The present invention proposes a kind of sequential evaluation method of netlist after FPGA mappings, including：For the single hop line between source block unit and remittance module unit, according to the type of the source block unit and remittance module unit, the type of the single hop line is determined；According to the type of the single hop line, single hop line is fallen into described in temporal model library file global reference time delay and global crowding scope are searched；The local congestion degree of the single hop line is calculated, according to the local congestion degree, the local congestion degree scope and local reference time delay belonging to the single hop line is determined；Local congestion degree scope and local reference time delay according to belonging to the single hop line, calculate the delay value of the single hop line.Thus the maximum operating frequency before FPGA placement-and-routings can be estimated and time constraints file is generated, the time constraints set instead of user can obtain more preferably highest frequency as the input of placement-and-routing's instrument with less iterations.
Description
Technical field
The present invention relates to the sequential evaluation method of netlist behind chip layout field, more particularly to a kind of FPGA mappings.
Background technology
Field programmable gate array (Field Programmable Gate Array, FPGA) software can reach
Highest frequency be fpga chip performance a measurement index, the initial clock constraint that it is set with user has much relations,
Different initial clock constraints may cause the highest frequency being finally reached to be very different, and the estimation of FPGA sequential is general in cloth
Carried out after office's wiring.The estimation of FPGA sequential is done before placement-and-routing, physical bit on the piece due to lacking module unit and interconnection resource
Confidence ceases, and to reach that less error has very big difficulty, the research in the field substantially belongs to space state in current industry.
The content of the invention
It is an object of the invention to provide it is a kind of the gate level circuit that user designs is integrated and storehouse map after formed
Netlist carries out the method for sequential estimation, so as to generate more suitably time constraints file, layout is used as instead of user clock constraint
The input of wiring tool, enables FPGA softwares to obtain more preferably highest frequency with less iterations.
To achieve the above object, in a first aspect, the invention provides a kind of FPGA mapping after netlist sequential evaluation method,
This method includes：
For the single hop line between source block unit and remittance module unit, according to the class of the source block unit and remittance module unit
Type, determines the type of the single hop line；
According to the type of the single hop line, the global delay that single hop line described in temporal model library file is fallen into is searched
Scope and global crowding scope；
The local congestion degree of the single hop line is calculated, according to the local congestion degree, is determined belonging to the single hop line
Local congestion degree scope and local reference time delay；
Local congestion degree scope and local reference time delay according to belonging to the single hop line, calculate the single hop line
Delay value.
In the above-mentioned methods, the type according to the single hop line, searches single hop described in temporal model library file
The global reference time delay and global crowding scope that line is fallen into include：
According to the source block unit in the number and chip of the source block unit of all kinds of lines recorded in default netlist
Sum, calculates the utilization rate of the source block unit of all kinds of lines；
According to the remittance module unit in the number and chip of the remittance module unit of all kinds of lines recorded in default netlist
Sum, calculates the utilization rate of the remittance module unit of all kinds of lines；
According to the utilization rate of the type of the single hop line, the utilization rate of source block unit and remittance module unit, when searching described
Single hop line is fallen into described in sequence model library file global reference time delay and global crowding scope.
In the above-mentioned methods, the local congestion degree for calculating the single hop line includes：
Calculating source block unit is fanned out to crowding with remittance module unit；
According to the crowding that is fanned out to of the source block unit and remittance module unit, between the calculating source block unit and remittance module unit
The local congestion degree of single hop line.
In the above-mentioned methods, the source block unit and the crowding that is fanned out to of remittance module unit of calculating includes：
Crowding is fanned out to according to K1, K2, K3, K4 and K5 calculating source block unit；
Crowding is fanned out to according to K0, K2, K3, K4 and K5 calculating remittance module unit；
Wherein, K0 for source block unit fan out unit in, with converge module unit type identical number；K1 is remittance module unit
In fan out unit, add 1 again with source block cell type identical number（Source node unit is in itself）；K2 fans for the fan-in of source block unit
Go out unit sum；K3 is total for the fan-in fan out unit of remittance module unit；K4 is that the number of unit during K2 gathers is subtracted in K0 set
Number of unit；K5 subtracts the number of unit in K1 set for the number of unit in K3 set.
Second aspect, the invention provides the sequential evaluation method of netlist after a kind of FPGA mappings, this method includes：
According to the type of source block unit and remittance module unit, the single hop line between source block unit and remittance module unit is divided
Class；
For each class single hop line in all kinds of single hop lines, marked according to the netlist generated after placement-and-routing in file
The JB hop count that each single hop line passes through on chip, is divided into multiple hop count set；
According to the local congestion degree of single hop line in each set, the local congestion degree model of each hop count set is determined
Enclose；
According to the delay value after the placement-and-routing of single hop line in each set, the part of each hop count set is determined
Reference time delay；
According to the local reference time delay respectively gathered and local crowding scope, temporal model library file is set up.
In the above-mentioned methods, the multiple hop count set refers to 3 hop count set.
In the above-mentioned methods, each class single hop line being directed in all kinds of single hop lines, according to raw after placement-and-routing
Into netlist mark file in the JB hop count that passes through on chip of each single hop line, being divided into 3 hop count set includes：
For each class single hop line in all kinds of single hop lines, marked according to the netlist generated after placement-and-routing in file
All kinds of lines are divided into N grades by the difference for the JB hop count that each single hop line passes through on chip, and the single hop counted in each shelves connects
Line sum, using i-th grade of corresponding JB hop count with maximum single hop line sum as typical hop count j, and counts i-th
The minimum delay value of the first of single hop line and the first maximum delay value in shelves；
Shelves of the JB hop count more than j that all single hop lines pass through on chip are traveled through, all single hops in each shelves are calculated
The geometric average delay value of line；
The M shelves that the geometric average delay value of all single hop lines is more than the first maximum delay value are classified as greatly
Hop count set, remaining N-M shelves are classified as typical hop count set；
According to big hop count set and typical hop count intersection of sets collection, N number of shelves are reclassified as the conjunction of jete manifold, allusion quotation
The set of type hop count and big hop count set.
In the above-mentioned methods, the local congestion degree according to single hop line in each set, determines each hop count
The local congestion degree scope of set includes：
According to the local congestion degree of single hop line in each set, the minimum office of single hop line in each set is counted
Portion's crowding and maximum local congestion degree, and calculate the geometric average local congestion degree of all single hop lines in each set,
The minimum local congestion degree, maximum local congestion degree and geometric average local congestion degree constitute the local congestion degree model of each set
Enclose.
In the above-mentioned methods, the delay value according to single hop line in each set, determines each hop count set
Local reference time delay include：
According to the delay value after the placement-and-routing of single hop line in each set, single hop line in each set is counted
The second minimum delay value and the second maximum delay value, and calculate the geometric average delay of all single hop lines in each set
Value, the described second minimum delay value, the second maximum delay value and geometric average delay value constitute the local reference time delay of each set.
The sequential evaluation method of netlist, completes once to be laid out first on fpga chip after the FPGA mappings that the present invention is provided
Wiring, is then based on the delay value and local congestion degree of each single hop line after this time wiring, sets up temporal model library file, then
To any single hop line in netlist, by matching its corresponding local congestion degree scope and part in temporal model library file
Reference time delay, calculates the delay value of the single hop line.
Brief description of the drawings
Below by drawings and examples, technical scheme is described in further detail.
Fig. 1 is the sequential evaluation method flow chart of netlist after the FPGA mappings that the embodiment of the present invention one is provided;
Fig. 2 is a kind of structural representation of netlist;
Fig. 3 is the sequential evaluation method flow chart of netlist after the FPGA mappings that the embodiment of the present invention two is provided.
Embodiment
The circuit that user is designed integrated and storehouse mapping after form netlist, so that elementary cell can also be obtained
And their annexation, wherein, elementary cell includes：Look-up table, register, memory, input and output etc., substantially singly
Line between member is referred to as single hop line, a placement-and-routing is completed generally on fpga chip, according to the knot of the placement-and-routing
Fruit just can uniquely determine the delay value of any single hop line.
Fig. 1 is the sequential evaluation method flow chart of netlist after the FPGA mappings that the embodiment of the present invention one is provided.Such as Fig. 1 institutes
Show, method provided in an embodiment of the present invention includes：
Step 101, for the single hop line between source block unit and remittance module unit, according to the source block unit and the block list that converges
The type of member, determines the type of the single hop line.
It can be divided into two classes for the line recorded in default netlist：Hardwired and non-hardwired, hardwired refer to
Fpga chip upper port is uniquely determined to the line between port；Non-hardwired refer to fpga chip upper port and port it
Between line can have various ways, usual sequential algorithm for estimating is directed to the non-hardwired in default netlist.It is default
The elementary cell recorded in netlist includes：LUT, LUTC, REG and IO etc. are several, and the line in default netlist is according to connection
The difference of the source node of the line and sink nodes type and polytype can be divided into, i.e., any one single hop line is saved according to source
The type of point and sink nodes, can uniquely determine the type of the single hop line, be exemplified as, LUT-LUT, LUTC-LUT, REG-
LUT and IO-LUT etc..
It should be noted that after to the single hop line classification in default netlist, it is possible to calculate the source section per class line
The utilization rate of point and the utilization rate of sink nodes, the utilization rate of source node can reflect the global congestion status of source node resource, converge
The utilization rate of node can reflect the global congestion status of sink nodes resource, be exemplified as, and above-mentioned source, sink nodes are LUT, and it
Utilization rate be 3%, then it on chip is not also at present very congestion to illustrate such line.In a kind of specific embodiment, source section
The formula of the utilization rate of point and sink nodes is as follows：
In the utilization rate of source node=default netlist on number/chip of source node source node number（1）
In the utilization rate of sink nodes=default netlist on number/chip of sink nodes sink nodes number（2）
According to formula（1）With（2）After calculating obtains the source node of every class line and the utilization rate of sink nodes, in conjunction with
The delay value of single hop line after a placement-and-routing is completed on fpga chip, it is possible to uniquely determine minimum in every class line
Delay value and maximum delay value.
Step 102, according to the type of the single hop line, search what single hop line described in temporal model library file was fallen into
Global reference time delay and global crowding scope.
Specifically, for any one single hop line, the type of the single hop line is assured that according to step 101, then is tied
Close the utilization rate of the affiliated line type of the single hop line, it is possible to find what the single hop line in temporal model library file was fallen into
Global reference time delay and global crowding scope, it is as follows：
It should be noted that have recorded two kinds of line, each group in above-mentioned temporal model library file<segment>
</segment>It is expressed as a type of line.With first group<segment></segment>Exemplified by the temporal model storehouse
File is explained, OK<segment src=″lut″dst=″lut″>Represent type be LUT-LUT line, i.e., source node and
The type of sink nodes is LUT, OK<senario util=″(0.03 0.03)″>Represent the utilization of source node and sink nodes
Rate is 0.03, OK<k conf=″0.5″min=″(0.100 0.167 0.189)″typical=”(0.192 0.211
0.232)”max=″(0.235 0.235 0.235)″/>Represent " min ", " typical " and " max " of LUT-LUT type lines
The corresponding local congestion degree scope of three set, wherein, three values each gathered represent the corresponding minimum office of the set respectively
The crowded angle value in portion, geometric average local congestion angle value and maximum local congestion angle value, OK<delay min=″(156 187 208)
(156 187 208)″typ=″(218 269 376)(218 269 376)″max=″(389 450 501)(389 450
501)″/>The corresponding delay value scope of " min ", " typical " and " max " three set is represented, wherein, three each gathered
Value represents the corresponding minimum delay value of the set, geometric average delay value and maximum delay value respectively.Specifically, for any one
Single hop line, if the type LUT-LUT of the single hop line, and the utilization rate of source node and sink nodes is 0.03, then basis
The type and source node and the utilization rate of sink nodes of the single hop line, it is possible to find this in above-mentioned temporal model library file
Global reference time delay and global crowding scope that single hop line is fallen into, its global reference time delay and global crowding scope are as above
State in temporal model library file shown in 4-7 rows.
Step 103, the local congestion degree of the single hop line is calculated, according to the local congestion degree, the single hop is determined
Local congestion degree scope and local reference time delay belonging to line.
Specifically, before the local congestion degree of single hop line is calculated, the fan of the source node of the single hop line is first calculated
Go out crowding and sink nodes is fanned out to crowding, is fanned out to crowding according to source node and sink nodes, calculates source node and saved with converging
The local congestion degree of single hop line between point.Fig. 2 is a kind of structural representation of netlist.As shown in Fig. 2 being saved to source node with converging
Single hop line between point, can describe its local congestion degree state by 6 coefficients：K0 is the fan out unit of source node
In, with sink nodes cell type identical number；K1 for sink nodes fan out unit in, with source node unit type identical number
Mesh adds 1 again（Source node unit is in itself）；K2 is total for the fan-in fan out unit of source node；K3 is the fan-in fan out unit of sink nodes
Sum；K4 subtracts the number of unit in K0 set for the number of unit in K2 set；K5 is that the number of unit during K3 gathers is subtracted
Number of unit in K1 set.
K0=2, K1=2, K2=3, K3=5, K4=1, K5=3 can be obtained from Fig. 2.
Specifically, described by setting up equation below the local congestion degree of the single hop line and K0, K1, K2, K3, K4,
Relation between K5.
Wherein, x1 and x2 represent the local congestion degree one-dimensional coordinate of source node and sink nodes respectively, try to achieve x1=x2=1.
When | x1-x2 | when=0, local congestion degree is maximum.
As K0=1, crowding is fanned out to according to what equation below tried to achieve source node：
As K1=1, crowding is fanned out to according to what equation below can try to achieve sink nodes：
Obtain being fanned out to after crowding for source node and sink nodes, so that it may which source node and sink nodes are tried to achieve according to equation below
Between single hop line local congestion degree：
kdegree=(src_kdegree+sink_kdegree)/2∈[0,1] （6）
It should be noted that according to formula（6）After the local congestion degree for trying to achieve single hop line, it is possible in above-mentioned sequential
The set of the single hop line is determined in model library file.It is exemplified as, belongs to LUT-LUT types, and source, the utilization rate of sink nodes are equal
Local congestion degree for 0.03 a certain single hop line is 0.22, passes through the minimum local congestion degree for gathering 0.22 and " min "
Value 0.100 and maximum local congestion angle value 0.189 compare, it is known that the single hop line belongs to " typical " set or " max " collection
Close, by further comparing with " typical " minimum local congestion angle value 0.192 gathered and maximum local congestion angle value 0.232
Relatively understand, the local congestion degree scope of the single hop line is (0.192 0.211 0.232), and corresponding local reference time delay is
(218 269 376)。
Step 104, local congestion degree scope according to belonging to the single hop line and local reference time delay, calculate the list
The delay value of section line.
Specifically, it is 0.22 to the local congestion degree according to the single hop line tried to achieve in step 103, and single hop line belongs to
" typical " gathers, and then judges whether tried to achieve local congestion angle value is less than or equal to " typical " and gathers corresponding part
Geometric average local congestion angle value in crowding scope, if less than equal to then according to the corresponding part of " typical " set
Geometric average local congestion angle value and minimum local congestion angle value in crowding scope, and " typical " set are corresponding
Geometric average delay value and minimum delay value in local reference time delay, try to achieve the delay value of the single hop line；If it is greater, then
Gather the geometric average local congestion angle value and maximum local congestion degree in corresponding local congestion degree scope according to " typical "
Value, and " typical " gather the geometric average delay value and maximum delay value in corresponding local reference time delay, try to achieve the list
The delay value of section line.It is exemplified as, because the local congestion angle value of the single hop line is 0.22>0.211, then according to following public affairs
Formula tries to achieve the delay value of the single hop line：
Tfinal=269+(376–269)*β （7）
Wherein, TfinalRepresent the delay value of the single hop line, β=(0.22-0.211)/(0.232-0.211).
Fig. 3 is the sequential evaluation method flow chart of netlist after the FPGA mappings that the embodiment of the present invention two is provided.Such as Fig. 3 institutes
Show, method provided in an embodiment of the present invention includes：
Step 301, according to the type of source block unit and remittance module unit, the single hop between source block unit and remittance module unit is connected
Line is classified.
The elementary cell recorded in default netlist includes：LUT, LUTC, REG and IO etc. are several, and in default netlist
Line according to connect the line source node and sink nodes type difference and polytype can be divided into, i.e., any one single hop
Line, according to the type of source node and sink nodes, can uniquely determine the type of the single hop line, be exemplified as, LUT-LUT,
LUTC-LUT, REG-LUT or IO-LUT etc., equally, can be divided into LUT-LUT, LUTC- to all single hop lines in default netlist
The several types such as LUT, REG-LUT and IO-LUT.
Step 302, for each class single hop line in all kinds of single hop lines, according to the netlist mark generated after placement-and-routing
The JB hop count that each single hop line passes through on chip in explanatory notes part, is divided into multiple hop count set.
In a kind of specific embodiment, three hop count set can be divided into, specifically, for each in all kinds of lines
Class single hop line, the line that each single hop line passes through on chip in file is marked according to according to the netlist generated after placement-and-routing
All kinds of lines are divided into N grades by the difference of box hop count, wherein, it have recorded netlist in the netlist mark file generated after placement-and-routing
In the selector switch node set passed through between any single hop line, it can thus be concluded that the selection passed through to any single hop line
Device switching node number, i.e. JB hop count, count the single hop line sum in each shelves, by with maximum single hop line sum
I-th grade of corresponding JB hop count as typical hop count j, and count single hop line in i-th grade the first minimum delay value and
First maximum delay value；Shelves of the JB hop count more than j that all single hop lines pass through on chip are traveled through, institute in each shelves is calculated
There is the geometric average delay value of single hop line；The geometric average delay value of all single hop lines is more than described first maximum
M shelves of delay value are classified as big hop count set（" max " gathers）, remaining N-M shelves are classified as typical hop count set, i.e.,
（" typical " gathers）, typical hop count set is referred to as middle hop count set, have recorded belonging to most single hop line
Local congestion degree scope and local reference time delay；According to big hop count set and typical hop count intersection of sets collection, by N number of shelves
It is reclassified as the conjunction of jete manifold（" min " gathers）, typical hop count set and big hop count set.
Step 303, according to the local congestion degree of single hop line in each set, the part of each hop count set is determined
Crowding scope.
To according to the conjunction of jete manifold, typical hop count set and the big hop count set determined in step 302, according in each set
The local congestion degree of single hop line, counts the minimum local congestion degree KMIN of single hop line and maximum local congestion degree in each set
KMAX, and it is each to calculate geometric average local congestion degree KGEO, KMIN, KMAX and KGEO composition of all single hop lines in each set
The local congestion degree scope of set, specifically, it is [MIN_KMIN, MIN_ that jete manifold, which closes corresponding local congestion degree scope,
KGEO, MIN_KMAX], the corresponding local congestion degree scope of typical hop count set is [TYP_KMIN, TYP_KGEO, TYP_
KMAX], the corresponding local congestion degree scope of big hop count set is [MAX_KMIN, MAX_KGEO, MAX_KMAX].
Step 304, according to the delay value after the placement-and-routing of single hop line in each set, each hop count collection is determined
The local reference time delay of conjunction.
To according to the conjunction of jete manifold, typical hop count set and the big hop count set determined in step 302, according in each set
Delay value after the placement-and-routing of single hop line, counts the second minimum delay value DMIN and second of single hop line in each set most
Big delay value DMAX, and calculate all single hop lines in each set geometric average delay value DGEO, DMIN, DMAX and
DGEO constitutes the local reference time delay of each set, specifically, jete manifold close corresponding local reference time delay for [MIN_DMIN,
MIN_DGEO, MIN_DMAX], the corresponding local reference time delay of typical hop count set is [TYP_DMIN, TYP_DGEO, TYP_
DMAX], the corresponding local reference time delay of big hop count set is [MAX_DMIN, MAX_DGEO, MAX_DMAX].
Step 305, according to the local reference time delay respectively gathered and local crowding scope, temporal model library text is set up
Part.
According to step 301 all single hop lines in default netlist are divided into LUT-LUT, LUTC-LUT, REG-LUT and
After the several types such as IO-LUT, further in accordance with source node in step 101 and the computational methods of sink nodes utilization rate, calculate after classification
Every class line source node utilization rate and the utilization rate of sink nodes.Specifically, according to the utilization of the source node of every class line
The utilization rate of rate and sink nodes, and the often corresponding local congestion degree scope of three hop count set and part of the division of class line
Reference time delay, can build temporal model library file as follows：
It should be noted that row<segment src=″lut″dst=″lut″>The line that type is LUT-LUT is represented, i.e.,
The type of source node and sink nodes is LUT, OK<senario util=″(0.030.03)″>Represent source node and sink nodes
Utilization rate be 0.03, OK<kconf=″0.5″min=″(0.100 0.167 0.189)″typical=”(0.192 0.211
0.232)”max=″(0.235 0.235 0.235)″/>Represent " min ", " typical " and " max " of LUT-LUT type lines
The corresponding local congestion degree scope of three set, wherein, three values each gathered represent the corresponding minimum office of the set respectively
The crowded angle value in portion, geometric average local congestion angle value and maximum local congestion angle value, OK<delay min=″(156 187 208)
(156 187 208)″typical=″(218 269 376)(218 269 376)″max=″(389 450 501)(389 450
501)″/>The corresponding delay value scope of " min ", " typical " and " max " three set is represented, wherein, three each gathered
Value represents the corresponding minimum delay value of the set, geometric average delay value and maximum delay value respectively.
Step 306- steps 309 are identical with step 101-104.
It should be noted that after to establishing temporal model library file according to step 301-305, for any one single hop
Line, the delay value of the single hop line can be tried to achieve according to step 101-104.
The sequential evaluation method of netlist, completes once to be laid out first on fpga chip after the FPGA mappings that the present invention is provided
Wiring, is then based on the delay value and local congestion degree of each single hop line after this time wiring, sets up temporal model library file, then
To any single hop line in netlist, by matching its corresponding local congestion degree scope and part in temporal model library file
Reference time delay, calculates the delay value of the single hop line, so as to generate more suitably time constraints file, is constrained instead of user clock
As the input of placement-and-routing's instrument, FPGA softwares are enable to obtain more preferably highest frequency with less iterations.Solve
In the prior art, sequential estimation is done before placement-and-routing, physical location information on the piece due to lacking module unit and interconnection resource,
Reach the problem of smaller error has great difficulty.
Professional should further appreciate that, each example described with reference to the embodiments described herein
Unit and algorithm steps, can be realized with electronic hardware, computer software or the combination of the two, hard in order to clearly demonstrate
The interchangeability of part and software, generally describes the composition and step of each example according to function in the above description.
These functions are performed with hardware or software mode actually, depending on the application-specific and design constraint of technical scheme.
Professional and technical personnel can realize described function to each specific application using distinct methods, but this realize
It is not considered that beyond the scope of this invention.
The method that is described with reference to the embodiments described herein can use hardware, computing device the step of algorithm
Software module, or the two combination are implemented.Software module can be placed in random access memory（RAM）, internal memory, read-only storage
（ROM）, electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field
In any other form of storage medium well known to interior.
Above-described embodiment, has been carried out further to the purpose of the present invention, technical scheme and beneficial effect
Describe in detail, should be understood that the embodiment that the foregoing is only the present invention, be not intended to limit the present invention
Protection domain, within the spirit and principles of the invention, any modification, equivalent substitution and improvements done etc. all should be included
Within protection scope of the present invention.
Claims (8)
1. the sequential evaluation method of netlist after a kind of FPGA mappings, including：
For source block unit and converge module unit between single hop line, according to the source block unit and converge module unit type, really
The type of the fixed single hop line；
According to the sum of the source block unit in the number and chip of the source block unit of all kinds of lines recorded in default netlist,
Calculate the utilization rate of the source block unit of all kinds of lines；
According to the sum of the remittance module unit in the number and chip of the remittance module unit of all kinds of lines recorded in default netlist,
Calculate the utilization rate of the remittance module unit of all kinds of lines；
According to the utilization rate of the type of the single hop line, the utilization rate of source block unit and remittance module unit, the sequential mould is searched
Global reference time delay and global crowding scope that single hop line described in type library file is fallen into；
The local congestion degree of the single hop line is calculated, according to the local congestion degree, the office belonging to the single hop line is determined
Portion's crowding scope and local reference time delay；
Local congestion degree scope and local reference time delay according to belonging to the single hop line, calculate the delay of the single hop line
Value.
2. the sequential evaluation method of netlist after FPGA mappings according to claim 1, it is characterised in that described in the calculating
The local congestion degree of single hop line includes：
Calculating source block unit is fanned out to crowding with remittance module unit；
According to the crowding that is fanned out to of the source block unit and remittance module unit, single hop between the calculating source block unit and remittance module unit
The local congestion degree of line.
3. the sequential evaluation method of netlist after FPGA mappings according to claim 2, it is characterised in that the calculating source block
The crowding that is fanned out to of unit and remittance module unit includes：
Crowding is fanned out to according to K1, K2, K3, K4 and K5 calculating source block unit；
Crowding is fanned out to according to K0, K2, K3, K4 and K5 calculating remittance module unit；
Wherein, K0 for source block unit fan out unit in, with converge module unit type identical number；K1 is fanned out to for remittance module unit
In unit, add 1 again with source block cell type identical number；K2 is total for the fan-in fan out unit of source block unit；K3 is remittance block
The fan-in fan out unit sum of unit；K4 subtracts the number of unit in K0 set for the number of unit in K2 set；K5 is K3 collection
Number of unit in conjunction subtracts the number of unit in K1 set.
4. the sequential evaluation method of netlist after a kind of FPGA mappings, including：
According to the type of source block unit and remittance module unit, the single hop line between source block unit and remittance module unit is classified；
For each class single hop line in all kinds of single hop lines, each list in file is marked according to the netlist generated after placement-and-routing
The JB hop count that section line passes through on chip, is divided into multiple hop count set；
According to the local congestion degree of single hop line in each set, the local congestion degree scope of each hop count set is determined；
According to the delay value after the placement-and-routing of single hop line in each set, the local delay of each hop count set is determined
Scope；
According to the local reference time delay respectively gathered and local crowding scope, temporal model library file is set up.
5. the sequential evaluation method of netlist after FPGA mappings according to claim 4, it is characterised in that the multiple hop count
Set refers to 3 hop count set.
6. the sequential evaluation method of netlist after FPGA mappings according to claim 5, it is characterised in that described for all kinds of
Each class single hop line in single hop line, according to each single hop line in the netlist mark file generated after placement-and-routing in chip
The JB hop count of upper process, being divided into 3 hop count set includes：
For each class single hop line in all kinds of single hop lines, each list in file is marked according to the netlist generated after placement-and-routing
All kinds of lines are divided into N grades by the difference for the JB hop count that section line passes through on chip, and the single hop line counted in each shelves is total
Number, using i-th grade of corresponding JB hop count with maximum single hop line sum as typical hop count j, and is counted in i-th grade
The minimum delay value of the first of single hop line and the first maximum delay value；
Shelves of the JB hop count more than j that all single hop lines pass through on chip are traveled through, all single hop lines in each shelves are calculated
Geometric average delay value；
The M shelves that the geometric average delay value of all single hop lines is more than the first maximum delay value are classified as big hop count
Set, remaining N-M shelves are classified as typical hop count set；
According to big hop count set and typical hop count intersection of sets collection, N number of shelves are reclassified as the conjunction of jete manifold, typical case and jumped
Manifold is closed and big hop count set.
7. the sequential evaluation method of netlist after FPGA mappings according to claim 4, it is characterised in that described in the basis
The local congestion degree of single hop line in each set, determining the local congestion degree scope of each hop count set includes：
According to the local congestion degree of single hop line in each set, the minimum part for counting single hop line in each set is gathered around
Degree and maximum local congestion degree are squeezed, and calculates the geometric average local congestion degree of all single hop lines in each set, it is described
Minimum local congestion degree, maximum local congestion degree and geometric average local congestion degree constitute the local congestion degree scope of each set.
8. the sequential evaluation method of netlist after FPGA mappings according to claim 4, it is characterised in that described in the basis
Delay value in each set after the placement-and-routing of single hop line, determining the local reference time delay of each hop count set includes：
According to the delay value after the placement-and-routing of single hop line in each set, the of single hop line in each set is counted
Two minimum delay values and the second maximum delay value, and calculate the geometric average delay value of all single hop lines in each set,
Described second minimum delay value, the second maximum delay value and geometric average delay value constitute the local reference time delay of each set.
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