CN116127913A

CN116127913A - Power consumption analysis method and device for design of integrated circuit chip

Info

Publication number: CN116127913A
Application number: CN202310076413.7A
Authority: CN
Inventors: 王毓千; 高鹏鹏; 晋大师; 梁洪昌
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2023-01-17
Filing date: 2023-01-17
Publication date: 2023-05-16

Abstract

A power consumption analysis method and a power consumption analysis device for designing an integrated circuit chip, a design method of power supply integrity of the integrated circuit chip, an electronic device and a storage medium. The power consumption analysis method comprises the following steps: mapping operation is carried out on the register transmission level simulation waveform file of the integrated circuit chip, and a gate level netlist waveform file corresponding to the register transmission level simulation waveform file is obtained; performing power consumption analysis operation on the integrated circuit chip according to the gate-level netlist waveform file to obtain a power consumption waveform file of the integrated circuit chip; and obtaining a current characteristic file representing the current characteristic of the integrated circuit chip according to the power consumption waveform file of the integrated circuit chip. The power consumption analysis method can obtain the power consumption and the current characteristic of the integrated circuit chip at the early stage of the design process of the integrated circuit chip, is beneficial to reducing the power consumption of the integrated circuit chip earlier, solves the voltage drop problem of the integrated circuit chip, optimizes the chip design and reduces the design cost.

Description

Power consumption analysis method and device for design of integrated circuit chip

Technical Field

Embodiments of the present disclosure relate to a power consumption analysis method and a power consumption analysis apparatus for design of an integrated circuit chip, a design method of power integrity of an integrated circuit chip, an electronic device, and a non-transitory computer-readable storage medium.

Background

With the continuous upgrading of semiconductor technology, the design scale of high-performance chips such as a central processing unit (Central Processing Unit, CPU) and a graphics processor (Graphics Processing Unit, GPU) is continuously increased, the number of transistors on a chip per unit area is increased, and the complexity of chip design is multiplied.

With the increase of chip size and the increase of integration level, the power consumption of the chip is larger and larger, and the excessive power consumption not only can cause huge pressure of a power supply network, but also can cause the problem of voltage Drop (IR Drop) of the chip in the working process. The voltage drop problem may cause the operating voltage of the chip to be insufficient to drive the logic gate to flip, or may cause the clock frequency to be limited, thereby seriously affecting the performance of the chip.

Disclosure of Invention

At least one embodiment of the present disclosure provides a power consumption analysis method for design of an integrated circuit chip, the power consumption analysis method including: mapping the register transmission-level simulation waveform file of the integrated circuit chip to obtain a gate-level netlist waveform file corresponding to the register transmission-level simulation waveform file; performing power consumption analysis operation on the integrated circuit chip according to the gate-level netlist waveform file to obtain a power consumption waveform file of the integrated circuit chip; and obtaining a current characteristic file representing the current characteristic of the integrated circuit chip according to the power consumption waveform file of the integrated circuit chip.

For example, in the power consumption analysis method provided in at least one embodiment of the present disclosure, the mapping operation is performed on the register transmission level simulation waveform file of the integrated circuit chip to obtain a gate level netlist waveform file corresponding to the register transmission level simulation waveform file, including: and mapping the register transmission level of the integrated circuit chip into a corresponding gate level netlist according to the naming mapping file to obtain the gate level netlist waveform file corresponding to the register transmission level simulation waveform file.

For example, in the power consumption analysis method provided in at least one embodiment of the present disclosure, performing a power consumption analysis operation on the integrated circuit chip according to the gate-level netlist waveform file to obtain a power consumption waveform file of the integrated circuit chip includes: performing the power consumption analysis operation according to the obtained gate-level netlist waveform file by using a power consumption analysis tool to obtain a time-based power consumption waveform file of the integrated circuit chip;

the obtaining a current characteristic file representing the current characteristic of the integrated circuit chip according to the power consumption waveform file of the integrated circuit chip comprises the following steps: and obtaining a current piecewise linear file representing the current characteristic of the integrated circuit chip according to the time-based power consumption waveform file and the arrangement of the voltage domains of the integrated circuit chip.

For example, in the power consumption analysis method provided in at least one embodiment of the present disclosure, the performing, by a power consumption analysis tool, the power consumption analysis operation according to the obtained gate level netlist waveform file, to obtain a time-based power consumption waveform file of the integrated circuit chip includes: acquiring a power consumption analysis input file set comprising the gate-level netlist waveform file; and performing the power consumption analysis operation on the integrated circuit chip according to the power consumption analysis input file set by a power consumption analysis tool so as to generate the time-based power consumption waveform file of the integrated circuit chip.

For example, the power consumption analysis method provided in at least one embodiment of the present disclosure further includes: setting a sampling time interval according to the clock of the gate-level netlist waveform file; and generating a power consumption waveform file based on time according to the sampling time interval.

For example, in the power consumption analysis method provided in at least one embodiment of the present disclosure, the power consumption analysis input file set further includes a standard latency format file, a library file, a data file, and a script file.

For example, in a power consumption analysis method provided in at least one embodiment of the present disclosure, the integrated circuit chip includes a plurality of voltage domains, and the obtaining a current piecewise linear file representing the current characteristic of the integrated circuit chip according to the time-based power consumption waveform file and an arrangement of the voltage domains of the integrated circuit chip includes: acquiring working voltage of each of the plurality of voltage domains and a plurality of power consumption waveform files based on time; and respectively obtaining a plurality of current piecewise linear files of the voltage domains according to the plurality of power consumption waveform files based on time for each of the voltage domains.

For example, the power consumption analysis method provided in at least one embodiment of the present disclosure further includes: selecting a plurality of working conditions of the integrated circuit chip and acquiring a time-based power consumption waveform file corresponding to the plurality of working conditions; and obtaining a plurality of current piecewise linear files of the voltage domains according to the time-based power consumption waveform files corresponding to the working conditions.

For example, in the power consumption analysis method provided in at least one embodiment of the present disclosure, the plurality of operating conditions includes a best case, a normal case and a worst case.

For example, in the power consumption analysis method provided in at least one embodiment of the present disclosure, the integrated circuit chip includes a plurality of modules, and the power consumption analysis method further includes: integrating a plurality of current piecewise linear files of the voltage domains to obtain current piecewise linear files of the modules; and integrating the current piecewise linear files of the modules to obtain the current piecewise linear file of the whole integrated circuit chip.

At least one embodiment of the present disclosure also provides a method for designing power integrity of an integrated circuit chip, the method comprising: obtaining a current characteristic file of the integrated circuit chip according to a power consumption analysis method provided by at least one embodiment of the present disclosure; and adjusting or designing the power supply module for the integrated circuit chip according to the current characteristic file of the integrated circuit chip.

For example, in a design method provided by at least one embodiment of the present disclosure, the power module includes a power supply and a voltage stabilizing module.

At least one embodiment of the present disclosure also provides a power consumption analysis apparatus for design of an integrated circuit chip, the power consumption analysis apparatus including: the mapping module is configured to perform mapping operation on the register transmission level simulation waveform file of the integrated circuit chip to obtain a gate level netlist waveform file corresponding to the register transmission level simulation waveform file; the power consumption analysis module is configured to perform power consumption analysis operation on the integrated circuit chip according to the gate-level netlist waveform file to obtain a power consumption waveform file of the integrated circuit chip; and the current characteristic acquisition module is configured to obtain a current characteristic file representing the current characteristic of the integrated circuit chip according to the power consumption waveform file of the integrated circuit chip.

At least one embodiment of the present disclosure also provides an electronic device comprising a memory non-transitory storing computer-executable instructions; a processor configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement the power consumption analysis method of any embodiment of the present disclosure or the design method of any embodiment of the present disclosure.

At least one embodiment of the present disclosure also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions that, when executed by a processor, implement the power consumption analysis method according to any embodiment of the present disclosure or the design method according to any embodiment of the present disclosure.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

FIG. 1 is a flow chart illustrating a method for analyzing power consumption for a design of an integrated circuit chip according to at least one embodiment of the present disclosure;

FIG. 2 illustrates a schematic diagram of a mapping operation provided by at least one embodiment of the present disclosure;

FIG. 3 is a flow chart of a method for analyzing power consumption for designing an integrated circuit chip according to another embodiment of the present disclosure;

FIG. 4 is a flow chart illustrating a method for designing power integrity of an integrated circuit chip according to at least one embodiment of the present disclosure;

FIG. 5 is a schematic block diagram of a power consumption analysis apparatus for design of an integrated circuit chip provided in accordance with at least one embodiment of the present disclosure;

FIG. 6 is a schematic block diagram of an electronic device provided in accordance with at least one embodiment of the present disclosure; and

fig. 7 is a schematic diagram of a non-transitory computer readable storage medium according to at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

The present disclosure is illustrated by the following several specific examples. Detailed descriptions of known functions and known parts (elements) may be omitted for the sake of clarity and conciseness in the following description of the embodiments of the present disclosure. When any part (element) of an embodiment of the present disclosure appears in more than one drawing, the part (element) is denoted by the same or similar reference numeral in each drawing.

Voltage Drop (IR Drop) refers to a phenomenon in an integrated circuit where the voltage drops due to line resistance on the line between power and ground. Voltage drop phenomena include static voltage drop and dynamic voltage drop. The static voltage drop phenomenon is mainly caused by the voltage division of the metal connecting wire of the power network, the self resistance of the metal connecting wire is large, and the power voltage drop can be generated when the current passes through the internal power connecting wire. Dynamic voltage drop refers to voltage drop caused by current fluctuation when a power supply is switched by a circuit switch, and generally occurs at the triggering edge of a clock. The clock edge jump not only brings on and off of a large number of transistors in the circuit, but also brings jump of the combinational logic circuit, so that a large current is often generated on the whole chip in a short time, and the voltage drop phenomenon is caused by the instantaneous large current. The greater the number of transistors that switch at the same time, the easier it is to trigger the dynamic voltage drop phenomenon.

For static voltage drop, with the continuous evolution of semiconductor technology, the width of the metal interconnection line is narrower and narrower, and the resistance value of the interconnection line is continuously increased. Since the power supply network is a global network, the average length is longer, and if a device is far from the power supply point, the equivalent resistance on the connection line of the device must be larger, so that the farther from the power supply point, the smaller the power supply voltage can be obtained by the device. That is, a remote area of the chip far from the power supply terminal may suffer from insufficient operating voltage, resulting in a decrease in the flip speed of the logic gate unit in the area, or in more serious cases, the logic gate unit may not flip normally.

For dynamic voltage drop, since the current of each logic gate unit causes voltage drop to other logic gate units to different extent, when a large number of logic gate units connected to the metal wire are turned over simultaneously, the chip generates a large current in a short time, and the excessive instantaneous current causes a large voltage drop, so that the chip cannot work normally. In this case, although the chip can be brought back into normal operation by lowering the clock frequency, it comes at the cost of a decrease in chip performance, an increase in time cost, and the like.

The voltage drop problem can be solved by methods such as load reduction, over-design of a power supply network of a chip or addition of a voltage stabilizing module.

By over-designing the power supply network is meant reserving some margin (margin) for voltage drops within a certain range (e.g. 3% -5%), e.g. providing sufficient winding resources when planning the power supply, etc. However, the degree of over-design of the power supply network is often difficult to evaluate, and if the reserved margin is smaller, the actual voltage drop exceeds a certain range, so that the chip cannot work normally; if the reserved margin is larger, wiring (routing) resources may be occupied, the area of the chip is forced to be increased, and the cost of the chip is still indirectly affected.

In another common method, adding a voltage stabilizing module into a power supply system of a chip refers to adding the voltage stabilizing module to ensure voltage stability during chip design, thereby meeting the requirement of voltage drop limitation. Therefore, in an Electronic Design Automation (EDA) simulation process, a Chip Power Model (CPM) is acquired according to a post-simulation waveform of the entire Chip, so that the Chip Power Model is utilized to verify whether the voltage stabilizing module can bear the change of Power consumption, and then voltage Drop (IR Drop) analysis is performed on the Chip according to the Chip Power Model. Therefore, evaluating power consumption of a chip is an important ring of chip design.

Currently, generating a chip power consumption model using, for example, a voltage drop analysis tool requires the waveform to be simulated after input, i.e., the timing (timing) correct after the layout wiring (placement and routing, P & R) is completed.

However, generating a model of chip power consumption for the entire chip is not only a significant challenge for the project, but also very limited assistance for chip design. On the one hand, since the design scale of high-performance chips such as a central processing unit (Central Processing Unit, a CPU) and a graphics processor (Graphics Processing Unit, a GPU) is large, the complexity is high, and it is very difficult to directly obtain a chip power consumption model of the whole chip through a voltage drop analysis tool, a large amount of manpower and material resources are required to be input, and a large amount of time is also required to be spent. On the other hand, since the formation of the post-simulation waveform means that the chip design has approached the tail noise, obtaining a chip power consumption model in this case is not helpful to solve the voltage drop problem because the distance chip (Tape Out) is already not far away, i.e., the design inside the chip has been substantially completed, and is not far away from mass production of the chip, and a lot of time will be wasted if the power consumption and the external circuit are designed again, or the design cost will be excessively high due to mismatching of the chip and the external circuit. Therefore, it is desirable to reduce power consumption as early as possible in the design flow of the chip project.

The chip power consumption model can help to reduce the power consumption of the chip system level, so that the earlier the chip power consumption model is obtained, the more effectively the power consumption budget can be reduced, the cost waste caused by redesign is avoided, and the voltage drop analysis is facilitated to guide the design of an external power supply. How to obtain a chip power consumption model in the early stage of an integrated circuit chip project is a problem to be solved.

At least one embodiment of the present disclosure provides a power consumption analysis method for design of an integrated circuit chip, the method comprising: mapping operation is carried out on the register transmission level simulation waveform file of the integrated circuit chip, and a gate level netlist waveform file corresponding to the register transmission level simulation waveform file is obtained; performing power consumption analysis operation on the integrated circuit chip according to the gate-level netlist waveform file to obtain a power consumption waveform file of the integrated circuit chip; and obtaining a current characteristic file representing the current characteristic of the integrated circuit chip according to the power consumption waveform file of the integrated circuit chip.

At least one embodiment of the present disclosure provides a power consumption analysis apparatus for design of an integrated circuit chip, the apparatus including a mapping module, a power consumption analysis module, and a current characteristic acquisition module. The mapping module is configured to perform mapping operation on the register transmission level simulation waveform file of the integrated circuit chip to obtain a gate level netlist waveform file corresponding to the register transmission level simulation waveform file; the power consumption analysis module is configured to perform power consumption analysis operation on the integrated circuit chip according to the gate-level netlist waveform file to obtain a power consumption waveform file of the integrated circuit chip; the current characteristic acquisition module is configured to obtain a current characteristic file representing current characteristics of the integrated circuit chip from the power consumption waveform file of the integrated circuit chip.

The power consumption analysis method and the power consumption analysis device for the design of the integrated circuit chip provided by at least one embodiment of the present disclosure can obtain the power consumption and the current characteristics of the integrated circuit chip at an early stage of the design process of the integrated circuit chip, and in at least one embodiment, can obtain the current characteristics of each module of the integrated circuit chip, thereby helping to reduce the power consumption of the integrated circuit chip early, helping to solve the voltage drop problem of the integrated circuit chip, optimizing the chip design, and reducing the design cost.

At least one embodiment of the present disclosure also provides a method for designing power integrity of an integrated circuit chip, the method comprising: obtaining a power consumption waveform file of the integrated circuit chip according to the power consumption analysis method; and adjusting or designing the power supply module for the integrated circuit chip according to the power consumption waveform file of the integrated circuit chip.

According to the design method for the power supply integrity of the integrated circuit chip, which is provided by at least one embodiment of the disclosure, the power consumption and the current characteristics of the integrated circuit chip can be obtained in the early stage of the design process of the integrated circuit chip, the power supply integrity of the integrated circuit chip is designed in an assisted manner, the design of an external circuit of the chip is guided, the resource allocation is planned reasonably, the over-design of the circuit is prevented, the design period can be shortened effectively, the design efficiency is improved, and the design cost is saved.

In the design process of integrated circuits, simulation and verification are also an important link, which is an essential loop for checking whether the designed circuit meets the requirements.

The integrated circuit design includes two processes, front simulation and back simulation. The front simulation is also called functional simulation, and is a simulation for a register transfer stage (Register Transfer Level, RTL), wherein the register transfer stage simulation is based on an RTL file to perform simulation, and test simulation is performed on a logic function to verify whether the logic relationship of a circuit is correct or not, so that the simulation speed is relatively high. The post simulation is also called time sequence simulation, is a simulation for a Gate-level net list, is a simulation performed by taking the Gate delay parameter and the clock delay of a circuit into consideration, and the simulation result can judge whether the time sequence is correct or not and directly influence the accuracy of power consumption evaluation and voltage drop analysis.

In one example, the integrated circuit design may also include post-synthesis simulation, i.e., post-synthesis simulation may also be performed in-between the pre-simulation and the post-simulation. The post-synthesis simulation refers to reversely marking (annotate) a standard delay file into a comprehensive simulation model to estimate the influence of gate delay on a circuit. In this example, post-simulation primarily refers to simulating a laid-out netlist that more closely approximates the case of real circuit device operation.

As before, in the analysis of power consumption of an integrated circuit, a post-simulation waveform in a later stage of design is mainly adopted to generate a power consumption model of the whole chip, so as to analyze the power consumption of the chip at a package level or a system level. Since the post-simulation is a simulation for a gate-level netlist, the connection conditions between various circuit units and the delay of the circuit are required to be considered for the post-simulation, so that the simulation result obtained by the post-simulation is closer to the actual application condition, but the period of the post-simulation is very long, and a great deal of hardware resources and time are required, especially in a very large scale integrated circuit, such as a CPU (central processing unit) or a GPU (graphics processing unit) chip, the designer has difficulty in performing simulation verification on various modes of the whole circuit. Also, in actual chip design, the time to complete accurate power consumption analysis is often late, which may lead to a delay in design progress and adverse to the time cost and design efficiency of the chip design.

In comparison, the time taken for the pre-simulation is much less. Therefore, the power consumption analysis method provided by at least one embodiment of the present disclosure may obtain a post-simulation waveform by using a pre-simulation waveform in an early stage of a chip design flow, that is, a simulation waveform based on the pre-simulation waveform obtains a simulation waveform of a gate-level netlist, so as to obtain a current characteristic of a chip, thereby enabling power consumption to be estimated earlier, enabling power consumption analysis to be performed synchronously in a project along with automatic layout and wiring, greatly improving a power consumption analysis speed, playing a key role in reducing circuit power consumption, further, the obtained chip current characteristic file may also be used for subsequent analysis and verification of the chip, helping to analyze and improve a voltage drop problem, helping to guide design of a power supply network and a power supply, thereby helping to better adapt to design changes, and improving design efficiency.

Fig. 1 is a flow chart illustrating a method for analyzing power consumption for designing an integrated circuit chip according to at least one embodiment of the present disclosure. As shown in fig. 1, the power consumption analysis method provided in at least one embodiment of the present disclosure includes steps S100 to S300.

Step S100: and mapping the register transmission-level simulation waveform file of the integrated circuit chip to obtain a gate-level netlist waveform file corresponding to the register transmission-level simulation waveform file.

Step S200: and performing power consumption analysis operation on the integrated circuit chip according to the gate-level netlist waveform file to obtain the power consumption waveform file of the integrated circuit chip.

Step S300: and obtaining a current characteristic file representing the current characteristic of the integrated circuit chip according to the power consumption waveform file of the integrated circuit chip.

For example, the integrated circuit chip may be a large scale integrated circuit or a very large scale integrated circuit, a high performance chip such as a Central Processing Unit (CPU) or a Graphics Processing Unit (GPU), or the like.

For example, step S100, that is, performing mapping operation on the register transfer level simulation waveform file of the integrated circuit chip to obtain a gate level netlist waveform file corresponding to the register transfer level simulation waveform file, may be performed early in the chip design project, so that the gate level netlist waveform file corresponding to the register transfer level simulation waveform file can be obtained earlier.

In embodiments of the present disclosure, early stages of an project refer to stages prior to digital back-end design, such as place and route, for example, may be comprehensive stages.

In the design of an integrated circuit, a digital front-end design starts with a design architecture, starts with a netlist that enables layout and wiring, and a digital back-end design starts with layout and wiring, and starts with a file that enables streaming. That is, the generated gate level netlist may be used as a boundary, before which the front-end design is followed by the back-end design, during which the gate level netlist is further converted into a physical layout. The gate level netlist can be obtained by synthesis.

The synthesis mainly comprises three stages: conversion (transformation), mapping (mapping), and optimization (optimization). For example, the hardware description language (Hardware description language, HDL) description may be first converted to a process independent RTL (register transfer level) netlist (RTL modules in the netlist interconnected by wires) using a synthesis tool, then the RTL netlist mapped to a process library according to a specific process library to a gate level netlist, and finally the gate level netlist optimized according to constraints such as latency and area imposed by the designer.

The Synthesis corresponds to a difference in abstraction level and can be classified into Logic Synthesis (Logic Synthesis), RTL Synthesis, and behavior-level Synthesis. Logic synthesis refers to the process of mapping Register Transfer Level (RTL) into a gate level netlist. That is, in logic synthesis, the design is described as a boolean equation, and the basic cells such as flip-flops and latches are expressed in terms of element instantiations (instances).

In at least one embodiment of the present disclosure, step S100, mapping the register transfer level emulation waveform file of the integrated circuit chip refers to mapping the register transfer level to a gate level netlist, thereby obtaining a waveform file of the gate level netlist that can be used for performing power consumption analysis operations. The simulation waveform file refers to a waveform file recorded after simulation, and can be used for research or analysis in a subsequent design process. The format of the simulation waveform file may be general, for example, a Fast Signal DataBase (FSDB) file or a value change dump (Value Change Dump, VCD) file, or may be non-general, and the format of the simulation waveform file may be selected for use according to the actual situation, which is not limited in the embodiments of the present disclosure.

Fig. 2 illustrates a schematic diagram of a mapping operation provided by at least one embodiment of the present disclosure. As shown in FIG. 2, a Register Transfer Level (RTL) netlist is converted to a gate level netlist by a mapping operation, each register having a corresponding point on the netlist, the registers and their states being converted to the gate level netlist by the mapping operation. The mapping state refers to that the register is updated once every time the clock is changed, and defines (defines) which state the chip is in, and after the mapping operation, the gate netlist also has a corresponding state, that is, the circuit of the gate netlist is updated corresponding to the register transmission stage.

For example, in at least one embodiment of the present disclosure, the mapping operation refers to selecting constraint-compliant cells from a process library, converting a register transfer stage into a gate-level netlist. The process library provides all the information of the standard logic cells required for conversion, for example, the process library may contain the information of logic functions, cell areas, timing relationships, etc. of the standard logic cells under specific process conditions. For example, the mapping operation may be implemented by existing tools or written scripts, to which embodiments of the present disclosure are not limited.

Fig. 3 is a flow chart illustrating a power consumption analysis method for designing an integrated circuit chip according to another embodiment of the present disclosure.

For example, in at least one example of the embodiment of the present disclosure, the step S100 mentioned above, that is, performing a mapping operation on a register transfer level simulation waveform file of an integrated circuit chip, obtains a gate level netlist waveform file corresponding to the register transfer level simulation waveform file, and may be specifically implemented through step S110 in fig. 3: and mapping the register transmission level of the integrated circuit chip into a corresponding gate level netlist according to the naming mapping file to obtain a gate level netlist waveform file corresponding to the register transmission level simulation waveform file.

As the design of integrated circuit chips becomes more complex, hierarchical designs (hierarchy designs) have evolved. The hierarchical design refers to dividing an integrated circuit chip into a plurality of modules, then designing and developing the modules in parallel, and finally integrating, laying out, wiring and the like together, so that the design time and cost can be saved. Hierarchical designs include, for example, top-level designs and sub-top-level designs, with the top-level design typically only being one, but there may be multiple sub-top-level designs, even with sub-top-level designs that are further below the sub-top-level design.

In the integration stage of the integrated circuit chip, the hierarchy of the integrated circuit may be changed, for example, the circuit is subjected to re-partition processing (re-partition) according to specific circuit requirements, so that the hierarchy of the circuit is modified from a first hierarchy to a second hierarchy, and the naming of the register transfer stage may be changed along with the change of the hierarchy, so that the correspondence between the register transfer stage and the gate netlist needs to be found through a naming mapping file.

In this example, the naming mapping file refers to a file containing the mapping relationship between the register transfer level and gate level netlists, for example, a file containing the mapping relationship between the names and locations of different devices of an integrated circuit chip. The naming map file may record, for example, the conversion process of the synthesis tool to the register transfer level to the gate level netlist, and thus may be used to find and design corresponding points of the register transfer level and gate level netlists.

For example, the naming-map file may be a set-up verification format file (Setup Verification Format, SVF) or a file containing a table of the above-described mapping relationships, and the format and type of the naming-map file are not limited in the embodiments of the present disclosure.

For example, in at least one example of the embodiment of the present disclosure, the step S100, that is, performing mapping operation on the register transfer level simulation waveform file of the integrated circuit chip to obtain a gate level netlist waveform file corresponding to the register transfer level simulation waveform file, may be further implemented as: after the hierarchical structure of the integrated circuit chip is changed, mapping operation is carried out on the register transmission level simulation waveform file obtained after the hierarchical structure is adjusted according to the naming mapping file, and a gate level netlist waveform file corresponding to the register transmission level simulation waveform file is obtained.

For example, in a hierarchical design where an integrated circuit chip is divided into a plurality of modules, it may be necessary to make a hierarchical modification to the circuit again (or more times) to achieve an optimal circuit so that the overall structure of each division, each module/instance (instance), and the entire circuit meets the intended objectives. For example, in the logic synthesis stage of the front-end design, the register transfer level simulation waveform files are regrouped (Re-group), i.e., repartitioned, according to the specific situation of the layout and wiring process of the back-end design, and then a new register transfer level is generated, where the hierarchy of the new register transfer level is different from that before repartitioning.

In this example, since the hierarchical structure of the register transfer stage has been modified, the simulation waveform of the register transfer stage before repartitioning cannot be directly used any more, so that the register transfer stage after the hierarchical structure is changed can be repartitioned to obtain a new register transfer stage simulation waveform file, or by other methods, for example, repartitioning the waveform file of the register transfer stage, integrating to obtain a register transfer stage simulation waveform file after the hierarchical structure is adjusted, and then mapping the register transfer stage simulation waveform file according to the naming mapping file to obtain a gate stage netlist waveform file required by performing the power consumption analysis operation.

In the power consumption analysis method provided in at least one embodiment of the present disclosure, a gate level netlist waveform file corresponding to a register transmission level simulation waveform file may be directly obtained through mapping operation, without performing simulation on a netlist (the more time it takes for simulation of a larger scale integrated circuit chip), the gate level netlist waveform file may be directly used for performing power consumption analysis operation, so that power consumption evaluation may be performed at an early stage of a project, a large amount of time may be saved, and a project period of chip design may be shortened.

For example, in at least one example of the embodiment of the present disclosure, step S200 described above, that is, performing a power consumption analysis operation on the integrated circuit chip according to the gate level netlist waveform file, obtains a power consumption waveform file of the integrated circuit chip, which may be specifically implemented by step S210 in fig. 3: and performing power consumption analysis operation according to the obtained gate-level netlist waveform file by using a power consumption analysis tool to obtain a time-based power consumption waveform file of the integrated circuit chip.

Since the power consumption of an integrated circuit chip varies according to the function when the integrated circuit chip is operating, that is, the dynamic current distribution of the integrated circuit chip is different in different states. When the power consumption analysis operation is performed, a time period when the device on the integrated circuit chip is turned over highly can be intercepted, for example, waveforms in N system clock cycles can be intercepted, and thus a power consumption waveform file based on time is obtained.

For example, the power consumption analysis tool in the present disclosure may be an existing power consumption analysis tool, and of course may be a power consumption analysis tool that may be developed in the future, which is not limited by the embodiments of the present disclosure.

In this example, performing a power consumption analysis operation from the obtained gate level netlist waveform file, for example, by a power consumption analysis tool, to obtain a time-based power consumption waveform file for the integrated circuit chip may include: acquiring a power consumption analysis input file set comprising the gate-level netlist waveform file; and performing power consumption analysis operation on the integrated circuit chip according to the power consumption analysis input file set by a power consumption analysis tool so as to generate a time-based power consumption waveform file of the integrated circuit chip.

In an embodiment of the present disclosure, the power consumption analysis input file set refers to a set of input files required for performing a power consumption analysis operation. For example, the power consumption analysis input file set includes the gate level netlist waveform file obtained after the mapping operation.

For example, in at least one embodiment of the present disclosure, the power consumption analysis input file set further includes a standard time delay format (Standard Delay Format, SDF) file, a library file, a data file, a script file.

For example, the standard delay file in the power consumption analysis input file set is a file for reversely marking the standard delay file in the comprehensive simulation model to estimate the influence of gate delay on a circuit, and the gate-level netlist waveform file obtained after adding the gate delay can be used for performing power consumption analysis.

For example, the standard delay file includes timing information for standard cells in the design. It should be noted that the delay here includes only the delay of the standard cell and not the delay of the wiring, that is, the delay of the clock, and thus does not require a lot of time as the post-simulation (e.g., the circuit needs to undergo a plurality of toggling to settle).

For example, in addition to standard latency files, other configuration files are required for performing power consumption analysis operations, such as library files for performing power consumption analysis operations, other ancillary data files or script files, and the like, to which embodiments of the present disclosure are not limited.

In this example, for example, performing, by a power consumption analysis tool, a power consumption analysis operation according to the obtained gate level netlist waveform file to obtain a time-based power consumption waveform file of the integrated circuit chip may further include: setting sampling time intervals according to a clock of the gate-level netlist waveform file; a time-based power consumption waveform file is generated from the sampling time intervals.

For example, the sampling time for power consumption analysis may be truncated based on an operating clock of the integrated circuit chip, e.g., a period of time during which a device on the integrated circuit chip is highly flipped may be truncated, e.g., in one example, waveforms may be truncated for N system clock cycles, or in another example, waveforms may be truncated for a period of time, e.g., waveforms within 100 milliseconds (ms).

For example, the sampling time interval may be set directly according to the clock of the gate-level netlist waveform file, for example, the sampling time interval may be set to 100 microseconds (us), or the sampling time interval may be set by setting the number of sampling points in the sampling time, for example, 1000 sampling points may be set. Embodiments of the present disclosure are not limited in this regard.

For step S300 shown in fig. 1, that is, a current characteristic file representing the current characteristic of the integrated circuit chip is obtained from the power consumption waveform file of the integrated circuit chip, the power consumption waveform file may be a power consumption waveform file obtained by taking a power consumption average value, or may be the above-mentioned time-based power consumption waveform file.

For example, in at least one embodiment of the present disclosure, the step S300 is to obtain a current characteristic file representing the current characteristic of the integrated circuit chip according to the power consumption waveform file of the integrated circuit chip, and may be specifically implemented by step S310 in fig. 3: a current piecewise linear file representing the current characteristics of the integrated circuit chip is derived from the time-based power consumption waveform file and the arrangement of the voltage domains of the integrated circuit chip.

Since the current characteristics of the integrated circuit chip are often more focused when the power supply design is performed, even under the same power consumption, the current requirements of different voltage domains are different, and the current requirements of different ports are also different, for example, in a multi-port network, the total current is obtained by converging the branch currents of a plurality of ports, so that the acquisition of the current of each port according to the arrangement of different voltage domains can greatly help the subsequent power supply design. However, it is currently difficult to acquire the current characteristics of the integrated circuit chip at an early stage of the project.

According to the Power consumption analysis method provided by at least one embodiment of the present disclosure, a current characteristic file, such as a current piecewise linear file, of an integrated circuit chip under different voltage domains can be further obtained based on a Power consumption waveform file obtained after Power consumption analysis operation, where the current piecewise linear file is a format describing a chip scene and can reflect current variation conditions of the integrated circuit chip under different voltage domains, so that a Power Integrity (PI) design of a large-scale and high-performance integrated circuit chip can be conveniently guided more deeply and carefully in early stages of projects, design efficiency is improved, and design cost is saved.

For example, in at least one example of an embodiment of the present disclosure, an integrated circuit chip may include a plurality of voltage domains, in which case deriving a current piecewise linear file representing current characteristics of the integrated circuit chip from a time-based power consumption waveform file and an arrangement of voltage domains of the integrated circuit chip may include: acquiring working voltage of each of a plurality of voltage domains and a plurality of power consumption waveform files based on time; for each of the plurality of voltage domains, a plurality of current piecewise linear profiles for the plurality of voltage domains are derived from the plurality of power consumption waveform profiles based on time, respectively.

In this example, the current characteristic file representing the current characteristic of the integrated circuit chip may be, for example, a current piecewise linear (current piece wise linear, IPWL) file. Since the integrated circuit chip may be divided into different Voltage domains (Voltage domains) that are powered by different power supplies, for example, a high performance-requiring circuit portion may be allocated to operate in a high Voltage Domain and a low performance-requiring circuit portion may be allocated to operate in a low Voltage Domain, the current characteristics files under the different Voltage domains are different, that is, the current piecewise linear files under the different Voltage domains are different.

For example, an integrated circuit chip may include multiple voltage domains, such as a high voltage domain and a low voltage domain, and the arrangement of the voltage domains may be different in different integrated circuit chips, as embodiments of the disclosure are not limited in this respect.

For example, the operating voltage of each voltage domain may be obtained based on a plurality of voltage domains of the integrated circuit chip, and then a current characteristic file corresponding to each voltage domain may be generated based on the power consumption waveform file, for example, a current piecewise linear file corresponding to each voltage domain may be generated, so that the current characteristic file of the integrated circuit chip under the plurality of voltage domains may be obtained. The power consumption analysis method can acquire the current characteristics of the chip under different voltage domains in the early stage of the chip design project, and is beneficial to voltage drop analysis and power supply design in the early stage of the project, so that the method can be better adapted to design change and improve the chip design efficiency.

In this example, power consumption waveform files for different operating conditions may also be generated according to different operating conditions of the integrated circuit, for example, according to the time-based power consumption waveform file and the arrangement of voltage domains of the integrated circuit chip, a current piecewise linear file representing current characteristics of the integrated circuit chip may further include: selecting a plurality of working conditions of the integrated circuit chip and acquiring a time-based power consumption waveform file corresponding to the plurality of working conditions; and obtaining a plurality of current piecewise linear files of a plurality of voltage domains according to the time-based power consumption waveform files corresponding to a plurality of working conditions.

For example, in at least one embodiment of the present disclosure, the plurality of operating conditions includes a best case, a normal case, and a worst case.

For example, the plurality of operating conditions refer to operating conditions of the integrated circuit chip under different operating conditions, such as different voltages, temperatures, pressures, etc., and for example, the operating conditions include a Best case (Best case), a normal case (normal case), or a worst case (worst case). Wherein, the worst case refers to the working limit condition, in order to ensure that the chip can still work under certain extreme conditions, the power consumption of the chip under the worst case needs to be analyzed, so that the acquisition of the current characteristic file of the integrated circuit chip under the worst case is very meaningful, can help to guide the subsequent analysis and verification of the chip,

For example, in at least one example of an embodiment of the present disclosure, the integrated circuit chip includes a plurality of modules, and the power consumption analysis method further includes: integrating a plurality of current piecewise linear files of a plurality of voltage domains to obtain current piecewise linear files of a plurality of modules; and integrating the current piecewise linear files of the plurality of modules to obtain the current piecewise linear file of the whole integrated circuit chip.

For example, as described above, an integrated circuit chip may be divided into a plurality of modules, and the power consumption analysis method provided by at least one embodiment of the present disclosure may obtain a current profile of each module of the integrated circuit chip, and then may obtain a current profile (e.g., a current piecewise linear file) of the entire integrated circuit chip by integrating the current profiles of the plurality of modules. The current characteristic file of each module of the integrated circuit chip is obtained, and the voltage drop problem of the chip can be better evaluated according to the current requirements of different modules.

For example, multiple current piecewise linear profiles for multiple voltage domains may also be integrated to obtain a current piecewise linear profile for each module. For example, a module herein may include multiple sub-modules under different voltage domains. Further, the current characteristic files of the plurality of modules can be integrated, so that the current characteristic file of the whole integrated circuit chip is obtained.

The power consumption analysis method for the design of the integrated circuit chip provided by at least one embodiment of the present disclosure can obtain the power consumption and the current characteristics of the integrated circuit chip at an early stage of the design process of the integrated circuit chip, and in at least one embodiment, can obtain the current characteristics of each module of the integrated circuit chip, thereby helping to reduce the power consumption of the integrated circuit chip earlier, helping to solve the voltage drop problem of the integrated circuit chip, optimizing the chip design, and reducing the design cost.

At least one embodiment of the present disclosure also provides a method for designing power integrity of an integrated circuit chip.

Fig. 4 is a flow chart illustrating a method for designing power integrity of an integrated circuit chip according to at least one embodiment of the present disclosure. As shown in fig. 4, the design method includes steps S10 and S20.

S10: obtaining a power consumption waveform file of the integrated circuit chip according to the power consumption analysis method;

s20: and adjusting or designing the power supply module for the integrated circuit chip according to the power consumption waveform file of the integrated circuit chip.

For example, in at least one embodiment of the present disclosure, the design method further includes step S30: the power supply module for the integrated circuit chip is adjusted or designed according to the current profile of the integrated circuit chip.

For example, in at least one example of an embodiment of the present disclosure, the power module includes a power supply and a voltage regulation module.

For example, the adjustment or design of the Power module for the integrated circuit chip refers to the design of the external Power supply of the integrated circuit chip, for example, a voltage stabilizing module may be added in the Power module to improve the Power Integrity (PI), or a capacitor, a wire winding, etc. in the Power module may be designed to prevent the Power network of the chip from being over designed.

The design method provided by at least one embodiment of the present disclosure can assist in designing the power integrity of the integrated circuit chip by obtaining the power consumption and the current characteristics of the integrated circuit chip at an early stage of the integrated circuit chip design process, guiding the design of the external circuit of the chip, reasonably planning the resource allocation, preventing the over-design of the circuit, effectively shortening the design period, improving the design efficiency, and saving the design cost.

Corresponding to the above-mentioned power consumption analysis method, at least one embodiment of the present disclosure further provides a power consumption analysis device, and fig. 5 is a schematic block diagram of a power consumption analysis device for designing an integrated circuit chip according to at least one embodiment of the present disclosure.

For example, as shown in fig. 5, the power consumption analysis apparatus 500 includes a mapping module 501, a power consumption analysis module 502, and a current characteristic acquisition module 503.

The mapping module 501 is configured to perform mapping operation on the register transmission level simulation waveform file of the integrated circuit chip, so as to obtain a gate level netlist waveform file corresponding to the register transmission level simulation waveform file.

And the power consumption analysis module 502 is configured to perform power consumption analysis operation on the integrated circuit chip according to the gate-level netlist waveform file to obtain the power consumption waveform file of the integrated circuit chip.

The current characteristic obtaining module 503 is configured to obtain a current characteristic file representing the current characteristic of the integrated circuit chip according to the power consumption waveform file of the integrated circuit chip.

For example, the mapping module 501, the power consumption analysis module 502, and the current characteristic acquisition module 503 include codes and programs stored in a memory; the processor may execute the code and program to implement some or all of the functions of the mapping module 501, the power consumption analysis module 502, and the current characteristic acquisition module 503 as described above. For example, the mapping module 501, the power consumption analysis module 502, and the current characteristic acquisition module 503 may be dedicated hardware devices, or may be a circuit board or a combination of circuit boards for implementing some or all of the functions of the mapping module 501, the power consumption analysis module 502, and the current characteristic acquisition module 503 as described above. The circuit board or combination of circuit boards may include: (1) one or more processors; (2) One or more non-transitory memories coupled to the processor; and (3) firmware stored in the memory that is executable by the processor.

It should be noted that, the mapping module 501 may be used to implement the step S100 in fig. 1, the power consumption analysis module 502 may be used to implement the step S200 in fig. 1, and the current characteristic obtaining module 503 may be used to implement the step S300 in fig. 1. For specific description of the mapping module 501, the power consumption analysis module 502 and the current characteristic acquisition module 503 reference may be made to the relevant descriptions of steps S100, S200 and S300 shown in fig. 1 in the above-described embodiment of the power consumption analysis method,

the power consumption analysis device can achieve similar technical effects as the power consumption analysis method, and will not be described herein.

At least one embodiment of the present disclosure further provides an electronic device, and fig. 6 is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.

For example, as shown in fig. 6, the electronic device includes a processor 1001, a communication interface 1002, a memory 1003, and a communication bus 1004. The processor 1001, the communication interface 1002, and the memory 1003 communicate with each other via the communication bus 1004, and the components of the processor 1001, the communication interface 1002, and the memory 1003 may communicate with each other via a network connection. The present disclosure is not limited herein with respect to the type and functionality of the network.

For example, the memory 1003 is used to store computer-executable instructions non-transitory. The processor 1001 is configured to execute computer-executable instructions that, when executed by the processor 1001, implement a power consumption analysis method or design method according to any of the embodiments described above. For specific implementation of each step of the power consumption analysis method or the design method and related explanation, reference may be made to the embodiments of the power consumption analysis method or the design method, which are not described herein.

For example, the implementation of the power consumption analysis method for the design of an integrated circuit chip or the design method for the power supply integrity of an integrated circuit chip by the processor 1001 executing the program stored on the memory 1003 is the same as the implementation mentioned in the foregoing description of the embodiments of the power consumption analysis method and the design method, and will not be repeated here.

For example, communication bus 1004 may be a peripheral component interconnect standard (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus may be classified as an address bus, a data bus, a control bus, or the like. For ease of illustration, the figures are shown with only one bold line, but not with only one bus or one type of bus.

For example, the communication interface 1002 is used to enable communication between an electronic device and other devices.

For example, the processor 1001 may control other components in the electronic device to perform desired functions. The processor 1001 may be a Central Processing Unit (CPU), a Network Processor (NP), etc., and may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The Central Processing Unit (CPU) can be an X86 or ARM architecture, etc.

For example, memory 1003 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, random Access Memory (RAM) and/or cache memory (cache) and the like. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer-executable instructions may be stored on the computer-readable storage medium that may be executed by the processor 1001 to implement various functions of an electronic device. Various applications and various data, etc. may also be stored in the storage medium.

For example, a detailed description of the power consumption analysis method or the design method performed by the electronic device may refer to a related description in an embodiment of the power consumption analysis method or the design method, and the repetition is omitted.

Fig. 7 is a schematic diagram of a non-transitory computer readable storage medium according to at least one embodiment of the present disclosure. For example, as shown in FIG. 7, one or more computer-executable instructions 1101 may be stored non-transitory on the storage medium 1100. For example, the computer-executable instructions 1101, when executed by a processor, may perform one or more steps in an analysis method according to the digital circuit described above.

For example, the storage medium 1100 may be applied to the power consumption analysis device 500 of the electronic device and/or the integrated circuit chip. For example, storage medium 1100 may include memory 1003 in an electronic device.

For example, the description of the storage medium 1100 may refer to the description of the memory in the embodiment of the electronic device, and the repetition is omitted.

While the disclosure has been described in detail with respect to the general description and the specific embodiments thereof, it will be apparent to those skilled in the art that certain modifications and improvements may be made thereto based on the embodiments of the disclosure. Accordingly, such modifications or improvements may be made without departing from the spirit of the disclosure and are intended to be within the scope of the disclosure as claimed.

For the purposes of this disclosure, the following points are also noted:

(1) The drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

(2) In the drawings for describing embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced for clarity, i.e., the drawings are not drawn to actual scale.

(3) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.

The foregoing is merely specific embodiments of the disclosure, but the scope of the disclosure is not limited thereto, and the scope of the disclosure should be determined by the claims.

Claims

1. A power consumption analysis method for design of an integrated circuit chip, comprising:

mapping the register transmission-level simulation waveform file of the integrated circuit chip to obtain a gate-level netlist waveform file corresponding to the register transmission-level simulation waveform file;

performing power consumption analysis operation on the integrated circuit chip according to the gate-level netlist waveform file to obtain a power consumption waveform file of the integrated circuit chip;

and obtaining a current characteristic file representing the current characteristic of the integrated circuit chip according to the power consumption waveform file of the integrated circuit chip.

2. The power consumption analysis method according to claim 1, wherein the mapping the register transfer level simulation waveform file of the integrated circuit chip to obtain a gate level netlist waveform file corresponding to the register transfer level simulation waveform file includes:

and mapping the register transmission level of the integrated circuit chip into a corresponding gate level netlist according to the naming mapping file to obtain the gate level netlist waveform file corresponding to the register transmission level simulation waveform file.

3. The power consumption analysis method according to claim 1, wherein the performing power consumption analysis operation on the integrated circuit chip according to the gate level netlist waveform file to obtain the power consumption waveform file of the integrated circuit chip includes:

performing the power consumption analysis operation according to the obtained gate-level netlist waveform file by using a power consumption analysis tool to obtain a time-based power consumption waveform file of the integrated circuit chip;

the obtaining a current characteristic file representing the current characteristic of the integrated circuit chip according to the power consumption waveform file of the integrated circuit chip comprises the following steps:

and obtaining a current piecewise linear file representing the current characteristic of the integrated circuit chip according to the time-based power consumption waveform file and the arrangement of the voltage domains of the integrated circuit chip.

4. The power consumption analysis method according to claim 3, wherein the performing, by the power consumption analysis tool, the power consumption analysis operation according to the obtained gate level netlist waveform file to obtain a time-based power consumption waveform file of the integrated circuit chip includes:

acquiring a power consumption analysis input file set comprising the gate-level netlist waveform file;

And performing the power consumption analysis operation on the integrated circuit chip according to the power consumption analysis input file set by a power consumption analysis tool so as to generate the time-based power consumption waveform file of the integrated circuit chip.

5. The power consumption analysis method of claim 4, further comprising:

setting a sampling time interval according to the clock of the gate-level netlist waveform file;

and generating a power consumption waveform file based on time according to the sampling time interval.

6. The power consumption analysis method of claim 4, wherein the power consumption analysis input file set further comprises a standard latency format file, a library file, a data file, a script file.

7. The power consumption analysis method according to claim 3, wherein the integrated circuit chip includes a plurality of voltage domains,

the obtaining a current piecewise linear file representing the current characteristic of the integrated circuit chip according to the time-based power consumption waveform file and the arrangement of the voltage domains of the integrated circuit chip comprises:

acquiring working voltage of each of the plurality of voltage domains and a plurality of power consumption waveform files based on time;

and respectively obtaining a plurality of current piecewise linear files of the voltage domains according to the plurality of power consumption waveform files based on time for each of the voltage domains.

8. The power consumption analysis method of claim 7, further comprising:

selecting a plurality of working conditions of the integrated circuit chip and acquiring a time-based power consumption waveform file corresponding to the plurality of working conditions;

and obtaining a plurality of current piecewise linear files of the voltage domains according to the time-based power consumption waveform files corresponding to the working conditions.

9. The power consumption analysis method of claim 8, wherein the plurality of operating conditions includes a best case, a normal case, and a worst case.

10. The power consumption analysis method according to claim 7, wherein the integrated circuit chip includes a plurality of modules,

the power consumption analysis method further comprises the following steps:

integrating a plurality of current piecewise linear files of the voltage domains to obtain current piecewise linear files of the modules;

and integrating the current piecewise linear files of the modules to obtain the current piecewise linear file of the whole integrated circuit chip.

11. A method of designing power integrity of an integrated circuit chip, comprising:

obtaining a current profile of the integrated circuit chip according to the power consumption analysis method of any one of claims 1-10;

And adjusting or designing the power supply module for the integrated circuit chip according to the current characteristic file of the integrated circuit chip.

12. The design method of claim 11, wherein the power module comprises a power supply and a voltage regulation module.

13. A power consumption analysis apparatus for design of an integrated circuit chip, comprising:

the mapping module is configured to perform mapping operation on the register transmission level simulation waveform file of the integrated circuit chip to obtain a gate level netlist waveform file corresponding to the register transmission level simulation waveform file;

the power consumption analysis module is configured to perform power consumption analysis operation on the integrated circuit chip according to the gate-level netlist waveform file to obtain a power consumption waveform file of the integrated circuit chip;

and the current characteristic acquisition module is configured to obtain a current characteristic file representing the current characteristic of the integrated circuit chip according to the power consumption waveform file of the integrated circuit chip.

14. An electronic device, comprising:

a memory non-transitory storing computer-executable instructions;

a processor configured to execute the computer-executable instructions,

wherein the computer executable instructions when executed by the processor implement the power consumption analysis method according to any of claims 1-10 or the design method according to any of claims 11-12.

15. A non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions,

the computer executable instructions, when executed by a processor, implement the power consumption analysis method according to any of claims 1-10 or the design method according to any of claims 11-12.