CN114357916A - Chip FPGA prototype verification method and system - Google Patents
Chip FPGA prototype verification method and system Download PDFInfo
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- CN114357916A CN114357916A CN202210029267.8A CN202210029267A CN114357916A CN 114357916 A CN114357916 A CN 114357916A CN 202210029267 A CN202210029267 A CN 202210029267A CN 114357916 A CN114357916 A CN 114357916A
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Abstract
The invention provides a chip FPGA prototype verification method and a system, which relate to the field of chip FPGA prototype verification, and are characterized by firstly reading a target RTL design code, setting macro definition data at the head of the RTL design code, then generating a first module file list according to the macro definition data, deleting modules which are not target verification modules in the first module file list according to target verification modules, generating a second module file list, and then only verifying the functions and the performances of the modules in the second module file list, thereby improving the verification pertinence, reducing the verification time, increasing the verification flexibility, simplifying the verification program, improving the efficiency of the FPGA prototype verification stage of the chip and shortening the research and development period of the chip.
Description
Technical Field
The invention relates to the technical field of FPGA prototype verification, in particular to a chip FPGA prototype verification method and a chip FPGA prototype verification system.
Background
With the increasing scale of chip design, the functions of the chip become more complex, and the verification stage of the chip occupies most of the time of the whole chip development. In order to shorten the verification time, many new verification methods, such as sdv (software drive verification), bfm (bus Function model), etc., and FPGA-based prototype verification technology, are emerging on the basis of the conventional simulation verification. Due to the advantages of the FPGA, the development of most chips adopts an FPGA prototype verification technology.
In the verification process of the FPGA prototype, the prior art carries out all compiling and verification on RTL design codes, the time is long, the verification speed is slow, the flexibility is low, some subsystems are verified, but the subsystems are required to be manually divided, and the program is complex, so that the verification time is long, and a verification method for solving the problems that the FPGA prototype verification time is long, the verification speed is slow, the flexibility is low and the program is complex is urgently needed.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the defects of long verification time, low verification speed, low flexibility and complicated program of the FPGA prototype in the prior art.
The invention provides a chip FPGA prototype verification method and a system, which can improve the verification pertinence, increase the verification flexibility, simplify the verification program, reduce the verification time, improve the efficiency of the FPGA prototype verification stage of the chip and shorten the research and development period of the chip.
According to one aspect of the invention, the following technical scheme is adopted:
a chip FPGA prototype verification method comprises the following steps:
step 101, reading a target RTL design code, and setting macro definition data at the head of the RTL design code, wherein the macro definition can be set according to a module name, a module switch and a module node in the RTL code, and the macro definition data includes but is not limited to acquired module capacity, module area, connection relationship between modules and clock relationship between modules;
102, generating a first module file list according to the macro definition data;
103, generating a target verification module list according to the target verification module;
step 104, comparing the first module file list with the target verification module list, deleting modules which are not in the target verification module list from the first module file list, and generating a second module file list;
105, according to the constraint conditions of multiple FPGAs, on the premise that the maximum working capacity and the use area of the multiple FPGAs are not exceeded, sequentially considering the minimum connection of the optimized multiple FPGAs and the clock relationship of the optimized multiple FPGAs, and distributing the modules in the second module file list to the corresponding FPGAs for verifying the functions and the performances;
step 106, judging whether the verification is successful; if the verification is successful, finishing the verification work; if not, an error is returned for modification, and step 105 is performed after the error is modified.
Further, comprising: step 1041, before said step 105, generating an Excel table according to the register, and converting into a header file usable by the system verilog or C program by using the script for register verification.
Further, comprising: the Excel table and the header file available to the program contain the address definitions and default values of the registers.
Further, still include: step 107, performing comprehensive processing on the module successfully verified, wherein the comprehensive processing refers to converting the RTL code into a gate-level netlist file or program, and includes compiling, converting, scheduling, allocating, synthesizing a controller and generating a result; the resource refers to a result of the comprehensive processing, namely a netlist file generated by the comprehensive processing; step 108, downloading the resources after the comprehensive processing to an FPGA for gate level verification; and step 109, judging whether the gate-level verification is successful, if so, finishing the gate-level verification, and if not, returning an error for modification.
Further, comprising: the comprehensive processing refers to converting the RTL code into a gate-level netlist file or program, and comprises a compiling step, a converting step, a scheduling step, a distributing step, a controller synthesizing step and a result generating step; the resource refers to a result of the comprehensive processing, namely a netlist file generated by the comprehensive processing;
in the compiling step, the behavior characteristic description compiled by the hardware description language is compiled into an intermediate representation format suitable for automatic synthesis, which comprises a control flow graph, a data flow graph and a control data flow graph;
in the conversion step, the behavior description of the design is optimized; the method comprises the steps of compiling optimization, increasing the parallelism of operation, converting complex multi-cycle operation into simple operation, and reducing the number of operations on a key path and a specified path in a control data flow graph;
in the scheduling step, giving the operation to the control step; the control step is a time sequence unit corresponding to a plurality of clock cycles; the purpose of scheduling is to minimize the time required for the device to complete all functions, i.e. to determine the moment at which each operation occurs, if the constraint is met;
in the allocation step, defining a process of interconnection among components in the system; including assigning registers or RAM memory to store data values, assigning functional units to perform specific operations, assigning interconnect paths to transfer data between units; establishing a data path consisting of functional block level modules, so that the occupied hardware resource cost is minimized and the hardware resource cost is shared as much as possible;
in the controller synthesis step, a controller for driving a data path according to a scheduling requirement;
in the result generation step, the design is converted into a physical implementation of the hardware structure.
According to another aspect of the invention, the following technical scheme is adopted:
a chip FPGA prototype verification system, comprising:
the system comprises a setting unit, a setting unit and a control unit, wherein the setting unit is used for reading a target RTL design code and setting macro definition data at the head of the RTL design code, the macro definition can be set according to a module name, a module switch and a module node in the RTL code, and the macro definition data comprises but is not limited to the acquired module capacity, module area, the connection relationship between modules and the clock relationship between modules;
the first generation unit is used for generating a first module file list according to the macro definition data;
the second production unit is used for generating a target verification module list according to the target verification module;
a third generating unit, configured to compare the first module file list with the target verification module list, delete a module in the first module file list that is not in the target verification module list, and generate a second module file list;
the first verification unit is used for distributing the modules in the second module file list to corresponding FPGAs for verifying the functions and the performances according to constraint conditions of the multiple FPGAs and on the premise that the maximum working capacity and the using area of the multiple FPGAs are not exceeded, sequentially considering the minimum connection of the optimized multiple FPGAs and the clock relationship of the optimized multiple FPGAs;
the first judging unit is used for judging whether the verification is successful; if the verification is successful, finishing the verification work; if not, an error is returned for modification, and the first verification unit is executed after the error is modified.
Further, comprising: and the conversion unit is used for generating an Excel table according to the register before the first verification unit is executed, and converting the Excel table into a header file which can be used by a system verilog or C program by using a script for register verification.
Further, comprising: the Excel table and the header file available to the program contain the address definitions and default values of the registers.
Further, still include: the comprehensive processing unit is used for carrying out comprehensive processing on the module which is successfully verified, wherein the comprehensive processing refers to the conversion of the RTL code into a gate-level netlist file or program and comprises compiling, converting, scheduling, distributing, controller synthesizing and result generating; the resource refers to a result of the comprehensive processing, namely a netlist file generated by the comprehensive processing;
the second verification unit is used for downloading the comprehensively processed resources to the FPGA for gate-level verification;
and the second judgment unit is used for judging whether the gate-level verification is successful or not, finishing the gate-level verification if the gate-level verification is successful, and returning an error for modification if the gate-level verification is unsuccessful.
Further, comprising: the comprehensive unit is used for converting the RTL code into a gate-level netlist file or program and comprises a compiling unit, a converting unit, a scheduling unit, a distributing unit, a controller comprehensive unit and a result generating unit; the resource refers to a result of the comprehensive processing, namely a netlist file generated by the comprehensive processing;
the synthesis unit includes:
the compiling unit is used for compiling the behavior characteristic description compiled by the hardware description language into an intermediate representation format suitable for automatic synthesis, and the intermediate representation format comprises a control flow graph, a data flow graph and a control data flow graph;
the conversion unit is used for optimizing the behavior description of the design; the method comprises the steps of compiling optimization, increasing the parallelism of operation, converting complex multi-cycle operation into simple operation, and reducing the number of operations on a key path and a specified path in a control data flow graph;
a scheduling unit for assigning the operation to the control step; the control step is a time sequence unit corresponding to a plurality of clock cycles; the purpose of scheduling is to minimize the time required for the device to complete all functions, i.e. to determine the moment at which each operation occurs, if the constraint is met;
a distribution unit to define processes of components and interconnections between components in the system; including assigning registers or RAM memory to store data values, assigning functional units to perform specific operations, assigning interconnect paths to transfer data between units; establishing a data path consisting of functional block level modules, so that the occupied hardware resource cost is minimized and the hardware resource cost is shared as much as possible;
a controller integration unit for driving a controller of the data path according to a scheduling requirement;
a result generation step unit to convert the design into a physical implementation of the hardware structure.
The technical scheme of the invention has the following advantages:
1. the invention provides a chip FPGA prototype verification method, which comprises the steps of firstly reading a target RTL design code, setting macro definition data at the head of the RTL design code, secondly generating a first module file list according to the macro definition data, deleting modules which are not target verification modules in the first module file list according to target verification modules, generating a second module file list, and then only verifying the functions and performances of the modules in the second module file list, thereby improving the verification pertinence, reducing the verification time, increasing the verification flexibility, simplifying the verification program, improving the efficiency of the FPGA prototype verification stage of the chip and shortening the research and development period of the chip.
2. According to the chip FPGA prototype verification method provided by the invention, before verification is executed, an Excel table is generated according to the register, and the Excel table is converted into a header file available for a system verilog or C program by using a script for register verification, so that the register verification time is reduced, and the FPGA prototype verification efficiency is improved.
3. The verification module can be set randomly according to the actual verification requirement, and the verification can be flexibly performed, so that the verification can be performed synchronously or in stages, the flexibility of the FPGA prototype verification is improved, and the verification efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic diagram of a chip FPGA prototype verification method according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of an improved chip FPGA prototype verification method according to a first embodiment of the present invention;
fig. 3 is a schematic diagram of a chip FPGA prototype verification method according to a second embodiment of the present invention;
fig. 4 is a schematic diagram of an improved chip FPGA prototype verification method according to a second embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1
In step 101, reading a target RTL design code, and setting macro definition data at a header of the RTL design code, where the macro definition may be set according to a module name, a module switch, and a module node in the RTL code, and the macro definition data includes, but is not limited to, an acquired module capacity, an acquired module area, a connection relationship between modules, and a clock relationship between modules; 102, generating a first module file list according to the macro definition data; 103, generating a target verification module list according to the target verification module; step 104, comparing the first module file list with the target verification module list, deleting modules which are not in the target verification module list from the first module file list, and generating a second module file list; 105, according to the constraint conditions of multiple FPGAs, on the premise that the maximum working capacity and the use area of the multiple FPGAs are not exceeded, sequentially considering the minimum connection of the optimized multiple FPGAs and the clock relationship of the optimized multiple FPGAs, and distributing the modules in the second module file list to the corresponding FPGAs for verifying the functions and the performances; step 106, judging whether the verification is successful; if the verification is successful, finishing the verification work; if not, an error is returned for modification, and step 105 is performed after the error is modified.
According to the chip FPGA prototype verification method, macro definition data of the module can be automatically generated, the module can be detailed to a very small module, irrelevant module codes are deleted according to a target verification module file, then code verification is carried out, tedious programs set manually can be reduced, verification time is saved, verification efficiency is improved, and a chip research and development period is shortened.
Specifically, the macro definition can be set according to the module name, the module switch and the module node in the RTL code, so that the module can be called or deleted at any time as required, and flexibility is increased. The macro defines data including, but not limited to, acquired module capacity, module area, connection relationships between modules, and clock relationships between modules. And then according to the constraint conditions of the multiple FPGAs, on the premise that the maximum working capacity and the using area of the multiple FPGAs are not exceeded, sequentially considering the minimum connection of the optimized multiple FPGAs and the clock relationship of the optimized multiple FPGAs, and distributing the modules to be verified to the corresponding FPGAs for verification.
An improved implementation of the above method for verifying the prototype of the chip FPGA, with reference to fig. 2, includes: step 1041, before said step 105, generating an Excel table according to the register, and converting into a header file usable by the system verilog or C program by using the script for register verification. The Excel table and the header file available to the program contain the address definitions and default values of the registers. Through the improved optimization, the verification speed can be further accelerated, so that the verification time is shortened.
An improved implementation of the above method for verifying the prototype of the chip FPGA refers to fig. 3 or fig. 4, and further includes: step 107, performing comprehensive processing on the module successfully verified, wherein the comprehensive processing refers to converting the RTL code into a gate-level netlist file or program, and includes compiling, converting, scheduling, allocating, synthesizing a controller and generating a result; the resource refers to a result of the comprehensive processing, namely a netlist file generated by the comprehensive processing; step 108, downloading the resources after the comprehensive processing to an FPGA for gate level verification; step 109, judging whether the gate-level verification is successful, if so, ending the gate-level verification, if not, returning an error for modification, and after the error is modified, returning to execute the chip FPGA prototype verification method from the corresponding step according to the modified place.
Further, comprising: the comprehensive processing refers to converting the RTL code into a gate-level netlist file or program, and comprises a compiling step, a converting step, a scheduling step, a distributing step, a controller synthesizing step and a result generating step; the resource refers to a result of the comprehensive processing, namely a netlist file generated by the comprehensive processing; in the compiling step, the behavior characteristic description compiled by the hardware description language is compiled into an intermediate representation format suitable for automatic synthesis, which comprises a control flow graph, a data flow graph and a control data flow graph; in the conversion step, the behavior description of the design is optimized; the method comprises the steps of compiling optimization, increasing the parallelism of operation, converting complex multi-cycle operation into simple operation, and reducing the number of operations on a key path and a specified path in a control data flow graph; in the scheduling step, giving the operation to the control step; the control step is a time sequence unit corresponding to a plurality of clock cycles; the purpose of scheduling is to minimize the time required for the device to complete all functions, i.e. to determine the moment at which each operation occurs, if the constraint is met; in the allocation step, defining a process of interconnection among components in the system; including assigning registers or RAM memory to store data values, assigning functional units to perform specific operations, assigning interconnect paths to transfer data between units; establishing a data path consisting of functional block level modules, so that the occupied hardware resource cost is minimized and the hardware resource cost is shared as much as possible; in the controller synthesis step, a controller for driving a data path according to a scheduling requirement; in the result generation step, the design is converted into a physical implementation of the hardware structure.
Example 2
In a specific embodiment of the chip FPGA prototype verification system of the present application, the setting unit is configured to read a target RTL design code, and set macro definition data at a header of the RTL design code, where the macro definition may be set according to a module name, a module switch, and a module node in the RTL code, and the macro definition data includes, but is not limited to, an obtained module capacity, an obtained module area, a connection relationship between modules, and a clock relationship between modules; the first generation unit is used for generating a first module file list according to the macro definition data; the second production unit is used for generating a target verification module list according to the target verification module; a third generating unit, configured to compare the first module file list with the target verification module list, delete a module in the first module file list that is not in the target verification module list, and generate a second module file list; the first verification unit is used for distributing the modules in the second module file list to corresponding FPGAs for verifying the functions and the performances according to constraint conditions of the multiple FPGAs and on the premise that the maximum working capacity and the using area of the multiple FPGAs are not exceeded, sequentially considering the minimum connection of the optimized multiple FPGAs and the clock relationship of the optimized multiple FPGAs; the first judging unit is used for judging whether the verification is successful; if the verification is successful, finishing the verification work; if not, an error is returned for modification, and the first verification unit is executed after the error is modified.
According to the chip FPGA prototype verification system, macro definition data of the module can be automatically generated, a very small module can be obtained in detail, irrelevant module codes are deleted according to a target verification module file, code verification is carried out, a tedious program set manually can be reduced, verification time is saved, verification efficiency is improved, and a chip research and development period is shortened.
Specifically, the macro definition can be set according to the module name, the module switch and the module node in the RTL code, so that the module can be called or deleted at any time as required, and flexibility is increased. The macro defines data including, but not limited to, acquired module capacity, module area, connection relationships between modules, and clock relationships between modules. And then according to the constraint conditions of the multiple FPGAs, on the premise that the maximum working capacity and the using area of the multiple FPGAs are not exceeded, sequentially considering the minimum connection of the optimized multiple FPGAs and the clock relationship of the optimized multiple FPGAs, and distributing the modules to be verified to the corresponding FPGAs for verification.
An improved implementation of the above chip FPGA prototype verification system includes: and the conversion unit is used for generating an Excel table according to the register before the verification unit is executed, and converting the Excel table into a header file which can be used by a system verilog or C program by using a script for register verification. The Excel table and the header file available to the program contain the address definitions and default values of the registers. Through the improved optimization, the verification speed can be further accelerated, so that the verification time is shortened.
An improved implementation of the above chip FPGA prototype verification system further includes: the comprehensive processing unit is used for carrying out comprehensive processing on the module which is successfully verified, wherein the comprehensive processing refers to the conversion of the RTL code into a gate-level netlist file or program and comprises compiling, converting, scheduling, distributing, controller synthesizing and result generating; the resource refers to a result of the comprehensive processing, namely a netlist file generated by the comprehensive processing; the gate level verification unit is used for downloading the comprehensively processed resources to the FPGA for gate level verification; and the second judgment unit is used for judging whether the gate-level verification is successful or not, if so, ending the gate-level verification, and if not, returning an error for modification, and after the error is modified, returning to execute the chip FPGA prototype verification method from the corresponding step according to the modified place.
Furthermore, the comprehensive processing unit is used for converting the RTL code into a gate-level netlist file or a program and comprises a compiling unit, a converting unit, a scheduling unit, a distributing unit, a controller synthesizing unit and a result generating unit; the resource refers to a result of the comprehensive processing, namely a netlist file generated by the comprehensive processing; the compiling unit is used for compiling the behavior characteristic description compiled by the hardware description language into an intermediate representation format suitable for automatic synthesis, and the intermediate representation format comprises a control flow graph, a data flow graph and a control data flow graph; the conversion unit is used for optimizing the behavior description of the design; the method comprises the steps of compiling optimization, increasing the parallelism of operation, converting complex multi-cycle operation into simple operation, and reducing the number of operations on a key path and a specified path in a control data flow graph; a scheduling unit for assigning the operation to the control step; the control step is a time sequence unit corresponding to a plurality of clock cycles; the purpose of scheduling is to minimize the time required for the device to complete all functions, i.e. to determine the moment at which each operation occurs, if the constraint is met; a distribution unit to define processes of components and interconnections between components in the system; including assigning registers or RAM memory to store data values, assigning functional units to perform specific operations, assigning interconnect paths to transfer data between units; establishing a data path consisting of functional block level modules, so that the occupied hardware resource cost is minimized and the hardware resource cost is shared as much as possible; a controller integration unit for driving a controller of the data path according to a scheduling requirement; in the result generation unit, the design is converted into a physical implementation of the hardware structure.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (10)
1. A chip FPGA prototype verification method is characterized by comprising the following steps:
step 101, reading a target RTL design code, and setting macro definition data at the head of the RTL design code, wherein the macro definition can be set according to a module name, a module switch and a module node in the RTL code, and the macro definition data includes but is not limited to acquired module capacity, module area, connection relationship between modules and clock relationship between modules;
102, generating a first module file list according to the macro definition data;
103, generating a target verification module list according to the target verification module;
step 104, comparing the first module file list with the target verification module list, deleting modules which are not in the target verification module list from the first module file list, and generating a second module file list;
105, according to the constraint conditions of multiple FPGAs, on the premise that the maximum working capacity and the use area of the multiple FPGAs are not exceeded, sequentially considering the minimum connection of the optimized multiple FPGAs and the clock relationship of the optimized multiple FPGAs, and distributing the modules in the second module file list to the corresponding FPGAs for verifying the functions and the performances;
step 106, judging whether the verification is successful; if the verification is successful, finishing the verification work; if not, an error is returned for modification, and step 105 is performed after the error is modified.
2. The chip FPGA prototype verification method of claim 1, comprising:
step 1041, before said step 105, generating an Excel table according to the register, and converting into a header file usable by the system verilog or C program by using the script for register verification.
3. The chip FPGA prototype verification method of claim 2, comprising:
the Excel table and the header file available to the program contain the address definitions and default values of the registers.
4. The chip FPGA prototype verification method according to any one of claims 1 to 3, further comprising:
step 107, performing comprehensive processing on the module successfully verified, wherein the comprehensive processing refers to converting the RTL code into a gate-level netlist file or program, and includes compiling, converting, scheduling, allocating, synthesizing a controller and generating a result; the resource refers to a result of the comprehensive processing, namely a netlist file generated by the comprehensive processing;
step 108, downloading the resources after the comprehensive processing to an FPGA for gate level verification;
step 109, determining whether the gate level verification is successful, if so, ending the gate level verification, if not, returning an error for modification, and executing step 105 after modifying the error.
5. The chip FPGA prototype verification method according to claim 4, comprising:
the comprehensive processing refers to converting the RTL code into a gate-level netlist file or program, and comprises a compiling step, a converting step, a scheduling step, a distributing step, a controller synthesizing step and a result generating step; the resource refers to a result of the comprehensive processing, namely a netlist file generated by the comprehensive processing;
in the compiling step, the behavior characteristic description compiled by the hardware description language is compiled into an intermediate representation format suitable for automatic synthesis, which comprises a control flow graph, a data flow graph and a control data flow graph;
in the conversion step, the behavior description of the design is optimized; the method comprises the steps of compiling optimization, increasing the parallelism of operation, converting complex multi-cycle operation into simple operation, and reducing the number of operations on a key path and a specified path in a control data flow graph;
in the scheduling step, giving the operation to the control step; the control step is a time sequence unit corresponding to a plurality of clock cycles; the purpose of scheduling is to minimize the time required for the device to complete all functions, i.e. to determine the moment at which each operation occurs, if the constraint is met;
in the allocation step, defining a process of interconnection among components in the system; including assigning registers or RAM memory to store data values, assigning functional units to perform specific operations, assigning interconnect paths to transfer data between units; establishing a data path consisting of functional block level modules, so that the occupied hardware resource cost is minimized and the hardware resource cost is shared as much as possible;
in the controller synthesis step, a controller for driving a data path according to a scheduling requirement;
in the result generation step, the design is converted into a physical implementation of the hardware structure.
6. A chip FPGA prototype verification system, comprising:
the system comprises a setting unit, a setting unit and a control unit, wherein the setting unit is used for reading a target RTL design code and setting macro definition data at the head of the RTL design code, the macro definition can be set according to a module name, a module switch and a module node in the RTL code, and the macro definition data comprises but is not limited to the acquired module capacity, module area, the connection relationship between modules and the clock relationship between modules;
the first generation unit is used for generating a first module file list according to the macro definition data;
the second production unit is used for generating a target verification module list according to the target verification module;
a third generating unit, configured to compare the first module file list with the target verification module list, delete a module in the first module file list that is not in the target verification module list, and generate a second module file list;
the first verification unit is used for distributing the modules in the second module file list to corresponding FPGAs for verifying the functions and the performances according to constraint conditions of the multiple FPGAs and on the premise that the maximum working capacity and the using area of the multiple FPGAs are not exceeded, sequentially considering the minimum connection of the optimized multiple FPGAs and the clock relationship of the optimized multiple FPGAs;
the first judging unit is used for judging whether the verification is successful; if the verification is successful, finishing the verification work; if not, an error is returned for modification, and the first verification unit is executed after the error is modified.
7. The chip FPGA prototype verification system of claim 6, comprising:
and the conversion unit is used for generating an Excel table according to the register before the first verification unit is executed, and converting the Excel table into a header file which can be used by a system verilog or C program by using a script for register verification.
8. The chip FPGA prototype verification system of claim 7, comprising:
the Excel table and the header file available to the program contain the address definitions and default values of the registers.
9. The chip FPGA prototype verification system according to any one of claims 6 to 8, further comprising:
the comprehensive processing unit is used for carrying out comprehensive processing on the module which is successfully verified, wherein the comprehensive processing refers to the conversion of the RTL code into a gate-level netlist file or program and comprises compiling, converting, scheduling, distributing, controller synthesizing and result generating; the resource refers to a result of the comprehensive processing, namely a netlist file generated by the comprehensive processing;
the second verification unit is used for downloading the comprehensively processed resources to the FPGA for gate-level verification;
and the second judgment unit is used for judging whether the gate-level verification is successful or not, ending the gate-level verification if the gate-level verification is successful, returning an error for modification if the gate-level verification is unsuccessful, and executing the first verification unit after the error is modified.
10. The chip FPGA prototype verification system of claim 9, comprising:
the comprehensive unit is used for converting the RTL code into a gate-level netlist file or program and comprises a compiling unit, a converting unit, a scheduling unit, a distributing unit, a controller comprehensive unit and a result generating unit; the resource refers to a result of the comprehensive processing, namely a netlist file generated by the comprehensive processing;
the synthesis unit includes:
the compiling unit is used for compiling the behavior characteristic description compiled by the hardware description language into an intermediate representation format suitable for automatic synthesis, and the intermediate representation format comprises a control flow graph, a data flow graph and a control data flow graph;
the conversion unit is used for optimizing the behavior description of the design; the method comprises the steps of compiling optimization, increasing the parallelism of operation, converting complex multi-cycle operation into simple operation, and reducing the number of operations on a key path and a specified path in a control data flow graph;
a scheduling unit for assigning the operation to the control step; the control step is a time sequence unit corresponding to a plurality of clock cycles; the purpose of scheduling is to minimize the time required for the device to complete all functions, i.e. to determine the moment at which each operation occurs, if the constraint is met;
a distribution unit to define processes of components and interconnections between components in the system; including assigning registers or RAM memory to store data values, assigning functional units to perform specific operations, assigning interconnect paths to transfer data between units; establishing a data path consisting of functional block level modules, so that the occupied hardware resource cost is minimized and the hardware resource cost is shared as much as possible;
a controller integration unit for driving a controller of the data path according to a scheduling requirement;
a result generation step unit to convert the design into a physical implementation of the hardware structure.
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