CN113904677A - Look-up table circuit capable of customizing multiple inputs and novel array structure of FPGA - Google Patents
Look-up table circuit capable of customizing multiple inputs and novel array structure of FPGA Download PDFInfo
- Publication number
- CN113904677A CN113904677A CN202111189704.4A CN202111189704A CN113904677A CN 113904677 A CN113904677 A CN 113904677A CN 202111189704 A CN202111189704 A CN 202111189704A CN 113904677 A CN113904677 A CN 113904677A
- Authority
- CN
- China
- Prior art keywords
- input
- lookup table
- selector
- output end
- input data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
Abstract
The invention discloses a lookup table circuit capable of customizing multiple inputs and a novel array structure of an FPGA (field programmable gate array), belongs to the technical field of programmable logic devices, and solves the problems of low density and inflexible configuration of lookup table logic resources in the prior art. According to the invention, through the connection of the plurality of lookup table units with different inputs, the plurality of data selectors and the adder, the lookup tables with various inputs can be flexibly realized according to requirements, and the flexibility and the adaptability in application are improved; the novel array structure of the customizable FPGA adopts a hexagonal tiled structure, and each hexagon comprises twelve polygonal PLBs. The invention is used for realizing various logic functions in the programmable logic device, simultaneously increases the density of the logic device, reserves enough wiring space and is beneficial to flexible wiring.
Description
Technical Field
The invention relates to the technical field of FPGA design and development, in particular to a lookup table circuit capable of customizing multiple inputs and a novel FPGA array structure.
Background
A Field Programmable Gate Array (FPGA) is a logic device widely used in many fields such as data processing, communication, and network.
In a large-scale FPGA chip, wiring resources account for more than 70% of the chip area, and meanwhile, interconnection delay also accounts for more than 70% of the overall delay, so that the performance of the wiring resources determines the performance of an FPGA device to a great extent. The LUT of the traditional FPGA PLB only has a fixed bit number, cannot well adapt to different specific requirements, and cannot be flexibly configured according to the requirements.
Conventional programmable interconnect resources are generally formed in a planar structure by horizontal interconnect resources and vertical interconnect resources, which are connected to each other through a switch matrix, as shown in fig. 1. The traditional horizontal and vertical interconnection mode has low density, less wiring resources, larger chip area and larger interconnection delay.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to overcome the defect of the prior art that the configuration cannot be flexibly configured according to the requirement, so as to provide a lookup table circuit capable of configuring multiple inputs.
The invention provides a lookup table circuit for customizing multiple inputs, which comprises four six-input lookup table units, four two-input lookup table units, six lookup table selectors, two adders, a three-input data selector, a four-input data selector and two-input data selectors, wherein,
the six input ends of the first six-input lookup table unit, the second six-input lookup table unit, the third six-input lookup table unit and the fourth six-input lookup table unit multiplex a first input signal, a second input signal, a third input signal, a fourth input signal, a fifth input signal and a sixth input signal;
the two input ends of the first two-input lookup table unit, the second two-input lookup table unit, the third two-input lookup table unit and the fourth two-input lookup table unit multiplex a ninth input signal and a tenth input signal;
the output end of the first six-input lookup table unit is connected with the first input end of the first lookup table selector; the output end of the first sixth input lookup table unit is connected with the first input end of the first adder; the output end of the second sixth input lookup table unit is connected with the second input end of the first lookup table selector; the output end of the second sixth input lookup table unit is connected with the second input end of the first adder; the output end of the third sixth input lookup table unit is connected with the first input end of the second lookup table selector; the output end of the third sixth input lookup table unit is connected with the first input end of the second adder; the output end of the fourth sixth input lookup table unit is connected with the second input end of the second lookup table selector; the output end of the fourth sixth input lookup table unit is connected with the second input end of the second adder;
the carry signal input end of the first adder is connected with a carry signal, and the carry signal output end of the first adder is connected with the carry signal input end of the first adder; the addition output end of the first adder is connected with the second input end of the three-input data selector; the addition output end of the second adder is connected with the second input end of the four-input data selector; the second adder is coupled to the input data output.
The output end of the first lookup table selector is connected with the first input end of the third lookup table selector; the output end of the second lookup table selector is connected with the second input end of the third lookup table selector;
the output end of the first two-input lookup table unit is connected with the first input end of the fourth lookup table selector; the output end of the second input lookup table unit is connected with the second input end of the fourth lookup table selector; the output end of the third second input lookup table unit is connected with the first input end of the fifth lookup table selector; the output end of the fourth second input lookup table unit is connected with the second input end of the fifth lookup table selector;
the output end of the fourth lookup table selector is connected with the first input end of the sixth lookup table selector; the output end of the fifth lookup table selector is connected with the second input end of the sixth lookup table selector;
the data selection ends of the first lookup table selector, the second lookup table selector and the sixth lookup table selector multiplex a seventh input signal; the data selection ends of the third lookup table selector, the fourth lookup table selector and the fifth lookup table selector multiplex an eighth input signal;
the output end of the third lookup table selector is connected with the third input end of the three-input data selector; the output end of the sixth lookup table selector is connected with the third input end of the four-input data selector; the first input end of the three-input data selector is connected with the input port of the shift register.
The output end of the three-input data selector is connected with the first input end of the first two-input data selector and the first input end of the first trigger; the output end of the four-input data selector is connected with the first input end of the second input data selector and the first input end of the second trigger;
the second input end of the first trigger and the second input end of the second trigger are connected with a clock signal in a branch manner;
the output end of the first trigger is simultaneously connected with the second input end of the first two-input data selector and the first input end of the four-input data selector; the output end of the second trigger is connected with the second input end of the second input data selector; the output end of the second trigger is simultaneously connected with the output port of the shift register;
the output port of the first two-input data selector is a first output port of the lookup table circuit capable of configuring various inputs; the output port of the second input data selector is a second output port of the lookup table circuit which can configure various inputs.
Furthermore, the configuration modes of the selection ends of the three-input data selector, the four-input data selector, the first two-input data selector and the second two-input data selector comprise SRAM chain programming, Flash programming, fuse programming and anti-fuse programming.
Further, the first sixth input lookup table unit, the second sixth input lookup table unit, the third sixth input lookup table unit, the fourth sixth input lookup table unit, the first second input lookup table unit, the second input lookup table unit, the third second input lookup table unit, the fourth second input lookup table unit, the first lookup table selector, the second lookup table selector, the third lookup table selector, the fourth lookup table selector, the fifth lookup table selector, the sixth lookup table selector, the first adder, the second adder, the third input data selector, the fourth input data selector, the first second input data selector, and the second input data selector are arranged in a polygon structure, the polygon structure is a right trapezoid structure or a structure formed by cutting 1 to 2 corners of a right trapezoid, twelve of the polygonal structures are laid in the honeycomb-shaped regular hexagon structure.
Further, one interior angle of the right trapezoid is 60 °.
The invention aims to solve another technical problem of overcoming the defects of low logic resource density and less space of wiring resources in the prior art, thereby providing a novel structure capable of configuring the FPGA, improving the logic resource density and increasing the space of the wiring resources.
The invention provides a novel array structure capable of configuring an FPGA (field programmable gate array). the novel array structure of the FPGA is formed by tiling the honeycomb regular hexagon structure of the lookup table circuit capable of configuring multiple inputs.
Further, the honeycomb-shaped regular hexagon structure is a centrosymmetric structure; the spacing between the polygonal structures is used for programmable routing; and a blank space is reserved in the center of the honeycomb regular hexagon structure formed by twelve polygonal structures, and the blank space can be used for programmable wiring or logic element arrangement.
Further, the programmable routing resources are distributed over 6 lines: 0 degree, 30 degrees, 60 degrees, 90 degrees, 120 degrees, 150 degrees; wiring resources are distributed in two directions of each line; the programmable wiring resources are composed of three wiring resources of a double wire, a quadruple wire and a long wire, wherein: the double-fold line realizes the connection between the two programmable logic blocks with the distance of 1 and 2 in any direction; the quadruple lines realize the connection between the two programmable logic blocks with the distance of 4 in any direction; the long line realizes the connection between any two programmable logic blocks with the distance of 6 on the same axis to form hierarchical interconnection; starting from any one of the programmable logic blocks, a double line and a quadruple line are connected to each logic block of a ring with the distance of 2 or 4 to the programmable logic block to form a ring surface connection.
Further, each of the programmable logic blocks is connected with 17 adjacent programmable logic blocks with the distance of 1 and is connected with 66 programmable logic blocks with the distance of 2 through a double line; each programmable logic block is connected with 216 programmable logic blocks with the distance of 4 through a quadruple line, and 360 programmable logic blocks with the distance of 6 are connected through a long line.
The technical scheme of the invention has the following advantages:
1. the multi-input customizable lookup table circuit provided by the invention can flexibly realize the multi-input lookup tables according to the needs by connecting the four six-input lookup table units, the four two-input lookup table units, the six lookup table selectors, the two adders, the three-input data selector, the four-input data selector and the two-input data selectors, thereby increasing the flexibility and the adaptability in application and improving the subsequent use efficiency of the FPGA.
2. The novel array structure of the customizable FPGA adopts a structure of laying hexagons, and each hexagon comprises twelve polygonal structures, so that the density of logic devices is further increased, and meanwhile, enough wiring space is reserved, and flexible wiring is facilitated.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a diagram of a conventional FPGA architecture;
FIG. 2 is a schematic diagram of a look-up table circuit capable of customizing a plurality of inputs according to a first embodiment of the present invention;
FIG. 3 is a schematic diagram of a circuit configuration of a customizable multiple-input lookup table circuit configured as an addition operation according to a first embodiment of the invention;
FIG. 4 is a schematic diagram of a circuit configuration of a customizable multiple input lookup table circuit configured as a shift register according to a first embodiment of the present invention;
FIG. 5 is a schematic diagram of a look-up table circuit configuration with customizable multiple inputs as provided in a first embodiment of the present invention as a 6- & 6-input look-up table circuit configuration;
FIG. 6 is a schematic diagram of a look-up table circuit configuration with customizable multiple inputs as provided in a first embodiment of the present invention as a 7- & 7-input look-up table circuit configuration;
FIG. 7 is a schematic diagram of a look-up table circuit configuration with customizable multiple inputs as provided in a first embodiment of the present invention as an 8- & 2-input look-up table circuit configuration;
FIG. 8 is a schematic diagram of a look-up table circuit configuration for customizable multiple inputs as provided in a first embodiment of the present invention as a 7- & 3-input look-up table circuit configuration;
FIG. 9 is a schematic view of a hexagonal structure of twelve PLBs provided in a first embodiment of the invention;
fig. 10 is a schematic diagram of a novel array structure of a hexagonal tiled FPGA according to a second embodiment of the present invention;
fig. 11 is a schematic diagram of a routing resource of a novel array structure of an FPGA according to a second embodiment of the present invention;
FIG. 12 is a schematic diagram of a PLB provided with a distance of 1 in a second embodiment of the present invention;
FIG. 13 is a schematic diagram of a PLB provided at distances 1 and 2 in a second embodiment of the present invention;
FIG. 14 is a schematic diagram of a PLB provided at a distance of 4 in a second embodiment of the present invention;
description of reference numerals:
111-a first sixth input look-up table; 112-a second sixth input look-up table; 113-a third sixth input look-up table; 114-a fourth sixth input look-up table; 121-first two-input lookup table; 122-a second input look-up table; 123-a third second input look-up table; 124-a fourth second input look-up table; 131-a first look-up table selector; 132-a second look-up table selector; 133-a third look-up table selector; 134-a fourth lookup table selector; 135-a fifth look-up table selector; 136-a sixth lookup table selector; 141-three input data selector; 142-four input data selector; 143-a first two-input data selector; 144-a second input data selector; 151-first adder; 152-a second adder; 161-a first flip-flop; 162-second flip-flop.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1
One embodiment of a multi-input customizable lookup table circuit as shown in fig. 2 comprises four six-input lookup table units, four two-input lookup table units, six lookup table selectors, two adders, a three-input data selector, a four-input data selector, and two-input data selectors, wherein,
the six input terminals of the first, second, third and fourth sixth input lookup table units 111, 112 and 114 multiplex the first, second, third, fourth, fifth and sixth input signals in1, in2, in3, in4, in5 and in 6;
the two input terminals of the first two-input lookup table unit 121, the second two-input lookup table unit 122, the third two-input lookup table unit 123 and the fourth two-input lookup table unit 123 multiplex the ninth input signal in9 and the tenth input signal in 10;
the output end of the first sixth input lookup table unit 111 is connected with the first input end of the first lookup table selector 131; the output end of the first sixth input lookup table unit 111 is connected to the first input end of the first adder 151; the output end of the second sixth input lookup table unit 112 is connected to the second input end of the first lookup table selector 131; the output terminal of the second sixth input lookup table unit 112 is connected to the second input terminal of the first adder 151; the output end of the third sixth input lookup table unit 113 is connected to the first input end of the second lookup table selector 132; the output end of the third sixth input lookup table unit 113 is connected to the first input end of the second adder 152; the output end of the fourth sixth input lookup table unit 114 is connected to the second input end of the second lookup table selector 132; the output terminal of the fourth sixth input lookup table unit 114 is connected to the second input terminal of the second adder 152;
a carry signal input end of the first adder 151 is connected to a carry signal Cin, and a carry signal output end of the first adder 151 is connected to a carry signal input end of the first adder 151; an addition output terminal of the first adder 151 is connected to a second input terminal of the three-input data selector 141; a summing output of the second adder 152 is connected to a second input of the four-input data selector 142; the second adder 152 is connected to the carry data output Cout.
The output terminal of the first lookup table selector 131 is connected to the first input terminal of the third lookup table selector 133; an output terminal of the second lookup table selector 132 is connected to a second input terminal of a third lookup table selector 133;
the output end of the first two-input lookup table unit 121 is connected to the first input end of the fourth lookup table selector 134; the output terminal of the second input lookup table unit 122 is connected to a second input terminal of the fourth lookup table selector 134; the output terminal of the third second input lookup table unit 123 is connected to a first input terminal of a fifth lookup table selector 135; an output terminal of the fourth second input lookup table unit 124 is connected to a second input terminal of a fifth lookup table selector 135;
an output terminal of the fourth lookup table selector 134 is connected to a first input terminal of a sixth lookup table selector 136; an output terminal of the fifth lookup table selector 135 is connected to a second input terminal of the sixth lookup table selector 136;
the data selection terminals of the first lookup table selector 131, the second lookup table selector 132 and the sixth lookup table selector 136 multiplex a seventh input signal in 7; the data selection terminals of the third lookup table selector 133, the fourth lookup table selector 134 and the fifth lookup table selector 135 multiplex an eighth input signal in 8;
an output terminal of the third lookup table selector 133 is connected to a third input terminal of the three-input data selector 141; the output terminal of the sixth lookup table selector 136 is connected to the third input terminal of the four-input data selector 142; a first input terminal of the three-input data selector 141 is connected to the input port REGin of the shift register.
The output terminal of the three-input data selector 141 is connected with the first input terminal of the first two-input data selector 143 and the first input terminal of the first flip-flop 161; the output terminal of the four-input data selector 142 is connected to the first input terminal of the second input data selector 144 and the first input terminal of the second flip-flop 162;
the second input terminal of the first flip-flop 161 and the second input terminal of the second flip-flop 162 are connected with a clock signal CLK;
the output end of the first flip-flop 161 is simultaneously connected with the second input end of the first two-input data selector 143 and the first input end of the four-input data selector 142; the output end of the second flip-flop 162 is connected to the second input end of the second input data selector 144; the output end of the second flip-flop 162 is simultaneously connected to the output port REGout of the shift register;
the output port of the first two-input data selector 143 is the lookup table circuit first output port out0 of the configurable multiple inputs; the output port of the second input data selector 144 is the look-up table circuit second output port out1 for the configurable variety of inputs.
As shown in fig. 3, the lookup table circuit capable of configuring multiple inputs is configured as a circuit for addition operation, and uses a first six-input lookup table unit 111, a second six-input lookup table unit 112, a third six-input lookup table unit 113 and a fourth six-input lookup table unit 114, wherein the outputs of the first six-input lookup table unit 111 and the second six-input lookup table unit 112 are connected to two inputs of the first adder 151, the outputs of the third six-input lookup table unit 113 and the fourth six-input lookup table unit 114 are connected to two inputs of the second adder 152, the output of the first adder 151 is connected to the first input of the first two-input data selector 143, the result is output from the output out0 of the first two-input data selector 143, the output of the second adder 152 is connected to the first input of the second two-input data selector 144, the result is output from the output out1 of the second two-input data selector 144, the carry signal Cin is connected to the first adder 151 and the second adder 152, and carries data is output from the carry signal output terminal Cout.
As shown in fig. 4, the look-up table circuit capable of customizing various inputs is configured as a circuit of a shift register, a shift signal REGin is input to a first input terminal of a first flip-flop 161, a clock signal CLK is connected to a second input terminal of the first flip-flop 161, an output terminal of the first flip-flop 161 outputs data to an out0, an output terminal of the first flip-flop 161 is connected to a first input terminal of a second flip-flop 162, the clock signal CLK is connected to a second input terminal of the second flip-flop 162, and an output terminal of the second flip-flop 162 outputs data to an out1, and a shift signal REGout is output to a shift output terminal REGout.
As shown in fig. 5, the look-up table circuit capable of customizing a plurality of inputs is configured as a 7- & 7-input look-up table circuit, the first input signal in1, the second input signal in2, the third input signal in3, the fourth input signal in4, the fifth input signal in5, the sixth input signal in6 and the seventh input signal in7 are configured as a 7-input data look-up table output to a first input terminal of the first two-input data selector 143, an output terminal out0 of the first two-input data selector 143 outputs the result, the first input signal in1 is multiplexed, the second input signal in2, the third input signal in3, the fourth input signal in4, the fifth input signal in5, the sixth input signal in6 and the seventh input signal in7 are configured as a 7-input data lookup table output to a first input terminal of the second input data selector 144, and an output terminal out1 of the second input data selector 144 outputs the result.
As shown in fig. 6, the look-up table circuit capable of customizing multiple inputs is configured as an 8- & 2-input look-up table circuit, the first input signal in1, the second input signal in2, the third input signal in3, the fourth input signal in4, the fifth input signal in5, the sixth input signal in6, the seventh input signal in7, and the eighth input signal in8 are configured such that the 8-input data look-up table is output to the first input terminal of the first two-input data selector 143, the output terminal out0 of the first two-input data selector 143 outputs the result, the ninth input signal in9 and the tenth input signal in10 are configured such that the 2-input data look-up table is output to the first input terminal of the second two-input data selector 144, and the output terminal out1 of the second two-input data selector 144 outputs the result.
As shown in fig. 7, the look-up table circuit capable of customizing a plurality of inputs is configured as a 7- & 3-input look-up table circuit, the first input signal in1, the second input signal in2, the third input signal in3, the fourth input signal in4, the fifth input signal in5, the sixth input signal in6 and the seventh input signal in7 are configured such that 8 input data look-up tables are output to the first input terminal of the first two-input data selector 143, the output terminal out0 of the first two-input data selector 143 outputs results, the eighth input signal in8, the ninth input signal in9 and the tenth input signal in10 are configured such that 3 input data look-up tables are output to the first input terminal of the second two-input data selector 144, and the output terminal out1 of the second two-input data selector 144 outputs results.
Fig. 8 is a look-up table circuit capable of customizing multiple inputs, which is configured as a 6- & 4-input look-up table circuit, wherein a first input signal in1, a second input signal in2, a third input signal in3, a fourth input signal in4, a fifth input signal in5 and a sixth input signal in6 are respectively connected to six input ends of the first six-input look-up table unit 111, an output end of the first six-input look-up table unit 111 is connected to a first input end of the first two-input data selector 143, an output end out0 of the first two-input data selector 143 outputs a result, a seventh input signal in7, an eighth input signal in8, a ninth input signal in9 and a tenth input signal in10 are configured as a 4-input data look-up table output to a first input end of the second two-input data selector 144, and an output end out1 of the second input data selector 144 outputs a result.
The lookup table circuit capable of being configured with various inputs can be configured into a circuit for addition operation, a shift register, a 7- & 7-input lookup table circuit, an 8- & 2-input lookup table circuit, a 7- & 3-input lookup table circuit and a 6- & 4-input lookup table circuit according to actual requirements, and is flexible in configuration and convenient for subsequent development.
Specifically, the configuration modes of the selection terminals of the three-input data selector 141, the four-input data selector 142, the first two-input data selector 143, and the second two-input data selector 144 include SRAM chain programming, Flash programming, fuse programming, and anti-fuse programming.
Specifically, the first sixth input lookup table unit 111, the second sixth input lookup table unit 112, the third sixth input lookup table unit 113, the fourth sixth input lookup table unit 114, the first two-input lookup table unit 121, the second two-input lookup table unit 122, the third two-input lookup table unit 123, the fourth two-input lookup table unit 124, the first lookup table selector 131, the second lookup table selector 132, the third lookup table selector 133, the fourth lookup table selector 134, the fifth lookup table selector 135, the sixth lookup table selector 136, the first adder 151, the second adder 152, the three-input data selector 141, the fourth input data selector 142, the first two-input data selector 143, the second two-input data selector 144, and other related elements not drawn are arranged in a polygonal structure PLB, the polygonal structure is a right trapezoid structure PLB or a structure PLB formed by cutting 1 to 2 corners of a right trapezoid, as shown in fig. 9, twelve polygonal structures PLBs are laid in a honeycomb regular hexagon structure.
Example 2
Fig. 10 shows an embodiment of a customizable FPGA new array structure, which is formed by tiling the honeycomb regular hexagon structures of the customizable multiple-input lookup table circuits. The honeycomb regular hexagon structure is a centrosymmetric structure; the spacing between the polygonal structures is used for programmable routing; and a blank space is reserved in the center of the honeycomb regular hexagon structure formed by twelve polygonal structures, and the blank space can be used for programmable wiring or logic element arrangement.
As shown in fig. 11, the programmable routing resources are distributed over 6 lines: 0 degrees, namely horizontal lines, 30 degrees, 60 degrees, 90 degrees, namely vertical lines, 120 degrees and 150 degrees; wiring resources are distributed in two directions of each line; the programmable wiring resources are composed of three wiring resources of a double wire, a quadruple wire and a long wire, wherein: the double-fold line realizes the connection between the two programmable logic blocks with the distance of 1 and 2 in any direction; the quadruple lines realize the connection between the two programmable logic blocks with the distance of 4 in any direction; the long line realizes the connection between any two programmable logic blocks with the distance of 6 on the same axis to form hierarchical interconnection; starting from any one of the programmable logic blocks, a double line and a quadruple line are connected to each logic block of a ring with the distance of 2 or 4 to the programmable logic block to form a ring surface connection.
As shown in fig. 12 and 13, each of the programmable logic blocks of the novel array structure of FPGA is connected to 17 adjacent programmable logic blocks at a distance of 1 and is connected to 66 adjacent programmable logic blocks at a distance of 2 through a double line; as shown in fig. 14, each of the programmable logic blocks is connected to 216 programmable logic blocks at a distance of 4 by a quadruple line, and 360 programmable logic blocks at a distance of 6 are connected by a long line.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (8)
1. A lookup table circuit capable of customizing a plurality of inputs, comprising: four six-input lookup table units, four two-input lookup table units, six lookup table selectors, two adders, a three-input data selector, a four-input data selector, and two-input data selectors,
the six input ends of the first six-input lookup table unit, the second six-input lookup table unit, the third six-input lookup table unit and the fourth six-input lookup table unit multiplex a first input signal, a second input signal, a third input signal, a fourth input signal, a fifth input signal and a sixth input signal;
the two input ends of the first two-input lookup table unit, the second two-input lookup table unit, the third two-input lookup table unit and the fourth two-input lookup table unit multiplex a ninth input signal and a tenth input signal;
the output end of the first six-input lookup table unit is connected with the first input end of the first lookup table selector; the output end of the first sixth input lookup table unit is connected with the first input end of the first adder; the output end of the second sixth input lookup table unit is connected with the second input end of the first lookup table selector; the output end of the second sixth input lookup table unit is connected with the second input end of the first adder; the output end of the third sixth input lookup table unit is connected with the first input end of the second lookup table selector; the output end of the third sixth input lookup table unit is connected with the first input end of the second adder; the output end of the fourth sixth input lookup table unit is connected with the second input end of the second lookup table selector; the output end of the fourth sixth input lookup table unit is connected with the second input end of the second adder;
the carry signal input end of the first adder is connected with a carry signal, and the carry signal output end of the first adder is connected with the carry signal input end of the first adder; the addition output end of the first adder is connected with the second input end of the three-input data selector; the addition output end of the second adder is connected with the second input end of the four-input data selector; the second adder is coupled to the input data output.
The output end of the first lookup table selector is connected with the first input end of the third lookup table selector; the output end of the second lookup table selector is connected with the second input end of the third lookup table selector;
the output end of the first two-input lookup table unit is connected with the first input end of the fourth lookup table selector; the output end of the second input lookup table unit is connected with the second input end of the fourth lookup table selector; the output end of the third second input lookup table unit is connected with the first input end of the fifth lookup table selector; the output end of the fourth second input lookup table unit is connected with the second input end of the fifth lookup table selector;
the output end of the fourth lookup table selector is connected with the first input end of the sixth lookup table selector; the output end of the fifth lookup table selector is connected with the second input end of the sixth lookup table selector;
the data selection ends of the first lookup table selector, the second lookup table selector and the sixth lookup table selector multiplex a seventh input signal; the data selection ends of the third lookup table selector, the fourth lookup table selector and the fifth lookup table selector multiplex an eighth input signal;
the output end of the third lookup table selector is connected with the third input end of the three-input data selector; the output end of the sixth lookup table selector is connected with the third input end of the four-input data selector; the first input end of the three-input data selector is connected with the input port of the shift register.
The output end of the three-input data selector is connected with the first input end of the first two-input data selector and the first input end of the first trigger; the output end of the four-input data selector is connected with the first input end of the second input data selector and the first input end of the second trigger;
the second input end of the first trigger and the second input end of the second trigger are connected with a clock signal in a branch manner;
the output end of the first trigger is simultaneously connected with the second input end of the first two-input data selector and the first input end of the four-input data selector; the output end of the second trigger is connected with the second input end of the second input data selector; the output end of the second trigger is simultaneously connected with the output port of the shift register;
the output port of the first two-input data selector is a first output port of the lookup table circuit capable of configuring various inputs; the output port of the second input data selector is a second output port of the lookup table circuit which can configure various inputs.
2. The customizable multiple input lookup table circuit of claim 1 wherein the configuration of the three input data selector, the four input data selector, the first two input data selector, and the second two input data selector select terminals comprises SRAM chain programming, Flash programming, fuse programming, anti-fuse programming.
3. The customizable multiple input lookup table circuit of claim 1 wherein the first six input lookup table unit, the second six input lookup table unit, the third six input lookup table unit, the fourth six input lookup table unit, the first two input lookup table unit, the second two input lookup table unit, the third two input lookup table unit, the fourth two input lookup table unit, the first lookup table selector, the second lookup table selector, the third lookup table selector, the fourth lookup table selector, the fifth lookup table selector, the sixth lookup table selector, the first adder, the second adder, the third input data selector, the fourth input data selector, the first two input data selector, and the second input data selector are arranged in a polygonal structure, the polygonal structure is a right-angle trapezoid structure or a structure formed by cutting 1 to 2 corners of the right-angle trapezoid, and twelve polygonal structures are laid in the honeycomb regular hexagon structure.
4. A customizable multiple input look-up table circuit according to claim 3, wherein one interior angle of the right trapezoid is 60 °.
5. A customizable FPGA novel array structure, characterized in that the honeycomb-shaped regular hexagon structure of the lookup table circuit capable of configuring multiple inputs according to any one of claims 3 to 4 is tiled to form the FPGA novel array structure.
6. The FPGA novel array structure of claim 5, wherein the honeycomb regular hexagon structure is a centrosymmetric structure; the spacing between the polygonal structures is used for programmable routing; and a blank space is reserved in the center of the honeycomb regular hexagon structure formed by twelve polygonal structures, and the blank space can be used for programmable wiring or logic element arrangement.
7. The FPGA novel array structure of claim 6, wherein the programmable routing resources are distributed over 6 lines: 0 degree, 30 degrees, 60 degrees, 90 degrees, 120 degrees, 150 degrees; wiring resources are distributed in two directions of each line; the programmable wiring resources are composed of three wiring resources of a double wire, a quadruple wire and a long wire, wherein: the double-fold line realizes the connection between the two programmable logic blocks with the distance of 1 and 2 in any direction; the quadruple lines realize the connection between the two programmable logic blocks with the distance of 4 in any direction; the long line realizes the connection between any two programmable logic blocks with the distance of 6 on the same axis to form hierarchical interconnection; starting from any one of the programmable logic blocks, a double line and a quadruple line are connected to each logic block of a ring with the distance of 2 or 4 to the programmable logic block to form a ring surface connection.
8. The FPGA new array structure of claim 7, characterized in that each of said programmable logic blocks is connected to 17 adjacent programmable logic blocks at a distance of 1 and to 66 programmable logic blocks at a distance of 2 by a double line; each programmable logic block is connected with 216 programmable logic blocks with the distance of 4 through a quadruple line, and 360 programmable logic blocks with the distance of 6 are connected through a long line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111189704.4A CN113904677B (en) | 2021-10-11 | 2021-10-11 | Look-up table circuit capable of customizing multiple inputs and novel array structure of FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111189704.4A CN113904677B (en) | 2021-10-11 | 2021-10-11 | Look-up table circuit capable of customizing multiple inputs and novel array structure of FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113904677A true CN113904677A (en) | 2022-01-07 |
| CN113904677B CN113904677B (en) | 2022-07-01 |
Family
ID=79191805
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111189704.4A Active CN113904677B (en) | 2021-10-11 | 2021-10-11 | Look-up table circuit capable of customizing multiple inputs and novel array structure of FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113904677B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114357916A (en) * | 2022-01-11 | 2022-04-15 | 北京汤谷软件技术有限公司 | Chip FPGA prototype verification method and system |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050146352A1 (en) * | 2003-12-24 | 2005-07-07 | Madurawe Raminda U. | Look-up table based logic macro-cells |
| US7394287B1 (en) * | 2007-05-21 | 2008-07-01 | Altera Corporation | Programmable logic device having complex logic blocks with improved logic cell functionality |
| US8010590B1 (en) * | 2007-07-19 | 2011-08-30 | Xilinx, Inc. | Configurable arithmetic block and a method of implementing a configurable arithmetic block in a device having programmable logic |
| CN202340217U (en) * | 2011-11-26 | 2012-07-18 | 深圳市国微电子股份有限公司 | Field programmable gate array (FPGA) element and logic array thereof |
| CN102708264A (en) * | 2012-06-11 | 2012-10-03 | 复旦大学 | Honeycomb hexagonal field programmable gata array (FPGA) structure |
| US20130278289A1 (en) * | 2012-04-18 | 2013-10-24 | Te-Tse Jang | Method and Apparatus for Improving Efficiency of Programmable Logic Circuit Using Cascade Configuration |
| CN103762974A (en) * | 2014-01-26 | 2014-04-30 | 中国电子科技集团公司第五十八研究所 | Multifunctional and configurable six-input lookup table structure |
| CN204290937U (en) * | 2014-10-13 | 2015-04-22 | 无锡中微亿芯有限公司 | Based on the programmable logic unit structure that multi-functional easily extensible connects fast |
| CN105187050A (en) * | 2015-07-23 | 2015-12-23 | 深圳市同创国芯电子有限公司 | Configurable five-input look-up-table circuit |
| JP2018022212A (en) * | 2016-08-01 | 2018-02-08 | 株式会社日立製作所 | Information processing device |
| US20180269880A1 (en) * | 2015-10-15 | 2018-09-20 | Menta | Logic block architecture for programmable gate array |
| CN109714042A (en) * | 2018-11-16 | 2019-05-03 | 京微齐力(北京)科技有限公司 | A kind of multiplexing method of look-up table |
-
2021
- 2021-10-11 CN CN202111189704.4A patent/CN113904677B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050146352A1 (en) * | 2003-12-24 | 2005-07-07 | Madurawe Raminda U. | Look-up table based logic macro-cells |
| US7394287B1 (en) * | 2007-05-21 | 2008-07-01 | Altera Corporation | Programmable logic device having complex logic blocks with improved logic cell functionality |
| CN101312347A (en) * | 2007-05-21 | 2008-11-26 | 阿尔特拉公司 | a programmable logic device having complex logic blocks with improved logic cell functionality |
| US8010590B1 (en) * | 2007-07-19 | 2011-08-30 | Xilinx, Inc. | Configurable arithmetic block and a method of implementing a configurable arithmetic block in a device having programmable logic |
| CN202340217U (en) * | 2011-11-26 | 2012-07-18 | 深圳市国微电子股份有限公司 | Field programmable gate array (FPGA) element and logic array thereof |
| US20130278289A1 (en) * | 2012-04-18 | 2013-10-24 | Te-Tse Jang | Method and Apparatus for Improving Efficiency of Programmable Logic Circuit Using Cascade Configuration |
| CN102708264A (en) * | 2012-06-11 | 2012-10-03 | 复旦大学 | Honeycomb hexagonal field programmable gata array (FPGA) structure |
| CN103762974A (en) * | 2014-01-26 | 2014-04-30 | 中国电子科技集团公司第五十八研究所 | Multifunctional and configurable six-input lookup table structure |
| CN204290937U (en) * | 2014-10-13 | 2015-04-22 | 无锡中微亿芯有限公司 | Based on the programmable logic unit structure that multi-functional easily extensible connects fast |
| CN105187050A (en) * | 2015-07-23 | 2015-12-23 | 深圳市同创国芯电子有限公司 | Configurable five-input look-up-table circuit |
| US20180269880A1 (en) * | 2015-10-15 | 2018-09-20 | Menta | Logic block architecture for programmable gate array |
| JP2018022212A (en) * | 2016-08-01 | 2018-02-08 | 株式会社日立製作所 | Information processing device |
| CN109714042A (en) * | 2018-11-16 | 2019-05-03 | 京微齐力(北京)科技有限公司 | A kind of multiplexing method of look-up table |
Non-Patent Citations (1)
| Title |
|---|
| 张惠国等: "FPGA高性能查找表的设计与实现", 《固体电子学研究与进展》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114357916A (en) * | 2022-01-11 | 2022-04-15 | 北京汤谷软件技术有限公司 | Chip FPGA prototype verification method and system |
| CN114357916B (en) * | 2022-01-11 | 2023-03-10 | 北京汤谷软件技术有限公司 | Chip FPGA prototype verification method and system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113904677B (en) | 2022-07-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6034547A (en) | Method and apparatus for universal program controlled bus | |
| US6781410B2 (en) | Method and apparatus for universal program controlled bus architecture | |
| EP0461798B1 (en) | Configurable interconnect structure | |
| US6191611B1 (en) | Driver circuitry for programmable logic devices with hierarchical interconnection resources | |
| US6128770A (en) | Configurable logic array including IOB to longlines interconnect means for providing selectable access to plural longlines from each IOB (input/output block) | |
| US7304496B2 (en) | Mask-programmable logic device with programmable input/output ports | |
| US5977793A (en) | Programmable logic device with hierarchical interconnection resources | |
| US6747480B1 (en) | Programmable logic devices with bidirect ional cascades | |
| US6798242B2 (en) | Programmable logic device with hierarchical interconnection resources | |
| US6184706B1 (en) | Logic device architecture and method of operation | |
| CN113904677B (en) | Look-up table circuit capable of customizing multiple inputs and novel array structure of FPGA | |
| US7360195B2 (en) | Block level routing architecture in a field programmable gate array | |
| EP2947893B1 (en) | Method and circuit for scalable cross point switching using 3-d die stacking | |
| TWI326531B (en) | Field programmable gate array | |
| JPS6143093A (en) | Resettable complete usable multistage switching circuit network | |
| CN103762974A (en) | Multifunctional and configurable six-input lookup table structure | |
| JP3269526B2 (en) | Programmable logic LSI | |
| US7755387B2 (en) | FPGA having a direct routing structure | |
| US6225823B1 (en) | Input/output circuitry for programmable logic devices | |
| CN113901749B (en) | FPGA array structure and programmable clock wiring method based on subsection space | |
| CN102647181B (en) | Integrated circuit with improved logic cells | |
| CN108153549B (en) | FPGA chip of distributed multi-functional-layer structure | |
| US6285212B1 (en) | Block connector splitting in logic block of a field programmable gate array | |
| CN112668268A (en) | High-flexibility Flash type FPGA programmable logic unit structure | |
| EP1674986A1 (en) | Data processing device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |