CN202340217U

CN202340217U - Field programmable gate array (FPGA) element and logic array thereof

Info

Publication number: CN202340217U
Application number: CN2011204772633U
Authority: CN
Inventors: 傅啟攀; 孙铁力
Original assignee: GUOWEI ELECTRONICS CO Ltd SHENZHEN
Current assignee: Shenzhen Guowei Electronics Co., Ltd.
Priority date: 2011-11-26
Filing date: 2011-11-26
Publication date: 2012-07-18
Anticipated expiration: 2021-11-26

Abstract

The utility model relates to a field programmable gate array (FPGA) element and a logic array thereof. The FPGA element comprises a configurable logic block and an interconnection resource portion distributed around the configurable logic block. The appearance of the FPGA element is in a shape of a regular hexagon. Compared with the prior art, the FPGA element has the advantages of enabling the logic array to use logic resource and silicon sheet resource to the maximum extent and optimizing interconnection delay.

Description

A kind of FPGA primitive and logic array thereof

Technical field

The utility model relates to a kind of FPGA primitive and logic array thereof.

Background technology

Now, programmable logic device (PLD) comprises field programmable gate array, after programming, can realize the integrated circuit of user-defined logic function.A typical FPGA structure, a configurable logic block (CLB) and programmable interconnect array around around programmable input/output circuitry.The primitive of this array structure all is rectangle or square, forms a kind of shape of isolated island.

Fig. 1 is a structure chart of logic array among the traditional rectangular FPGA; This FPGA includes primitive 102 able to programme, and by 102 arrays 101 formed; Fig. 2 is the structure chart of primitive 102 able to programme, and it comprises programmable logic block 201 and programmable logic block input and output interconnection box 202 and lane interconnect switch 203.

As what Fig. 1 saw, go to another member from a primitive able to programme with the shortest distance, it can be selected has only adjacent four primitives up and down, and this arrangement mode has following a few point defect.At first, interconnection needs longer line between the primitive; Secondly, the logic utilance in certain scope is lower.

The utility model content

The utility model technical problem to be solved is: a kind of FPGA primitive and logic array thereof that overcomes above-mentioned defective is provided.

The technical scheme that the utility model adopts is:

A kind of FPGA primitive comprises: configurable logic block and encircle the ICR interconnect resource portion that distributes in said configurable logic block, said FPGA primitive profile is a regular hexagon.

Preferably, said ICR interconnect resource portion comprises: input interconnection box module and lane interconnect switch module.

The utility model also provides a kind of logic array, comprising: at least 7 FPGA primitives as claimed in claim 1 that closely splice each other.

Compared with prior art, the advantage of the utility model is, makes the shape logic array can utilize logical resource to greatest extent, and the silicon chip resource is optimized interconnect delay.

Description of drawings

Fig. 1 is existing traditional FPGA array structure sketch map;

Fig. 2 is the structural representation of primitive in the existing traditional FPGA array;

Fig. 3 is traditional FPGA array and annexation structural representation all around;

Fig. 4 is the regular hexagon FPGA array structure sketch map of the utility model;

Fig. 5 is the primitive structural representation of the utility model;

Fig. 6 is the primitive of the utility model and primitive annexation sketch map all around.

Embodiment

Below in conjunction with accompanying drawing the embodiment of the utility model is done further explanation.

To shown in Figure 6, the technical scheme that the utility model solve the technical problem employing is like Fig. 2, regular hexagon logic array, and the regular hexagon primitive of forming this array, and by the formed array of this primitive repeated arrangement.Described primitive comprises configurable logic block, ICR interconnect resource.Described ICR interconnect resource has comprised interchannel interconnection box module, interconnecting channel, link block.This primitive is a regular hexagon.CLB (being configurable logic block) is connected with interconnecting channel through link block, is connected with adjacent CLB via interconnecting channel again; It is characterized in that, be the center with some CLB, and adjacent other CLB modules with this center become orthohexagonal distribution.

A kind of new FPGA array structure is referred to as the regular hexagon logic array, and this structure can improve the logic utilance effectively and optimize interconnect delay.Concrete structure is as shown in Figure 4.As can be seen from the figure, be different from the FPGA of rectangle or square, the logic array of the FPGA of the utility model is a regular hexagon, and each primitive in the array is accomplished the configurable logic function, and the shape of primitive also is a regular hexagon.With a certain regular hexagon is the center, and adjacent with this center have 6 primitives.Therefore, if from this center, can arrive 6 primitives with the shortest distance;

As shown in Figure 5, the primitive 402 of regular hexagon FPGA also is a regular hexagon, as an example; This primitive 402 has comprised a configurable logic block 501; Around ICR interconnect resource, comprise input interconnection box module 502 around 501, and lane interconnect switch module 503;

As shown in Figure 6, from primitive 402s,, can arrive 6 identical primitives 402 with the shortest cable run distance.

For more traditional square logic array and the quality of the utility model, we design a kind of logical combination, and this logical combination need take 6 CLB, and one of them CLB drives other 5 CLB;

For above-mentioned this logical combination; If use the logic array of traditional square, it may use with 5 CLBs of driving as the center, adds certain CLB on the diagonal; This layout type; For that CLB on the diagonal, it with other CLB track lengths no longer consistent, it needs longer cabling could arrive this CLB;

For above-mentioned this logical combination, if use the logic array of the utility model, it also need take 6 CLB; At this moment, this logical combination is mapped in this orthohexagonal logic array, driving is placed on the CLB at center; Around driven function is placed on; Like this, reach reception distributed delay equably by driving, its needed cabling is also shorter.

Above content is the further explain that combines concrete embodiment that the utility model is done, and can not assert that the practical implementation of the utility model is confined to these explanations.For the those of ordinary skill of technical field under the utility model, under the prerequisite that does not break away from the utility model design, can also make some simple deduction or replace, all should be regarded as belonging to the protection range of the utility model.

Claims

1. a FPGA primitive is characterized in that, comprising: configurable logic block and encircle the ICR interconnect resource portion that distributes in said configurable logic block, said FPGA primitive profile is a regular hexagon.

2. FPGA primitive as claimed in claim 1 is characterized in that, said ICR interconnect resource portion comprises: input interconnection box module and lane interconnect switch module.

3. a logic array is characterized in that, comprising: at least 7 FPGA primitives as claimed in claim 1 that closely splice each other.

4. logic array as claimed in claim 1 is characterized in that, said ICR interconnect resource portion comprises: input interconnection box module and lane interconnect switch module.