CN113901749A - FPGA array structure and programmable clock wiring method based on subsection space segmentation - Google Patents
FPGA array structure and programmable clock wiring method based on subsection space segmentation Download PDFInfo
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- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F30/347—Physical level, e.g. placement or routing
Abstract
The invention discloses an FPGA array structure and a programmable clock wiring method based on subsection space, belongs to the technical field of programmable logic devices, and solves the problems that in the prior art, the density of lookup table logic resources is low, wiring resources are few, and clock delay is difficult to control accurately. Logic elements are arranged into compact polygonal logic blocks, and a hexagonal structure is formed by 12 polygons and is flatly paved into an FPGA array structure; the wiring method of the programmable clock based on the subsection space subsection adopts a wiring clock, a distribution clock and a star-shaped distribution clock, the wiring clock sends a clock signal to the star-shaped clock, and then the star-shaped clock sends the clock signal to a logic block through a fishbone clock structure. The invention provides a novel array structure for the parallel FPGA, so that the element layout density is high, the wiring resources are increased, and the interconnection delay can be better controlled.
Description
Technical Field
The invention relates to the technical field of FPGA design and development, in particular to an FPGA array structure and a programmable clock wiring method based on subsection space segmentation.
Background
A Field Programmable Gate Array (FPGA) is a logic device widely used in many fields such as data processing, communication, and network.
In a large-scale FPGA chip, wiring resources account for more than 70% of the chip area, and meanwhile, interconnection delay also accounts for more than 70% of the overall delay, so that the performance of the wiring resources determines the performance of an FPGA device to a great extent. Conventional programmable interconnect resources are generally formed in a planar structure by horizontal interconnect resources and vertical interconnect resources, which are connected to each other through a switch matrix, as shown in fig. 1. The traditional horizontal and vertical interconnection has low arrangement mode density, less wiring resources and larger interconnection delay.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the defects of low arrangement mode density, less wiring resources, larger chip area and larger interconnection delay of the traditional FPGA horizontal and vertical interconnection in the prior art, thereby providing an FPGA array structure which comprises a programmable logic block and programmable wiring resources; each programmable logic block is distributed into a polygonal structure, the polygonal structure is a right-angle trapezoid structure or a structure formed by cutting 1 to 2 angles off from a right-angle trapezoid, twelve polygonal structures are laid in a honeycomb regular hexagon structure, and the FPGA is composed of a plurality of programmable logic blocks; the honeycomb regular hexagon structure is a centrosymmetric structure; the spacing between the polygonal structures is used for programmable routing; and a blank space is reserved in the center of the honeycomb regular hexagon structure formed by twelve polygonal structures, and the blank space can be used for programmable wiring or logic element arrangement.
Further, the programmable link resources are distributed on 6 lines: 0 degree, 30 degrees, 60 degrees, 90 degrees, 120 degrees, 150 degrees; wiring resources are distributed in two directions of each line; the programmable connecting line resource is composed of a double-line connecting line resource, a quadruple-line connecting line resource and a long-line connecting line resource, wherein: the double-fold line realizes the connection between the two programmable logic blocks with the distance of 1 and 2 in any direction; the quadruple lines realize the connection between the two programmable logic blocks with the distance of 4 in any direction; the long line realizes the connection between any two programmable logic blocks with the distance of 6 on the same axis to form hierarchical interconnection; starting from any one of the programmable logic blocks, a double line and a quadruple line are connected to each logic block of a ring with the distance of 2 or 4 to the programmable logic block to form a ring surface connection.
Further, the polygonal structure is a right trapezoid structure or a structure formed by cutting 1 to 2 corners of the right trapezoid.
Further, the right trapezoid has an angle of 60 °.
Further, each of the programmable logic blocks is connected with 17 adjacent programmable logic blocks with the distance of 1 and is connected with 66 programmable logic blocks with the distance of 2 through a double line; each programmable logic block is connected with 216 programmable logic blocks with the distance of 4 through a quadruple line, and 360 programmable logic blocks with the distance of 6 are connected through a long line.
Another technical problem to be solved by the invention is to overcome the defects of few wiring resources and difficult synchronization of clocks of the traditional FPGA in the prior art, so as to provide a programmable clock wiring method based on subsection space segmentation, which is characterized in that an FPGA array is an FPGA array structure as claimed in any one of claims 1 to 4, the FPGA chip is divided into a plurality of clock areas with the same size according to the size of the FPGA chip, the clock areas are arranged in an array manner, and the adjacent clock areas are spliced together; the programmable clock network comprises a wiring clock, a distribution clock and a star clock structure positioned in a clock area; the wiring clock is wired in the horizontal direction and the vertical direction; the wiring clock consists of a fixed-delay clock wiring section and a programmable bidirectional clock driver; the programmable bidirectional clock driver is positioned at the splicing position of two adjacent clock areas, and the wiring clock is programmable; the distribution clock is wired in the horizontal direction, the 30-degree direction, the 60-degree direction, the vertical direction, the 120-degree direction and the 150-degree direction; the distribution clock is composed of a fixed delay clock distribution section and a programmable bidirectional clock driver;
the wiring clock is connected with a root clock node of the distribution clock at the splicing position of the clock area, the wiring clock sends a clock signal to the root clock node in the clock area from a clock input port, the distribution clock sends the clock signal to the star clock structure from the root clock node, then the star clock structure sends the clock signal to each leaf clock node, and the leaf clock nodes send the clock signal to the programmable logic block through the fishbone clock structure.
Furthermore, the clock signal of the clock node is derived from a horizontal wiring clock, the clock node sends the clock signal to the star clock structure through a one-way programmable driver, and the star clock structure drives each leaf clock node through enabling.
Furthermore, the star clock drives each leaf clock node through enabling, and when the logic circuit of the corresponding leaf clock node does not work, the clock drive is closed, and the corresponding leaf clock node is cut off.
The technical scheme of the invention has the following advantages:
1. according to the FPGA array structure provided by the invention, logic elements are arranged into compact polygonal logic blocks, twelve polygons are placed in the hexagons, and then the hexagons are tiled into the FPGA array structure, so that the element layout density is high, the wiring resources are increased, and the interconnection delay can be better controlled under the condition that the chip area is not increased;
2. the invention provides a wiring method of a programmable clock based on subsection space subsection, which adopts 2 clock types of a wiring clock and a star clock, wherein the wiring clock with programmable fixed time delay sends a clock signal to the star clock, and then the star clock sends the clock signal to a logic block PLB, wherein the lengths of clock wires from all the star clocks to the logic block PLB are consistent, so that the wiring method can achieve very accurate clock synchronization and deviate from the clock signal which is almost zero.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a diagram of a conventional FPGA architecture;
FIG. 2 is a schematic diagram of a hexagonal structure formed by twelve polygonal PLBs according to a first embodiment of the present invention;
fig. 3 is a schematic diagram of a novel array structure of a hexagonal tiled FPGA according to a first embodiment of the present invention;
FIG. 4 is a schematic view of a right trapezoid PLB provided in a first embodiment of the present invention, with angles 1 to 2 cut away;
fig. 5 is a schematic diagram of a routing resource of a novel array structure of an FPGA according to a first embodiment of the present invention;
FIG. 6 is a schematic diagram of a PLB provided with a distance of 1 in a first embodiment of the present invention;
FIG. 7 is a schematic diagram of a PLB provided with a distance of 2 in a first embodiment of the present invention;
FIG. 8 is a schematic diagram of a PLB provided at distances 1 and 2 in a first embodiment of the present invention;
FIG. 9 is a schematic diagram of a PLB provided at a distance of 4 in accordance with a first embodiment of the present invention;
FIG. 10 is a general diagram of a programmable clock routing method based on fractional space segmentation according to a second embodiment of the present invention;
FIG. 11 is a diagram showing the leaf clocks on a star-type distributed clock based on a fractional space segment programmable clock routing method according to a second embodiment of the present invention.
Fig. 12 is a programming diagram of a programmable clock routing method based on fractional space segmentation according to a second embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1
As shown in fig. 2 and fig. 3, the FPGA array structure provided in this embodiment includes a programmable logic block PLB and programmable routing resources; each programmable logic block is arranged in a polygonal structure, twelve polygonal structures are laid in a honeycomb regular hexagon structure, and the FPGA is composed of a plurality of programmable logic blocks; the honeycomb regular hexagon structure is a centrosymmetric structure; the spacing between the polygonal structures is used for programmable routing; and a blank space is reserved in the center of the honeycomb regular hexagon structure formed by twelve polygonal structures, and the blank space can be used for programmable wiring or logic element arrangement.
According to the FPGA array structure provided by the embodiment, the logic elements are arranged into the compact polygonal logic blocks, twelve polygons are placed in the hexagons, and then the hexagons are tiled into the FPGA array structure, so that the element layout density is high, the wiring resources are increased, and the interconnection delay can be well controlled under the condition that the chip area is not increased.
As shown in fig. 5, the programmable routing resources are distributed over 6 lines: 0 degree, 30 degrees, 60 degrees, 90 degrees, 120 degrees, 150 degrees; wiring resources are distributed in two directions of each line; the programmable wiring resources are composed of three wiring resources of a double wire, a quadruple wire and a long wire, wherein: the double-fold line realizes the connection between the two programmable logic blocks with the distance of 1 and 2 in any direction; the quadruple lines realize the connection between the two programmable logic blocks with the distance of 4 in any direction; the long line realizes the connection between any two programmable logic blocks with the distance of 6 on the same axis to form hierarchical interconnection; starting from any one of the programmable logic blocks, a double line and a quadruple line are connected to each logic block of a ring with the distance of 2 or 4 to the programmable logic block to form a ring surface connection.
As shown in fig. 4, the polygonal structure is a right trapezoid structure or a structure formed by cutting 1 to 2 corners of a right trapezoid, a and b are structures of a right triangle with any one corner cut, and c is a structure of a right triangle with two corners cut at random.
Specifically, the right trapezoid has an angle of 60 ° at one corner.
Each of said programmable logic blocks is connected to 17 adjacent ones of said programmable logic blocks at a distance of 1, as shown in fig. 6, and to 66 of said programmable logic blocks at a distance of 2, as shown in fig. 7, by a double line; as shown in fig. 8, each of the programmable logic blocks is connected to 216 programmable logic blocks at a distance of 4 by a quadruple line, and as shown in fig. 9, 360 programmable logic blocks at a distance of 6 are connected by a long line.
Example 2
Another embodiment provided by the present application provides a programmable clock wiring method based on subsection space segmentation, as shown in fig. 10, an FPGA array is an FPGA array structure of the present invention, an FPGA chip is divided into a plurality of clock regions with the same size according to the size of the FPGA chip, the clock regions are arranged in an array, and adjacent clock regions are spliced together; the programmable clock network comprises a wiring clock, a distribution clock and a star clock structure positioned in a clock area; the wiring clock is wired in the horizontal direction and the vertical direction; the wiring clock consists of a fixed-delay clock wiring section and a programmable bidirectional clock driver; the programmable bidirectional clock driver is positioned at the splicing position of two adjacent clock areas, and the wiring clock is programmable; the distribution clock is wired in the horizontal direction, the 30-degree direction, the 60-degree direction, the vertical direction, the 120-degree direction and the 150-degree direction; the distribution clock is composed of a fixed delay clock distribution section and a programmable bidirectional clock driver;
the wiring clock is connected with a root clock node of the distribution clock at the splicing position of the clock area, the wiring clock sends a clock signal to the root clock node in the clock area from a clock input port, the distribution clock sends the clock signal to the star clock structure from the root clock node, then the star clock structure sends the clock signal to each leaf clock node, and the leaf clock nodes send the clock signal to the programmable logic block through the fishbone structure clock. Fig. 11 shows a clock structure of a fishbone type structure.
The wiring method of the programmable clock based on subsection space provided by the embodiment adopts 3 clock types of a wiring clock, a distribution clock and a star clock, the programmable wiring clock with fixed time delay sends a clock signal to the distribution clock, the distribution clock is sent to the star clock, and then the star clock sends the clock signal to a logic block PLB, wherein the lengths of clock wires from all the star clocks to the logic block PLB are consistent, so that the wiring method can achieve very accurate clock synchronization and deviate from the clock signal which is almost zero.
Specifically, the clock signal of the clock node is derived from a horizontal wiring clock, the clock node sends the clock signal to the star clock structure through a one-way programmable driver, and the star clock structure drives each leaf clock node through enabling.
Specifically, the star clock drives each leaf clock node through enabling, and when the logic circuit of the corresponding leaf clock node does not work, the clock drive is turned off, and the corresponding leaf clock node is cut off.
As shown in fig. 12, an example of a programming implementation based on a fractional space segment programmable clock routing method. In the graph, a and B are root clock nodes of two clock regions, and it can be seen from the graph that the distances from the root clock nodes of a and B to a clock input port are different, in a traditional FPGA clock network structure, a clock input from the clock input port has a large delay difference to the root clock nodes of a and B, and meanwhile, some deviations can exist in the clock regions, thereby affecting some high-speed applications. The programmable clock wiring method based on subsection space segmentation can well solve the problem based on the programmability of the wiring clock and the distribution clock, ensure that the clock delay of two root clock nodes A and B is zero, simultaneously ensure that the clock delay of a programmable logic block PLB in each clock area is zero, and improve the whole application performance.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (8)
1. An FPGA array structure is characterized by comprising a programmable logic block and programmable wiring resources; each programmable logic block is arranged in a polygonal structure, twelve polygonal structures are laid in a honeycomb regular hexagon structure, and the FPGA is composed of a plurality of programmable logic blocks;
the honeycomb regular hexagon structure is a centrosymmetric structure;
the spacing between the polygonal structures is used for programmable routing;
and a blank space is reserved in the center of the honeycomb regular hexagon structure formed by twelve polygonal structures, and the blank space can be used for programmable wiring or logic element arrangement.
2. The FPGA array structure of claim 1, wherein said programmable routing resources are distributed over 6 lines: 0 degree, 30 degrees, 60 degrees, 90 degrees, 120 degrees, 150 degrees; wiring resources are distributed in two directions of each line; the programmable wiring resources are composed of three wiring resources of a double wire, a quadruple wire and a long wire, wherein: the double-fold line realizes the connection between the two programmable logic blocks with the distance of 1 and 2 in any direction; the quadruple lines realize the connection between the two programmable logic blocks with the distance of 4 in any direction; the long line realizes the connection between any two programmable logic blocks with the distance of 6 on the same axis to form hierarchical interconnection; starting from any one of the programmable logic blocks, a double line and a quadruple line are connected to each logic block of a ring with the distance of 2 or 4 to the programmable logic block to form a ring surface connection.
3. The FPGA array structure of claim 1, wherein the polygonal structure is a right trapezoid structure or a structure formed by truncating 1 to 2 corners of the right trapezoid.
4. The FPGA array structure of claim 3, wherein the right angle trapezoid has an angle of 60 ° at one corner.
5. The FPGA array structure of claim 2, wherein each of said programmable logic blocks is connected to 17 adjacent ones of said programmable logic blocks at a distance of 1 and to 66 of said programmable logic blocks at a distance of 2 by a doubling line; each programmable logic block is connected with 216 programmable logic blocks with the distance of 4 through a quadruple line, and 360 programmable logic blocks with the distance of 6 are connected through a long line.
6. A programmable clock wiring method based on subsection space segmentation is characterized in that an FPGA array is in an FPGA array structure as claimed in any one of claims 1 to 4, the FPGA chip is divided into a plurality of clock areas with the same size according to the size of the FPGA chip, the clock areas are arranged in an array form, and adjacent clock areas are spliced together; the programmable clock network comprises a wiring clock, a distribution clock and a star clock structure positioned in a clock area; the wiring clock is wired in the horizontal direction and the vertical direction; the wiring clock consists of a fixed-delay clock wiring section and a programmable bidirectional clock driver; the programmable bidirectional clock driver is positioned at the splicing position of two adjacent clock areas, and the wiring clock is programmable; the distribution clock is wired in the horizontal direction, the 30-degree direction, the 60-degree direction, the vertical direction, the 120-degree direction and the 150-degree direction; the distribution clock is composed of a fixed delay clock distribution section and a programmable bidirectional clock driver;
the wiring clock is connected with a root clock node of the distribution clock at the splicing position of the clock area, the wiring clock sends a clock signal to the root clock node in the clock area from a clock input port, the distribution clock sends the clock signal to the star clock structure from the root clock node, then the star clock structure sends the clock signal to each leaf clock node, and the leaf clock nodes send the clock signal to the programmable logic block through the fishbone clock structure.
7. The fractional-spatial-segment-based programmable clock routing method of claim 6, wherein the clock signal of the clock node is derived from a horizontal routing clock, the clock node sends a clock signal to the star clock structure through a one-way programmable driver, and the star clock structure drives each leaf clock node through an enable.
8. The fractional-space-segment-based programmable clock routing method of claim 6, wherein the star clock drives each leaf clock node by enabling, and turns off the clock drive to switch off the corresponding leaf clock node when the logic circuit of the corresponding leaf clock node is not operating.
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