CN102708264B

CN102708264B - Honeycomb hexagonal field programmable gata array (FPGA) structure

Info

Publication number: CN102708264B
Application number: CN201210189713.8A
Authority: CN
Inventors: 陈利光; 陈丽; 童家榕
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2012-06-11
Filing date: 2012-06-11
Publication date: 2015-05-13
Anticipated expiration: 2032-06-11
Also published as: CN102708264A

Abstract

The invention belongs to the technical field of programmable logic devices, in particular to a honeycomb hexagonal field programmable gata array (FPGA) structure. An FPGA consists of a hexagonal unit; a basic logic unit is hexagonal, and has a completely symmetrical structure; and physics realization is convenient during array extension. A programmable connecting line resource has a three-axis structure and is distributed along three diagonal lines (0 degrees, 120 degrees and 240 degrees), a wiring resource structure can be partitioned into a twofold line, a quintuple line and long lines according to the length of an interconnecting line, and the interconnecting lines of the twofold line and the quintuple line can be connected to each unit of a ring with corresponding distance; and the long lines have point connecting structures and are distributed in three axis directions, so that linear connection at the distance of 12 can be realized. The honeycomb hexagonal FPGA structure has the advantages of ring surface connecting characteristic of an interconnecting structure, uniform distribution of connecting lines, high utilization ratio, high speed and contribution to improving the logic density and time sequence performance.

Description

A kind of honeycomb hexagon field programmable logic array (FPLA) structure

Technical field

The invention belongs to programming device technical field, be specifically related to a kind of field programmable device structure.

Background technology

Field programmable logic device (FPGA) is made up of programmable logic block (PLB) and programmable interconnect, and programmable logic block is connected by programmable interconnect.In large-scale F PGA chip, interconnection resource accounts for more than 70% of chip area, and interconnected time delay simultaneously also accounts for more than 70% of overall time delay, and therefore the performance of interconnection resource determines the performance of FPGA device to a great extent.Traditional programmable interconnect resource all forms planar structure [1-2] by horizontal interconnect resource and perpendicular interconnection resource usually, is connected each other, as shown in Figure 1 by switch matrix.Scale along with FPGA becomes increasing, and the interconnect resource of conventional planar structure constrains the lifting of FPGA scale and speed.

This is because traditional interconnection structure is divided into horizontal interconnect resource and perpendicular interconnection resource interconnect resource, and two logical blocks of the interconnection needed in application are not often in a level or perpendicular line, therefore no matter these two logical blocks are apart from how close, connecting these two logical blocks at least all will through a programmable switch, very large to the rate of FPGA like this.

In order to address this problem, document [3] proposes the interconnection resource kind of a kind of 45 degree, but this one being traditional structure simply expands.In industry member, XILINX proposes direct interconnection concept [1] (direct connection) in VIRTEX-II chip, its main thought is exactly increase a kind of interconnect resource of being direct interconnection, directly can connect 8 logical blocks on a logical block side, as shown in Figure 2, and do not need through programmable switch, the speed of some adjacency lines can be accelerated like this, but to other longer lines or helpless.

In nearest VIRTEX-5 chip, part 5 times of lines of XILINX have employed and turn line structure [4] and (be also hardwired, hard wired), as shown in Figure 3,5 times of lines that unit 1 exports can reach 5 equidistant positions such as unit 2,3,4,5,6 respectively, wherein unit 6 and unit 1 are in same vertical channel, and its wiring quantity is 12, and other position wiring quantity are 3.This 5 times of lines turn line structure and accelerate moderate distance link speed, but thisly turn line just minority in VIRTEX-5, its agent structure still based on horizontal vertical channel architecture, in essence still based on the interconnect architecture of passage.

list of references:

[1] V. Betz, J. Rose and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs[M], Kluwer Academic Publishers, 1999.

[2] Ian Kuon, Russell Tessier, and Jonathan Rose, “ FPGA Architecture: Survey and Challenges”, Now Publishers Inc, 2008

[3] Sumanta Chaudhuri, “Diagonal Tracks in FPGAs: A Performance Evaluation”, International Symposium on Field Programmable Gate Arrays 2009, p245-248

[4] Xilinx, Inc., Virtex/Virtex-II/Virtex-4/Virtex-5/Spartan/Spartan-II/Spartan-3 FP- GA Family Complete Data Sheet.

[5] Altera Corp., Stratix/Stratix-II/Stratix-III/Cyclone/Cyclone-II Device Handbook.

[6] David Lewis，”The Stratix II logic and routing architecture”，13th international symposium on Field-programmable gate arrays 2005，P14 – 20。

Summary of the invention

For the deficiency of traditional structure, the present invention proposes a kind of honeycomb hexagon field programmable logic array (FPLA) structure connected based on anchor ring.This structure line is evenly distributed, and utilization factor is high, and speed is fast, is conducive to improving logic density and timing performance.

Honeycomb hexagon field programmable logic (FPGA) array structure connected based on anchor ring that the present invention proposes, by programmable logic block (PLB) and programmable links resource composition, as shown in Figure 4, this interconnect architecture is specific as follows:

hexagon: basic programmable logic block (PLB) unit is cellular hexagonal structure, and FPGA is made up of some hexagon PLB unit.

three axles: programmable links resource distribution is 3 diagonals: 0 degree, 120 degree, 240 degree, is designated as X, Y, Z 3 axis successively; Each axis is distributed with interconnection resource; As shown in dotted line X Y Z in Fig. 4.

stratification is interconnected: interconnection resource able to programme is made up of two times of lines, five times of lines and long line three kinds of interconnection resources:

In quadrangular array structure, the definition of two cell distances is along the bee-line between the unit of two, line direction, is namely cornerwise rectangular length and wide sum with these two unit.Equally, in hexagonal array, any two cell distances are also defined as along 3 axial bee-lines of symmetry.

It is connection between 1 and the unit of 2 that two times of lines can realize any direction two distances; Five times of lines can realize any direction two distances be 5 unit between connection; It is the connection between the unit of 12 that long line can realize any two distances on same axis.

anchor ring connects: from any one PLB, two times of lines and five times of lines can be connected to its distance on each unit of the ring being 2 or 5.

symmetrical structure: this structure is full symmetric (Central Symmetry) structure, facilitates physics realization when array extension.

Global routing of the present invention resource has anchor ring connection performance:

(1) in conventional programmable logic device, interconnection line is only connected to the several points on straight line, and certain class interconnection line that the present invention PLB sets out can be connected to all PLB on a ring, as shown in Figure 4.

(2) interconnection line of different length forms multiple interconnected ring that can reach.

Article (3) one, interconnection line can reach interconnected ring at different location deflection 60 degree of angles.

(4) may there is different line in the same PLB arrived on interconnected ring from a PLB, as shown in Figure 4.

Hexagonal PLB presentation logic unit, arranges according to honeycomb hexagonal structure.Exemplarily, point centered by PLB is marked by Dark grey in figure, fine line represents the connection between PLB and PLB, can find out in figure, center PLB directly can be connected with all grey PLB and light grey PLB, and by two times of lines and five times of lines, center PLB can be connected on all PLB on 1,2,5 three ring centered by it, therefore, this structure is the structure that an anchor ring connects.Meanwhile, long line is the same with traditional F PGA, be distributed in X Y Z tri-directions upper, and long line quantity XYZ tri-axis of orientations are symmetrical, and therefore, it is again three-axis structure.

Accompanying drawing explanation

Fig. 1 is traditional F PGA interconnection resource structure.

The direct interconnection line structure of Fig. 2.

Fig. 3 is that VIRTEX-5 turns line structure.

Fig. 4 is hexagon interconnection resource structure in this paper.

Embodiment

Interconnection resource structure of the present invention can be divided into according to the length of interconnection line: two times of lines, five times of lines and long lines three kinds of interconnection resources are formed: it is connection between 1 and the unit of 2 that two times of lines can realize any direction two distances.Five times of lines can realize any direction two distances be 5 unit between connection.It is the connection between 1 and the unit of 2 that long line can realize any two distances on same axis.Each hexagonal cells has 6 limits, and in order to effectively distinguish interconnection line, interconnection line can be thought from a limit of center PLB, ends at a limit of another PLB.

Two times of lines are connect two PLB that distance is 2, and two times of lines have a centre tap simultaneously, also can be connected to 2 PLB adjacent on path, therefore, from center PLB's thus two times of lines be connected to distance be 1 and 2 two rings on so PLB.

Five times of lines are connect two PLB that distance is 5, from five times of lines of center PLB, after different distance, turn 60 degree of angles, be connected to distance be 5 ring on different PLB.

From starting point and the terminal of line, line starts from 6 limits of center PLB, stops and inner side edge on anchor ring.Therefore, girth and the channel width of the wiring quantity that center PLB sets out and ring are directly proportional, and channel width refers to the quantity of the connecting line of the same race with identical starting point and terminating point.Twice line ends at inside 2 rings, has 18 limits inside 2 rings, and therefore when channel width is 1 time, 2 times of line minimum numbers have 18; Equally, five times of lines end at inside 5 rings, have 72 limits inside 5 rings, and therefore when channel width is 1 time, 5 times of line minimum numbers have 72;

Long line length is 12, and long line only just has at three axis directions, and long line does not turn round, and only connects two PLB on same axis.

From function distinguishing, key at a distance connection be responsible for by long line, and proof load little, speed is fast; Five times of lines and two times of lines are as local short circuit line, owing to having the characteristic that anchor ring connects, compare the some syndeton of traditional horizontal vertical passage, the signal that optional position is connected just can be able to be arrived at the destination by fewer switch, thus improves timing performance.

Claims

1. a field programmable logic device array structure, is characterized in that by programmable logic block and programmable links resource composition; Wherein, each PLB unit is cellular regular hexagon structure, and FPGA is made up of some PLB unit, and centered by symmetrical structure;

Programmable links resource distribution is 3 diagonals: 0 degree, 120 degree, 240 degree, is designated as X, Y, Z 3 axis successively; Each axial both direction is distributed with interconnection resource;

Programmable links resource is made up of two times of lines, five times of lines and long line three kinds of interconnection resources, wherein:

Two times of lines realize any direction two distances be 1 and 2 PLB unit between connection; Five times of lines realize any direction two distances be 5 PLB unit between connection; It is the connection between the PLB unit of 12 that long line realizes any two distances on same axis, forms stratification interconnected;

From any one PLB unit, two times of lines and five times of lines are connected to this PLB cell distance on each unit of the ring being 2 or 5, form anchor ring and connect;

Wherein, symbol FPGA is field programmable logic device, and PLB is programmable logic block.

2. field programmable logic device array structure according to claim 1, is characterized in that:

By two times of lines, each PLB unit and distance be 1 adjacent 6 PLB unit be connected, and to be connected with 12 PLB unit that distance is 2; By five times of lines, each PLB unit and distance be 5 30 PLB unit be connected, it is the PLB unit of 12 that long line connects distance on 3 axis.