CN101494455B - Multi-hierarchy FPGA - Google Patents
Multi-hierarchy FPGA Download PDFInfo
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- CN101494455B CN101494455B CN2009100584327A CN200910058432A CN101494455B CN 101494455 B CN101494455 B CN 101494455B CN 2009100584327 A CN2009100584327 A CN 2009100584327A CN 200910058432 A CN200910058432 A CN 200910058432A CN 101494455 B CN101494455 B CN 101494455B
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Abstract
The invention discloses a multi-level FPGA, which relates to an integrated circuit technology. The invention comprises a configurable logical block CLB, an interconnection resource and an input-output block IOB, wherein, the interconnection resource comprises a channel, a switch block SB and a connecting block CB, and the CLB is connected with the channel by the connecting block CB; the multi-level FPGA is characterized in that the FPGA comprises at least three layers; each layer comprises a plurality of modules, each module comprises a plurality of arithmetic units, and the arithmetic units and the modules are connected by the interconnection resource; the modules at lower layers constitute the arithmetic units of the modules at higher layers; the passage width between the modules at the lower layers is greater than the passage width between the modules at the higher layers; and the module at the lowest layer is the CLB. The beneficial effects of the FPGA are as follows: the FPGA improves the utilization efficiency of the interconnection resource, and is provided with better delay characteristics compared with the prior art, and the FPGA is more beneficial to the high integration and miniaturization of the chip.
Description
Technical field
The present invention relates to integrated circuit.
Background technology
Traditional island-style (isolated island type) FPGA be by configurable logic block (Configurable Logic Block, CLB), interconnection resource (Route Resource, RRS) and input/output block (I/O Block, IOB) three parts.Interconnection resource comprise switch block (Switch Block, SB) and contiguous block (Connection Block, CB).As Fig. 1 is the structure diagram of isolated island type FPGA, CLB and SB are according to the array symmetric arrays, this height symmetrical structure greatly facilitates writing of software, but still exists bigger problem aspect following two: the structural high symmetry of isolated island FPGA has determined its chip wiring resource fully not use; Wiring delay is bigger.
Summary of the invention
Technical problem to be solved by this invention is, a kind of multi-hierarchy FPGA is provided, and can make full use of interconnection resource to greatest extent, has good time-delay characteristics simultaneously.
The technical scheme that the present invention solve the technical problem employing is, multi-hierarchy FPGA, comprise configurable logic block CLB, interconnection resource, input/output block IOB, described interconnection resource comprises passage, switch block SB and contiguous block CB, and CLB is connected with passage by contiguous block CB; It is characterized in that FPGA comprises at least three layers; Each layer comprises a plurality of modules, and each module comprises a plurality of arithmetic elements, between the arithmetic element, connect by interconnection resource between each module; Modules at lower layers constitutes the arithmetic element of higher level module; Channel width between the modules at lower layers is greater than the channel width between the high-rise module; The lowermost layer module is CLB.
Described FPGA is divided into three layers, and the arithmetic element of ground floor is CLB.The arithmetic element of each layer is an arranged.
The invention has the beneficial effects as follows, improved the utilization ratio of interconnection resource,, have better delay character, and be more conducive to the Highgrade integration and the miniaturization of chip than prior art.
The present invention is further illustrated below in conjunction with the drawings and specific embodiments.
Description of drawings
Fig. 1 a is the prior art constructions schematic diagram, and Fig. 1 b is the annexation schematic diagram of CLB, SB, CB and passage.
Fig. 2 is a hierarchical structure schematic diagram of the present invention.
Fig. 3 is a CLB structural representation of the present invention.
Fig. 4 is ground floor (LEV-1) structural representation.
Fig. 5 is the second layer (LEV-2) structural representation.
Fig. 6 is the 3rd layer of (LEV-3) structural representation.
Embodiment
The present invention proposes a kind of new FPGA structure, is referred to as Multi-level FPGA (multi-hierarchy FPGA), and this structure can effectively solve the problem of this two aspect, and concrete structure as shown in Figure 2.As can be seen from the figure, be different from isolated island FPGA, FPGA of the present invention is divided into many levels, each level is finished function corresponding, and the channel width W in each level (representing the number of lines in the passage is W) is along with increasing of level reduces, thereby make full use of interconnection resource to greatest extent, be formed by connecting because the wiring between most logical blocks all is a interconnection resource (short-term) by low level, so the time-delay characteristics of circuit are also better.
As shown in Figure 3, the CLB of multi-hierarchy FPGA is identical with the CLB of common FPGA, and as an example, CLB of the present invention comprises 4 basic logic units, and (Basic LogicElement, BLE), pin comprises 10 inputs and 4 outputs, specifically arranges and sees Fig. 3.CLB is as the arithmetic element of lowermost layer.
Fig. 4 is the structural representation of ground floor module.In the present embodiment, a module (being called LEV-1) of ground floor is formed channel width W=20 by 4 CLB and 9 SB.CLB module C0～C3 and passage carry out exchanges data all to be needed through contiguous block (ConnectionBlock, CB are expressed as arrow among the figure).The area of contiguous block and delay are subjected to directly influencing of channel width and CLB number of pins.Channel width is big more, and number of pins is many more, and the area of contiguous block is big more, postpones also can be linear growth.
Fig. 5 is that a module (being called LEV-2) of the second layer is made up of 4 LEV-1 and 9 SB than the modular structure schematic diagram of the second layer of Fig. 4 higher level time, and channel width W=15, LEV-1 have 8 inputs and 4 outputs.
Fig. 6 is the top layer of multi-hierarchy FPGA, is made up of 4 LEV-2 and 9 SB, and channel width W=10, LEV-2 have 4 inputs and 4 outputs.
From to above analysis at all levels as can be seen, Multi-level FPGA has 3 levels, has Duoed two levels than isolated island FPGA, and along with the raising of level, the corresponding minimizing of channel width W.LEV-1 is as the bottom, and its interconnection resource mainly carries out the connection of arithmetic element; The interconnection resource of LEV-2 is responsible for partial arithmetic and partial data transmission, and the top layer of Fig. 6 only is responsible for transfer of data.
Embodiment
For relatively isolated island FPGA and Multi-level FPGA consider following embodiment in the quality aspect delay and the area.
Realize one 8 full adder with isolated island FPGA and multi-hierarchy FPGA of the present invention respectively.In 8 full adders, two group of 8 bit data of establishing input is respectively A1, A2, and A3, A4, A5, A6, A7 and B1, B2, B3, B4, B5, B6, B7, carry is Cin.Each CLB can realize one one adder, therefore needs 8 CLB, and Fig. 1 has marked out 8 CLB that isolated island FPGA uses, and such distribution is the bigger distribution mode of possibility in the practical application.Among Fig. 1 a, the black square is represented SB, and white square is represented CLB, and the line segment between the black square is represented passage, connects by CB between CLB and the passage, between per two CLB two CB is arranged all, and CB does not draw in Fig. 1 a, is expressed as black rectangle in Fig. 1 b.Each CLB can regard 1 full adder as, has used 3 inputs and 2 outputs of this CLB, and 8 CLB are equivalent to form a CLB chain, and the order of this CLB chain is set to 1-2-3-4-5-6-7-8, as shown in Figure 1.The carry value of previous CLB output is as the carry input of next CLB, and the isolated island FPGA of prior art that hence one can see that realizes that 8 full adders need be through 14 CB (not marking among the figure) and 5 SB (the black square of band white circle among Fig. 1 a).
Eight CLB that the multi-hierarchy FPGA of present embodiment is used are respectively 4 CLB of LEV1 (0) among 4 CLB of LEV1 (0) among the LEV2 (0) and the LEV2 (3).Multi-hierarchy FPGA of the present invention is finished 8 full adders also to be needed through 14 CB and 5 SB, owing to adopted hierarchical setting, all computings are concentrated among the LEV1 (0) of the LEV1 (0) of LEV2 (0) and LEV2 (3) and carry out, carry out and transfer of data changed at LEV-2 and top layer, can reduce like this and realize the required hardware resource of function.From Fig. 4,5,6 as can be known 5 SB of process be respectively the S2 (0) of S2 (4), S2 (5), S2 (8), S3 (4) and another second layer module.The scale of these SB all those 5 SB than isolated island FPGA is little.Therefore overall wiring area is littler than isolated island FPGA, and simultaneously because the line between SB is shorter, so time delay is also little than isolated island FPGA.
Claims (2)
1. multi-hierarchy FPGA comprises configurable logic block CLB, interconnection resource, input/output block IOB, and described interconnection resource comprises passage, switch block SB and contiguous block CB, and CLB is connected with passage by contiguous block CB; It is characterized in that FPGA comprises at least three layers; Each layer comprises a plurality of modules, and each module comprises a plurality of arithmetic elements, between the arithmetic element, connect by interconnection resource between each module; Modules at lower layers constitutes the arithmetic element of higher level module; Channel width between the modules at lower layers is greater than the channel width between the high-rise module; The lowermost layer module is CLB; The interconnection resource of the bottom mainly carries out the connection of arithmetic element; The interconnection resource of the last layer of the bottom is responsible for partial arithmetic and partial data transmission, and top layer only is responsible for transfer of data.
2. multi-hierarchy FPGA as claimed in claim 1 is characterized in that, the arithmetic element of each layer is an arranged.
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| CN2009100584327A CN101494455B (en) | 2009-02-26 | 2009-02-26 | Multi-hierarchy FPGA |
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| CN2009100584327A CN101494455B (en) | 2009-02-26 | 2009-02-26 | Multi-hierarchy FPGA |
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| CN101494455B true CN101494455B (en) | 2011-02-16 |
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| CN102314528B (en) * | 2010-07-07 | 2013-05-01 | 中国科学院微电子研究所 | Resource sharing system and method for digital large-scale integrated circuit |
| CN108427829B (en) * | 2018-02-09 | 2022-11-08 | 京微齐力(北京)科技有限公司 | FPGA with common line structure |
| DE102019006292A1 (en) * | 2019-09-05 | 2021-03-11 | PatForce GmbH | Arrangement of switch boxes |
| CN111725187B (en) * | 2020-07-01 | 2022-05-31 | 无锡中微亿芯有限公司 | Multi-die FPGA (field programmable Gate array) formed based on silicon connection layer with universal structure |
| CN112947282B (en) * | 2021-03-08 | 2023-06-20 | 电子科技大学 | Novel isolation unit applied to power gate FPGA structure |
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Address after: 610000 No. two, Jianshe North Road, Chengdu, Sichuan, four Co-patentee after: Chengdu Sino Microelectronics Technology Co., Ltd. Patentee after: University of Electronic Science and Technology of China Address before: 610000 No. two, Jianshe North Road, Chengdu, Sichuan, four Co-patentee before: Chengdu Sino Microelectronics System Co., Ltd. Patentee before: University of Electronic Science and Technology of China |
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Address after: 610000 2006 West Yuan Road, hi-tech West, Chengdu, Sichuan Patentee after: University of Electronic Science and Technology of China Patentee after: Chengdu Hua Microelectronics Technology Co., Ltd; Address before: 610000 No. two, Jianshe North Road, Chengdu, Sichuan, four Patentee before: University of Electronic Science and Technology of China Patentee before: Chengdu Huahua Microelectronics Technology Co., Ltd; |
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