CN109714042A - A kind of multiplexing method of look-up table - Google Patents
A kind of multiplexing method of look-up table Download PDFInfo
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- CN109714042A CN109714042A CN201811368471.2A CN201811368471A CN109714042A CN 109714042 A CN109714042 A CN 109714042A CN 201811368471 A CN201811368471 A CN 201811368471A CN 109714042 A CN109714042 A CN 109714042A
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- lut5
- configuration bit
- lut4
- lut6
- lut3
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Abstract
The invention discloses a kind of multiplexing methods of look-up table, applied to the look-up table LUT6 of 6 input, 2 output, comprising steps of making two LUT5 generate a reusable to LUT5-2 by logic synthesis；And then generate specific configuration bit pair；LUT5-2 is placed on the position LUT6；All input terminals and configuration bit to LUT5-2 to being routed simultaneously.Allow LUT6 to be multiplexed with two LUT5, can more extend to multiplexing two LUT4, LUT3, LUT2 etc.；The resource utilization of LUT6 is improved, better reasonable multiplexed resource copes with the case where smallest number inputs.
Description
Technical field
The present invention relates to PFGA look-up table field more particularly to a kind of multiplexing methods of look-up table.
Background technique
As circuit scale constantly expands, fpga chip scale is also continuously increased module number, simple increase module
Quantity is not well positioned to meet user's design requirement, while having carried out the promotion of LUT look-up table input quantity, mainstream FPGA yet
Manufacturer is generally upgraded to LUT6 from original LUT4, thus can preferably support user's grand designs circuit, but simultaneously
Also some drawbacks are brought.
When LUT inputs negligible amounts, LUT6 will cause the waste of resource, and granularity becomes larger, to small input LUT circuitry
Design there are certain wastings of resources.For better reasonable multiplexed resource, this patent proposes the multiplexing method of LUT6 a kind of,
The case where coping with smallest number input.
Summary of the invention
It is an object of the invention to: it can achieve raising resource utilization by being multiplexed LUT6.
In order to achieve the above objectives, the present invention provides a kind of multiplexing methods of look-up table, applied to looking into for 6 input, 2 output
Look for table LUT6, comprising the following steps:
By logic synthesis, two LUT5 is made to generate a reusable to LUT5-2；And then generate specific configuration bit pair；
LUT5-2 is placed on the position LUT6；
All input terminals and configuration bit to LUT5-2 to being routed simultaneously.
Preferably, LUT5-2 includes the LUT5-B of 1 output of the input of LUT5-A and 5 of 5 inputs 1 output.
It is further preferred that LUT5-A and LUT5-B is there are 4 multiplexing ports, i.e. LUT5-A have 4 input ports and
4 input ports of LUT5-B use identical input signal.
Preferably, two output ports of the configuration bit to corresponding LUT6.
Preferably, configuration bit centering includes two groups of configuration bits, and two LUT5 respectively use wherein one group of configuration bit.
Preferably, further includes: by logic synthesis, two LUT4 is made to generate a reusable to LUT4-2；And then it generates
Specific configuration bit pair；Wherein, configuration bit centering includes two groups of configuration bits, and two LUT4 respectively use wherein one group of configuration bit；
LUT4-2 is placed on the position LUT6；
All input terminals and configuration bit to LUT4-2 to being routed simultaneously.
It is further preferred that LUT4-2 includes the LUT4-B of 1 output of the input of LUT4-A and 4 of 4 inputs 1 output.
It is further preferred that there are at least two multiplexing port, i.e. LUT4-A at least 2 inputs by LUT4-A and LUT4-B
2 input ports of port and LUT5-B use identical input signal.
Preferably, further includes: by logic synthesis, two LUT3 is made to generate a reusable to LUT3-2；And then it generates
Specific configuration bit pair；Wherein, configuration bit centering includes two groups of configuration bits, and two LUT3 respectively use wherein one group of configuration bit；
LUT3-2 is placed on the position LUT6；
All input terminals and configuration bit to LUT3-2 to being routed simultaneously.
Preferably, further includes: by logic synthesis, two LUT2 is made to generate a reusable to LUT2-2；And then it generates
Specific configuration bit pair；Wherein, configuration bit centering includes two groups of configuration bits, and two LUT2 respectively use wherein one group of configuration bit；
LUT2-2 is placed on the position LUT6；
All input terminals and configuration bit to LUT2-2 to being routed simultaneously.
The present invention has the advantages that improving LUT6 resource utilization, LUT6 is allowed to be multiplexed with two LUT5；It more can be with
Extend to multiplexing two LUT4, LUT3, LUT2 etc..Improve the resource utilization of LUT6, better reasonable multiplexed resource, reply
The case where smallest number inputs.
Detailed description of the invention
In order to become apparent from the technical solution for illustrating the embodiment of the present invention, embodiment will be described below in it is required use it is attached
Figure is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this field
For those of ordinary skill, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is that one kind 6 of the embodiment of the present invention inputs the method that look-up table is multiplexed LUT5；
Fig. 2 (a) is that one kind 6 of the embodiment of the present invention inputs the method that look-up table is multiplexed LUT4；
Fig. 2 (b) is that one kind 5 of the embodiment of the present invention inputs the method that look-up table is multiplexed LUT4；
Fig. 3 (a) is that one kind 4 of the embodiment of the present invention inputs the method that look-up table is multiplexed LUT3；
Fig. 3 (b) is that one kind 5 of the embodiment of the present invention inputs the method that look-up table is multiplexed LUT3；
Fig. 3 (c) is that one kind 6 of the embodiment of the present invention inputs the method that look-up table is multiplexed LUT3；
Fig. 4 (a) is that one kind 3 of the embodiment of the present invention inputs the method that look-up table is multiplexed LUT2；
Fig. 4 (b) is that one kind 4 of the embodiment of the present invention inputs the method that look-up table is multiplexed LUT2.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
In a first aspect, one kind 6 inputs the multiplexing method of look-up table, applied to the look-up table LUT6 of 6 input, 2 output, including
Following steps:
By logic synthesis, two LUT5 is made to generate a reusable to LUT5-2；And then generate specific configuration bit pair；
LUT5-2 is placed on the position LUT6；
All input terminals and configuration bit to LUT5-2 to being routed simultaneously.
As shown in Figure 1, LUT5-2 includes the LUT5-B of 1 output of the input of LUT5-A and 5 of 5 inputs 1 output.Wherein LUT5-A
There are separate port I6, LUT5-A and LUT5-B there are 4 multiplexing ports I2, I3, I4 there are separate port I1, LUT5-B and
I5, the i.e. port I2, I3, I4 and I5 use identical input signal.
Two output port O1s and O2 of the configuration bit to corresponding LUT6.
Configuration bit centering includes two groups of configuration bits, and two LUT5 respectively use wherein one group of configuration bit.
Specifically, logic synthesis is to describe the design circuit of user, such as VHDL, Verilog, the languages such as systemC and C
Comprehensive speech is gate level netlist, is then mapped in the modules such as IO, LUT and REG on fpga chip.
Second aspect, a kind of multiplexing method of 6 input look-up table, applied to the look-up table LUT6 of 6 input, 2 output, including
Following steps:
By logic synthesis, two LUT4 is made to generate a reusable to LUT4-2；And then generate specific configuration bit pair；
Wherein, configuration bit centering includes two groups of configuration bits, and two LUT4 respectively use wherein one group of configuration bit；
LUT4-2 is placed on the position LUT6；
All input terminals and configuration bit to LUT4-2 to being routed simultaneously.
LUT4-2 includes the LUT4-B of 1 output of the input of LUT4-A and 4 of 4 inputs 1 output.
As shown in Fig. 2 (a), LUT4-A there are separate port I1, I2, LUT4-B there are separate port I5, I6, LUT4-A and
There are 2 multiplexing ports I3 and I4, the i.e. port I3 and I4 to use identical input signal by LUT4-B.
Two output port O1s and O2 of the configuration bit to corresponding LUT6.
Configuration bit centering includes two groups of configuration bits, and two LUT4 respectively use wherein one group of configuration bit.
As shown in Fig. 2 (b), LUT4-A is there are separate port I1, and there are separate port I5, LUT4-A and LUT4-B by LUT4-B
There are 3 multiplexing ports I2, I3 and I4, i.e. the port I2, I3 and I4 uses identical input signal.
Two output port O1s and O2 of the configuration bit to corresponding LUT6.
Configuration bit centering includes two groups of configuration bits, and two LUT4 respectively use wherein one group of configuration bit.
The third aspect, a kind of multiplexing method of 6 input look-up table, applied to the look-up table LUT6 of 6 input, 2 output, including
Following steps:
By logic synthesis, two LUT3 is made to generate a reusable to LUT3-2；And then generate specific configuration bit pair；
Wherein, configuration bit centering includes two groups of configuration bits, and two LUT3 respectively use wherein one group of configuration bit；
LUT3-2 is placed on the position LUT6；
All input terminals and configuration bit to LUT3-2 to being routed simultaneously.
LUT3-2 includes the LUT3-B of 1 output of the input of LUT3-A and 3 of 3 inputs 1 output.
As shown in Fig. 3 (a), LUT3-A is there are separate port I1, and there are separate port I4, LUT3-A and LUT3-B by LUT3-B
There are 2 multiplexing ports I2 and I3, i.e. the port I2 and I3 uses identical input signal.
Two output port O1s and O2 of the configuration bit to corresponding LUT6.
Configuration bit centering includes two groups of configuration bits, and two LUT3 respectively use wherein one group of configuration bit.
As shown in Fig. 3 (b), LUT3-A is there are separate port I1 and I2, and there are separate port I4 and I5, LUT3-A by LUT3-B
With LUT3-B there are 1 multiplexing port I2, i.e. the port I2 uses identical input signal.
Two output port O1s and O2 of the configuration bit to corresponding LUT6.
Configuration bit centering includes two groups of configuration bits, and two LUT3 respectively use wherein one group of configuration bit.
As shown in Fig. 3 (c), LUT3-A is there are separate port I1, I2 and I3, and there are separate port I4, I5 and I6 by LUT3-B.
Two output port O1s and O2 of the configuration bit to corresponding LUT6.
Configuration bit centering includes two groups of configuration bits, and two LUT3 respectively use wherein one group of configuration bit.
Fourth aspect, a kind of multiplexing method of 6 input look-up table, applied to the look-up table LUT6 of 6 input, 2 output, including
Following steps:
By logic synthesis, two LUT2 is made to generate a reusable to LUT2-2；And then generate specific configuration bit pair；
Wherein, configuration bit centering includes two groups of configuration bits, and two LUT2 respectively use wherein one group of configuration bit；
LUT2-2 is placed on the position LUT6；
All input terminals and configuration bit to LUT2-2 to being routed simultaneously
As shown in Fig. 4 (a), LUT2-A is there are separate port I1, and there are separate port I3, LUT3-A and LUT3-B by LUT3-B
There are 1 multiplexing port I2, i.e. the port I2 uses identical input signal.
Two output port O1s and O2 of the configuration bit to corresponding LUT6.
Configuration bit centering includes two groups of configuration bits, and two LUT2 respectively use wherein one group of configuration bit.
As shown in Fig. 4 (b), LUT3-A is there are separate port I1 and I2, and there are separate port I3 and I4 by LUT3-B.
Two output port O1s and O2 of the configuration bit to corresponding LUT6.
Configuration bit centering includes two groups of configuration bits, and two LUT2 respectively use wherein one group of configuration bit.
The present invention provides a kind of multiplexing methods of look-up table, improve LUT6 resource utilization, LUT6 is multiplexed
For two LUT5；Multiplexing two LUT4, LUT3, LUT2 etc. can more be extended to.The resource utilization of LUT6 is improved, preferably
The case where reasonable multiplexed resource, reply smallest number input.
Above specific embodiment has carried out further in detail the purpose of the present invention, technical scheme and beneficial effects
Illustrate, it should be understood that the above is only a specific embodiment of the invention, the protection model that is not intended to limit the present invention
It encloses, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should be included in the present invention
Protection scope within.
Claims (10)
1. a kind of multiplexing method of look-up table, the look-up table LUT6 applied to 6 input, 2 output, which is characterized in that including following step
It is rapid:
By logic synthesis, two LUT5 is made to generate a reusable to LUT5-2；And then generate specific configuration bit pair；
The LUT5-2 is placed on the position LUT6；
All input terminals and configuration bit to LUT5-2 to being routed simultaneously.
2. the method according to claim 1, wherein the LUT5-2 includes the LUT5-A and 5 of 5 inputs 1 output
The LUT5-B of 1 output of input.
3. according to the method described in claim 2, it is characterized in that, the LUT5-A and LUT5-B there are 4 multiplexing ports, i.e.,
LUT5-A has 4 input ports of 4 input ports and LUT5-B to use identical input signal.
4. the method according to claim 1, wherein two output ports of the configuration bit to corresponding LUT6.
5. the method according to claim 1, wherein the configuration bit centering include two groups of configuration bits, described two
A LUT5 respectively uses wherein one group of configuration bit.
6. the method according to claim 1, wherein further include:
By logic synthesis, two LUT4 is made to generate a reusable to LUT4-2；And then generate specific configuration bit pair；Its
In, the configuration bit centering includes two groups of configuration bits, and described two LUT4 respectively use wherein one group of configuration bit；
The LUT4-2 is placed on the position LUT6；
All input terminals and configuration bit to LUT4-2 to being routed simultaneously.
7. according to the method described in claim 6, it is characterized in that, the LUT4-2 includes the LUT4-A and 4 of 4 inputs 1 output
The LUT4-B of 1 output of input.
8. the method according to the description of claim 7 is characterized in that there are at least two to be multiplexed end by the LUT4-A and LUT4-B
Mouthful, i.e. 2 input ports of LUT4-A at least 2 input ports and LUT5-B use identical input signal.
9. the method according to claim 1, wherein further include:
By logic synthesis, two LUT3 is made to generate a reusable to LUT3-2；And then generate specific configuration bit pair；Its
In, the configuration bit centering includes two groups of configuration bits, and described two LUT3 respectively use wherein one group of configuration bit；
The LUT3-2 is placed on the position LUT6；
All input terminals and configuration bit to LUT3-2 to being routed simultaneously.
10. the method according to claim 1, wherein further include:
By logic synthesis, two LUT2 is made to generate a reusable to LUT2-2；And then generate specific configuration bit pair；Its
In, the configuration bit centering includes two groups of configuration bits, and described two LUT2 respectively use wherein one group of configuration bit；
The LUT2-2 is placed on the position LUT6；
All input terminals and configuration bit to LUT2-2 to being routed simultaneously.
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| CN201811368471.2A CN109714042A (en) | 2018-11-16 | 2018-11-16 | A kind of multiplexing method of look-up table |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113904677A (en) * | 2021-10-11 | 2022-01-07 | 北京汤谷软件技术有限公司 | Look-up table circuit capable of customizing multiple inputs and novel array structure of FPGA |
| CN116894413A (en) * | 2023-09-05 | 2023-10-17 | 苏州异格技术有限公司 | Logic mapping method, device, equipment and storage medium based on hardware |
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| CN101969306A (en) * | 2010-09-07 | 2011-02-09 | 复旦大学 | FPGA (Field Programmable Gate Array) configurable five-input lookup table structure |
| CN102176673A (en) * | 2011-02-25 | 2011-09-07 | 中国科学院半导体研究所 | LUT4 (look up table), logical unit of FPGA (field programmed gate array) and logical block of FPGA |
| CN105958996A (en) * | 2016-05-18 | 2016-09-21 | 中国电子科技集团公司第五十八研究所 | Non-full-coverage eight-input lookup table (LUT) structure |
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| JPH09181598A (en) * | 1995-12-18 | 1997-07-11 | At & T Corp | Field programmable gate array |
| US7194723B1 (en) * | 2003-10-27 | 2007-03-20 | Altera Corporation | Techniques for mapping functions to lookup tables on programmable circuits |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113904677A (en) * | 2021-10-11 | 2022-01-07 | 北京汤谷软件技术有限公司 | Look-up table circuit capable of customizing multiple inputs and novel array structure of FPGA |
| CN113904677B (en) * | 2021-10-11 | 2022-07-01 | 北京汤谷软件技术有限公司 | Look-up table circuit capable of customizing multiple inputs and novel array structure of FPGA |
| CN116894413A (en) * | 2023-09-05 | 2023-10-17 | 苏州异格技术有限公司 | Logic mapping method, device, equipment and storage medium based on hardware |
| CN116894413B (en) * | 2023-09-05 | 2023-12-05 | 苏州异格技术有限公司 | Logic mapping method, device, equipment and storage medium based on hardware |
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