CN107112996B - Lookup table process mapping method based on FPGA and lookup table - Google Patents
Lookup table process mapping method based on FPGA and lookup table Download PDFInfo
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
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Abstract
The invention relates to a lookup table process mapping method based on an FPGA and a lookup table, wherein the method comprises the following steps: determining a first number N1 of first input signals of the first look-up table and determining a second number N2 of second input signals of the second look-up table; determining the number K of input signals of the same type in the first input signal and the second input signal; and if N1+ N2-K is less than or equal to M, combining the first lookup table and the second lookup table to generate a third lookup table, wherein the third lookup table has a third number of input ports, first output ports and second output ports. The lookup table process mapping method based on the FPGA and the lookup table provided by the invention can save logic resources of an FPGA chip, improve the maximum frequency of the FPGA chip, reduce the power of the FPGA chip, reduce the area of the FPGA chip and optimize the layout of the FPGA chip.
Description
Technical Field
The invention relates to the technical field of integrated circuit design in the field of microelectronics, in particular to a lookup table process mapping method based on an FPGA and a lookup table.
Background
A Field-Programmable Gate Array (FPGA) is a logic device with rich hardware resources, powerful parallel processing capability, and flexible reconfigurable capability. Look-Up tables (LUTs) are the basic logic units on an FPGA chip.
Process Mapping (Technology Mapping), which is an important step in the design process of digital systems, maps process-independent structural descriptions to process-dependent physical realizations, enabling the synthesis results of various levels of integrated system abstractions to be converted into a concrete process realization.
With the update of FPGA hardware, the number of input ports of basic LUTs in the FPGA is increased from 4 to 6, which greatly expands the capacity of the lookup tables, but the increase of the number of the lookup tables which are insufficiently utilized after process mapping is accompanied, a large number of the lookup tables which are insufficiently utilized waste FPGA logic resources, the maximum frequency, power and layout of an FPGA chip are influenced, and the area of the FPGA chip is increased. How to use LUTs maximally and reduce the number of LUTs in the process mapping process is an urgent problem to be solved.
Disclosure of Invention
The invention overcomes the defects of the prior art and provides a lookup table process mapping method based on an FPGA and a lookup table.
In a first aspect, the present invention provides a lookup table process mapping method based on an FPGA, which includes the following steps:
determining a first number N1 of first input signals of the first look-up table and determining a second number N2 of second input signals of the second look-up table; determining the number K of input signals of the same type in the first input signal and the second input signal; and if N1+ N2-K is less than or equal to M, combining the first lookup table and the second lookup table to generate a third lookup table, wherein the third lookup table has a third number of input ports, first output ports and second output ports.
Preferably, the number of input ports of the first lookup table and the second lookup table is the same, the number of output ports is 1, and the value of M is determined according to the number of input ports of the first lookup table and the second lookup table.
Preferably, the first number is the same as the second number, the number of input signals of the third lookup table is the same as the first number and the second number, the first output port outputs the output signal of the first lookup table, and the second output port outputs the output signal of the second lookup table.
Preferably, the sum of the first number and the second number is equal to the number of input signals of the third lookup table, the first output port outputs the output signal of the first lookup table, and the second output port outputs the output signal of the second lookup table.
Preferably, the second number is 0, the first number is the same as the number of input signals of the third lookup table, the first output port outputs an output signal of the first lookup table, and the second output port outputs a power supply signal, including: VCC and GND.
In a second aspect, the present invention provides an FPGA-based lookup table, which is obtained by combining two lookup tables having a plurality of input ports and one output port according to the method provided in the first aspect, and which has a plurality of input ports and two output ports.
Preferably, the FPGA-based lookup table has a plurality of operating modes, one operating mode is as a multi-input two-output lookup table, and the other operating mode is as a multi-input single-output lookup table.
The lookup table process mapping method based on the FPGA and the lookup table provided by the invention can reduce the use number of the lookup tables in the FPGA chip, and can make the lookup tables fully used, thereby saving the logic resource of the FPGA chip, improving the maximum frequency of the FPGA chip, reducing the power of the FPGA chip, reducing the area of the FPGA chip and optimizing the layout of the FPGA chip.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a programmable logic module in a C1 architecture according to an embodiment of the present invention;
FIG. 2 is a flowchart of a lookup table process mapping method based on FPGA according to an embodiment of the present invention;
FIG. 3 is a block diagram of an embodiment 1 for obtaining a lookup table according to the method of the present invention;
FIG. 4 is a block diagram of an embodiment 2 of obtaining a lookup table according to the method of the present invention;
FIG. 5 shows an embodiment 3 of obtaining a lookup table according to the method of the present invention;
FIG. 6 is a block diagram of an embodiment 4 of obtaining a lookup table according to the method of the present invention;
fig. 7 is a schematic structural diagram of a lookup table based on an FPGA according to an embodiment of the present invention.
Detailed Description
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
The method in the following embodiment of the invention is realized based on the first chip C1 of the cluster series in the FPGA chip. Fig. 1 is a schematic structural diagram of a programmable logic module in the C1 architecture according to an embodiment of the present invention. C1 is the first chip of the cloud series in the FPGA chip, mainly used in the high-speed communication field. As shown in fig. 1, in the structure of PLB (Programmable Logic Block), the lookup table 01 is a lookup table generated according to the method provided by the present invention. In the prior art, the lookup table is 6 input 1 output, and if two data outputs shown in fig. 1 are to be completed, two lookup tables with 6 input 1 output are needed to realize the logic function of the PLB, so that the logic resources of the FPGA chip and the maximum frequency of the FPGA chip are wasted, and the difficulty is increased for the layout of the FPGA chip. The method provided by the invention can combine the two multi-input 1-output lookup tables meeting the condition into one multi-input 2-output lookup table, thereby overcoming the defects of the prior art.
Fig. 2 is a flowchart of a lookup table process mapping method based on an FPGA according to an embodiment of the present invention, and as shown in fig. 2, the lookup table process mapping method based on the FPGA specifically includes the following steps:
step S101, determining a first number N1 of first input signals of a first look-up table and determining a second number N2 of second input signals of a second look-up table;
step S102, determining the number K of input signals of the same type in the first input signal and the second input signal;
and S103, if the N1+ N2-K is less than or equal to M, merging the first lookup table and the second lookup table to generate a third lookup table, wherein the third lookup table has a third number of input ports, first output ports and second output ports.
The first lookup table and the second lookup table mentioned in the above method are lookup tables of the same type, that is, the number of input ports is the same, and the size of the M value is determined according to the first lookup table and the second lookup table.
In order to more clearly describe the method provided by the embodiment of the present invention, how to apply the method to merge the lookup tables is described by several embodiments.
Example 1:
fig. 3 shows an embodiment 1 for obtaining the lookup table according to the method provided by the present invention, as shown in fig. 3, both LUT1 and LUT2 are 6-input 1-output lookup tables, and both LUT1 and LUT2 have 5 input signals and 1 output signal, and according to the method of the present invention, M is determined to be 5, and it can be known that N1 is 5, N2 is 5, K is 5, N1+ N2-K ≦ M, and it can be known that LUT1 and LUT2 meet the merging requirement, and LUT1 and LUT2 are merged to obtain LUT3, and LUT3 is a 5-input 2-output lookup table. After combination, the two output ports of LUT3 can output the output signals of original LUT1 and original LUT2 by compiling the mask value of LUT 3.
Example 2:
fig. 4 shows embodiment 2 for obtaining the look-up table according to the method provided by the present invention, as shown in fig. 4, both LUT1 and LUT2 are 6-input 1-output look-up tables, but LUT1 uses only three inputs after process mapping, and LUT2 uses 2 inputs, which wastes logic resources. According to the method, M is determined to be 5, N1 is known to be 3, N2 is known to be 2, K is known to be 0, N1+ N2-K is not more than M, LUT1 and LUT2 meet the combination requirement, LUT1 and LUT2 are combined to obtain LUT3, and LUT3 is a 5-input-2-output lookup table. After combination, the two output ports of LUT3 can output the output signals of original LUT1 and original LUT2 by compiling the mask value of LUT 3.
Example (b): 3:
fig. 5 shows embodiment 3 for obtaining the look-up table according to the method provided by the present invention, as shown in fig. 5, both LUT1 and LUT2 are 6-input 1-output look-up tables, but LUT1 uses only three inputs after process mapping, and LUT2 uses 2 inputs, which wastes logic resources. According to the method, M is determined to be 5, N1 is known to be 3, N2 is known to be 2, K is 1, N1+ N2-K is not more than M, LUT1 and LUT2 meet the combination requirement, LUT1 and LUT2 are combined to obtain LUT3, and LUT3 is a 4-input-2-output lookup table. After combination, the two output ports of LUT3 can output the output signals of original LUT1 and original LUT2 by compiling the mask value of LUT 3.
Example 4:
fig. 6 shows an embodiment 4 for obtaining the look-up table according to the method of the present invention, as shown in fig. 6, a special look-up table LUT3 can be obtained according to the method of the present invention, the look-up table LUT3 has two output ports, one output port meets the use requirement of the LUT1 in the figure and outputs OUT1, and the other port is used for outputting active signals, including VCC (power supply voltage) and GND (ground of wire). It should be noted that the number of input signals of the LUT3 is not limited to 5.
Fig. 7 is a schematic structural diagram of a lookup table based on an FPGA according to an embodiment of the present invention, as shown in fig. 7, the LUT includes: 5 input 1 output LUT5-0, 5 input 1 output LUT5-1, gate a, and gate B, and the LUT has two modes of operation.
Working mode 1:
the LUT is used as a multi-input 2-output lookup table, the input port f5 is not used, the gate A is used for gating a terminal 0, and the gate B is used for gating a terminal 0, so that the LUT outputs the output signal x [0] of the LUT5-0 from a terminal x, and the output signal x [1] of the LUT5-1 from a terminal x. Specifically, the operating state of operating mode 1 is achieved by compiling mask values for LUT5-0 and LUT 5-1.
The LUT in the working mode can output two signals, not only meets the output signal requirement of two multi-input single-output lookup tables before combination, but also reduces the using number of the lookup tables, so that the lookup tables are fully utilized, the waste of FPGA logic resources is reduced, the maximum frequency of an FPGA chip is improved, the power of the FPGA chip is reduced, the area of the FPGA chip is reduced, and the layout of the FPGA chip is optimized.
Specifically, when the LUT is used as a multi-input 2-output look-up table, one output port can output active signals including VCC (power supply voltage) and GND (ground of the wire).
The LUT in the working mode can meet certain logic requirements of the FPGA chip and provide an optimized space for the wiring of the FPGA chip.
The working mode 2 is as follows:
the LUT is used as a 6 input 1 output look-up table. At this time, input signals are inputted from the input ports f5-f0, the LUT5-0 outputs x [0] according to the input signals, the LUT5-1 outputs x [1] according to the input signals, the 1 terminal is gated by the gate A at this time, and the input signal of the f5 port finally controls the gate B to output x [0] or x [1] as LUT output signals from the xy port. Specifically, the operating state of operating mode 1 is achieved by compiling mask values for LUT5-0 and LUT 5-1.
The LUT in this operation mode is used as a general lookup table, so that the LUT provided by this embodiment can be used in a wider range.
It should be further noted that, in the LUT provided in this embodiment, during the use process, only the LUT needs to be configured to operate in different operation modes, there is no limitation on the type of the input signal of the input port of the LUT, and the LUT does not need to implement the different operation modes of the LUT through controlling the input signal of the input port.
The FPGA-based lookup table process mapping method and the lookup table provided by the embodiment of the invention are embodiments based on a chip architecture based on C1, but the technical scheme of the invention is not limited to a C1 chip architecture, and the combined lookup table is not limited to a 6-input 1-output lookup table, and the embodiment provided by the invention is only for more vividly describing the technical scheme of the invention, and is not limited to the technical scheme of the invention.
Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, a software module executed by a processor, or a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (4)
1. A lookup table process mapping method based on FPGA is characterized by comprising the following steps:
determining a first number N1 of first input signals of the first look-up table and determining a second number N2 of second input signals of the second look-up table;
determining the number K of input signals of the same type in the first input signal and the second input signal;
if N1+ N2-K is less than or equal to M, N1 is greater than 0, and N2 is greater than 0, merging the first lookup table and the second lookup table to generate a third lookup table with M inputs and two outputs, wherein the third lookup table has a third number of input ports, a first output port and a second output port; causing the first output port to output an output signal of the first lookup table and the second output port to output an output signal of the second lookup table by compiling a mask value of the third lookup table;
if M is greater than or equal to N1 > 0 and N2 is equal to 0, the first number is the same as the number of input signals of the third lookup table, the first output port outputs an output signal of the first lookup table, and the second output port outputs a power signal, including: VCC and GND.
2. The method of claim 1, wherein the first lookup table and the second lookup table have the same number of input ports and 1 number of output ports, and wherein the value of M is determined according to the number of input ports of the first lookup table and the second lookup table.
3. The method of claim 1, wherein the first number is the same as the second number, wherein the third lookup table has the same number of input signals as the first number and the second number, wherein the first output port outputs the output signals of the first lookup table, and wherein the second output port outputs the output signals of the second lookup table.
4. The method of claim 1, wherein a sum of the first number and the second number is equal to a number of input signals to the third lookup table.
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| Application Number | Priority Date | Filing Date | Title |
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| PCT/CN2015/095216 WO2017084104A1 (en) | 2015-11-20 | 2015-11-20 | Fpga-based look-up table technology mapping method and look-up table |
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| CN107112996B true CN107112996B (en) | 2021-06-18 |
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| US11144286B2 (en) | 2019-01-14 | 2021-10-12 | Microsoft Technology Licensing, Llc | Generating synchronous digital circuits from source code constructs that map to circuit implementations |
| US11106437B2 (en) * | 2019-01-14 | 2021-08-31 | Microsoft Technology Licensing, Llc | Lookup table optimization for programming languages that target synchronous digital circuits |
| US10810343B2 (en) | 2019-01-14 | 2020-10-20 | Microsoft Technology Licensing, Llc | Mapping software constructs to synchronous digital circuits that do not deadlock |
| US11113176B2 (en) | 2019-01-14 | 2021-09-07 | Microsoft Technology Licensing, Llc | Generating a debugging network for a synchronous digital circuit during compilation of program source code |
| US11093682B2 (en) | 2019-01-14 | 2021-08-17 | Microsoft Technology Licensing, Llc | Language and compiler that generate synchronous digital circuits that maintain thread execution order |
| US11275568B2 (en) | 2019-01-14 | 2022-03-15 | Microsoft Technology Licensing, Llc | Generating a synchronous digital circuit from a source code construct defining a function call |
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| US7350176B1 (en) * | 2003-07-17 | 2008-03-25 | Altera Corporation | Techniques for mapping to a shared lookup table mask |
| CN101656535A (en) * | 2008-08-20 | 2010-02-24 | 中国科学院半导体研究所 | Process mapping method for programmable gate array of multi-mode logical unit |
| US20120319752A1 (en) * | 2011-06-17 | 2012-12-20 | Telefonaktiebolaget Lm Ericsson(Publ) | Look-up tables for delay circuitry in field programmable gate array (fpga) chipsets |
| FR2987959B1 (en) * | 2012-03-06 | 2014-03-14 | Soitec Silicon On Insulator | MULTIPLEXER, CORRESPONDENCE TABLE AND FGPA |
| CN103762974B (en) * | 2014-01-26 | 2016-09-14 | 无锡中微亿芯有限公司 | Multi-functional configurable six input look-up table configuration |
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