CN101656535A - Process mapping method for programmable gate array of multi-mode logical unit - Google Patents
Process mapping method for programmable gate array of multi-mode logical unit Download PDFInfo
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Abstract
The invention discloses a process mapping method for a programmable gate array of a multi-mode logical unit. The method comprises two steps of mapping and combining, wherein an input gate level circuit netlist independent of particular process is resolved, and a resolved result is subjected to process mapping; then, the process mapping results are combined and processed according to restriction information of multi-mode LC to calculate mode configuration values of the multi-mode LC so as to acquire the finally optimized circuit netlist related to the process. The method solves the process mapping problem of the multi-mode logical unit structure FPGA, and sufficiently utilizes the advantage based on two LC structures of LUT3.
Description
Technical field
The present invention relates to integrated circuit and programmable gate array (Field Programmable GateArray is hereinafter to be referred as FPGA) chip design art field, be specifically related to the fpga logic cellular construction, and a kind of process mapping method at the multi-mode logical unit programmable gate array of fpga chip design automation aspect.
Background technology
Programmable logical block (Logic Cell, LC) array is an elementary cell of forming field programmable gate array (FPGA) chip, technology mapping (Technology Mapping) is the important bridge that connects the comprehensive and rear end placement-and-routing of front end logic in the FPGA design cycle, in this stage, the circuit meshwork list irrelevant with technology is mapped to the relevant structure of technology library under certain hardware constraints, the performance of fpga chip depends on the structure and the corresponding process mapping method thereof of logical block to a great extent.
LUT4 (4-input Look-up Table) in a kind of novel multi-mode LC structure also is based on two LUT3 and forms, characteristics with oneself, as shown in Figure 1, except a d type flip flop, two LUT3 and one are used for two LUT3 are combined into outside the MUX (MUX) of a LUT4, also have three model selection MUX with special effect, with its called after Fmux respectively, Cmux and Smux, the selection input of these three MUX are respectively by 1 programmable memory cell decision.Obviously, this LC structure can be configured to 2
3=8 kinds of patterns by a large amount of circuit analyses is drawn, are mainly contained four kinds of patterns what the actual FPGA design can use in a large number, and as shown in table 1, table 1 is four kinds of the most frequently used multi-mode LC configuration modes.
| Schema category | The Smux selecting side | The Cmux selecting side | The Fmux selecting side |
| Pattern one | ????0 | ????0 | ????1 |
| Pattern two | ????0 | ????1 | ????0 |
| Pattern three | ????0 | ????0 | ????0 |
| Pattern four | ????1 | ????0 | ????0 |
Table 1
When LC is operated in pattern once the time, circuit equivalent is a common LUT4, can realize the Boolean logics of any 4 inputs; Pattern two also can be called carry chain (carry-chain) pattern, at this moment, input CI replaces input I2 and enters two LUT3, input I3 does not enter LUT3, C-LUT3 and S-LUT3 export by CO and O respectively, the CO output carry, and the CI that is connected to next LC holds, O exports current results, the full adder logic that such LC just can be achieved as follows:
Saved the area of half approximately; The pattern three condition is more special, is to be applied to add entirely in the logic, during two addend lowest order additions, does not have carry C this moment
iSo, will not import CI and link to each other with LUT3; Four times most important purposes of pattern are to realize multiplier logic, and under this state, two LUT3 can be by XB and XO simultaneously with I0﹠amp; I1, I2﹠amp; The result of I3 output, a LC can obtain two partial products simultaneously, and then and pattern two under the LC combination, partial product is added up, draw final multiplication result.
Optimization method is shone upon to FPGA technology in academia both at home and abroad at present, concentrate on mostly general Boolean logic circuit meshwork list is mapped as the circuit of being made up of K input LUT, the input number of concrete LUT is by the technology library decision of reality, but these methods only are aimed at the structure that comprises a LUT simple among the LC, so just can't make full use of the advantage based on the LC structure of two LUT3.
Summary of the invention
(1) technical problem that will solve
In view of this, main purpose of the present invention is to provide a kind of process mapping method at the multi-mode logical unit programmable gate array, to solve the technology mapping problems of multi-mode logical unit structure FPGA, make full use of advantage based on the LC structure of two LUT3.
(2) technical scheme
For reaching above-mentioned order, the technical solution used in the present invention is such:
A kind of process mapping method at the multi-mode logical unit programmable gate array, this method comprises mapping and merges two steps, resolving at first to input with the irrelevant gate level circuit net table of concrete technology, and the result who resolves carried out the technology mapping, and then the technology mapping result is merged processing according to the constraint information of multi-mode LC, calculate the pattern configurations value of multi-mode LC, obtain the relevant circuit meshwork list of technology of final optimization pass.
In the such scheme, described result to parsing carries out adopting preferential partitioning algorithm in the technology mapping steps, and the irrelevant net of realization logic is shown the mapping of LUT net table.
In the such scheme, described preferential partitioning algorithm avoid exhaustive all cut apart, only each node is calculated cutting apart of fixed number, cut apart the cutting apart to be called preferentially of this fixed number.
In the such scheme, in described preferential partitioning algorithm, to cutting apart the target that the standard of carrying out priority calculating depends on mapping, for depth-first mapping, the degree of depth of cutting apart is as first standard, the situation that the degree of depth is identical, the input number of cutting apart is as second standard, and area is as last standard.
In the such scheme, described constraint information according to multi-mode LC merges in the step of processing the technology mapping result, is based on maximum radix coupling LUT net table is merged optimization, specifically comprises:
Figure G can by one two tuple G (V, E) expression, the nodal set in the V representative graph wherein, E represent the line collection between the node, represents the relation between node and the node; The circuit meshwork list that merges before handling may comprise n the LUT unit smaller or equal to 3 inputs, the node v of figure G each all can be thought in these LUT unit
i({ 1,2,3...... n}), calculates per two LUT in all these LUT unit to i ∈ then
i, LUT
j(i, j ∈ 1,2, and 3......, input intersection number K (K=faninLUTi ∪ faninLUTj) n}), the time complexity of this process is O (n
2), when the K value is less than or equal to 4, the some v of these two LUT representatives
i, v
jJust be considered to abutment points each other, and these points are made marks, have a limit e between them
Ij, last, with among the figure G not with any node each other the node of abutment points cast out, just obtain a new simple graph G '; If (V E) is simple graph to G, the limit collection
If any two limits adjacency not among the M, claim that then M is coupling among the G, wherein with M in the node of frontier juncture connection be called saturation point, otherwise become unsaturated point, if M is the coupling of G, and do not exist other coupling M ' to make | M|＜| M ' |, claim that then M is the maximum radix coupling of G, is also referred to as maximum coupling; Can reduce a maximum radix coupling M who asks figure G ' towards area-optimized LUT merging process like this, the LUT of two node representatives that every limit e among the M is connected can merge among the same LC.
In the such scheme, after the described maximum of obtaining side circuit isoboles G ' is mated M, further comprise: according to the maximum coupling M of the side circuit isoboles G ' that obtains, and the constraint of multi-mode LC library unit information, two relevant LUT are integrated with a LC, and the more LUT of acquiescence input number is mapped to C-LUT3.
In the such scheme, this method is that circuit meshwork list is converted into a figure, and maximum radix matching algorithm is applied to the merging of LUT, and the pattern configurations value of the LC after being combined is at last calculated.
In the such scheme, described merging specifically comprises: according to a pair of relevant LUT input intersection K (2≤K≤4), input union S (S=faninLUTi ∩ faninLUTj, 0≤S≤3) number, different one of the actual input number of S-LUT3 and the actual input number of C-LUT3 co-exists in 12 kinds of match condition, judge by these 12 kinds of situations during merging, calculate the Configuration Values of memory cell and three model selection MUX among the LC make new advances respectively.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, this process mapping method provided by the invention at the multi-mode logical unit programmable gate array, by mapping with merge two steps, i.e. resolving at first to input with the irrelevant gate level circuit net table of concrete technology, and the result who resolves carried out the technology mapping, and then the technology mapping result is merged processing according to the constraint information of multi-mode LC, calculate the pattern configurations value of multi-mode LC, obtain the relevant circuit meshwork list of technology of final optimization pass, solved the technology mapping problems of multi-mode logical unit structure FPGA, made full use of advantage based on the LC structure of two LUT3.
2, this process mapping method at the multi-mode logical unit programmable gate array provided by the invention can utilize computer program to finish easily the technology of the uncorrelated circuit meshwork list of technology in the FPGA design is shone upon and optimization.
3, this process mapping method at the multi-mode logical unit programmable gate array provided by the invention, the technology that can utilize computer program to finish in the FPGA design cycle is shone upon, and realizes electric design automation, has improved design efficiency.
Description of drawings
Fig. 1 is the structural representation of multi-mode logical unit;
Fig. 2 is the software approach flow chart of technology mapping;
Fig. 3 is that a LUT3 initial configuration value is adjusted example schematic.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
Below in conjunction with the accompanying drawing table software approach among the present invention is done concrete detailed description.Mainly comprise two parts: general technology mapping method and merging method.Input is and the irrelevant gate level circuit net table (Verilog HDL form) of concrete technology.
Step 1: input file is through carrying out general technology mapping earlier after resolving, this step has mainly been adopted a kind of (priority cut) algorithm of preferentially cutting apart, and the irrelevant net of realization logic is shown the mapping of LUT net table.Great majority are enumerated (Cut Enumeration) based on cutting apart algorithms need calculate each node all cut apart, the network of a n node to cut a number be O (n
K), computation complexity is very high.The prioritycut algorithm avoided exhaustive all cut apart, only each node is calculated cutting apart of fixed number (normally 5-10).These are retained cuts apart to be called preferentially and cuts apart.Carry out the target that standard that priority calculates depends on mapping to cutting apart, for example, for the depth-first mapping, the degree of depth of cutting apart is as first standard, the situation that the degree of depth is identical, and the input number of cutting apart is as second standard, and area is as last standard.Experiment shows the test circuit for 95%, and priority cut algorithm can access minimum-depth, even only keep a situation about preferentially cutting apart at each node, also can obtain result preferably.Therefore with respect to the method for exhaustion, priority cut algorithm has greatly improved computational speed and has reduced calculator memory consumption on the basis of minimising loss performance.
Step 2: LUT net table is merged optimization based on maximum radix coupling.Figure G can by one two tuple G (V, E) expression, the nodal set in the V representative graph wherein, E represent the line collection between the node, represents the relation between node and the node.The circuit meshwork list that merges before handling may comprise n the LUT unit smaller or equal to 3 inputs, the node v of figure G each all can be thought in these LUT unit
i({ 1,2,3...... n}), calculates per two LUT in all these LUT unit to i ∈ then
i, LUT
j(i, j ∈ 1,2, and 3......, input intersection number K (K=faninLUTi ∪ faninLUTj) n}), the time complexity of this process is O (n
2), when the K value is less than or equal to 4, the some v of these two LUT representatives
i, v
jJust be considered to abutment points each other, and these points are made marks, have a limit e between them
Ij, last, with among the figure G not with any node each other the node of abutment points cast out, just obtain a new simple graph G '.See a definition below:
G is established in definition, and (V E) is simple graph, the limit collection
If any two limits adjacency not among the M, claim that then M is coupling among the G, wherein with M in the node of frontier juncture connection be called saturation point, otherwise become unsaturated point,, and do not exist other coupling M ' to make if M is the coupling of G | M|＜| M ' |, claim that then M is the maximum radix coupling (maximum cardinalitymatching) of G, is also referred to as maximum coupling.
Can reduce a maximum radix coupling M who asks figure G ' towards area-optimized LUT merging process like this, the LUT of two node representatives that every limit e among the M is connected can merge among the same LC.
Step 3: after obtaining the maximum coupling M of side circuit isoboles G ', the constraint according to result and multi-mode LC library unit information begins two relevant LUT are integrated with a LC, and the more LUT of acquiescence input number is mapped to C-LUT3.As shown in Figure 1, LUT3 input is not arbitrarily with being connected between LC imports, to LUT to considering concrete annexation when merging, need to adjust the relative order and the absolute position of original LUT fan-in under the necessary situation, and adjust the initial configuration value of LUT.By analysis, according to a pair of relevant LUT input intersection K (2≤K≤4), input union S (S=faninLUTi ∩ faninLUTj, 0≤S≤3) number, different one of the actual input number of S-LUT3 and the actual input number of C-LUT3 co-exists in 12 kinds of match condition, and be as shown in table 2, and table 2 is match condition classification, judge by these 12 kinds of situations during merging, calculate the Configuration Values of memory cell and three model selection MUX among the LC make new advances respectively.
| The match condition classification | Input intersection K | Input union S | The actual input of S-LUT3 number | The actual input of C-LUT3 number |
| ????1 | ????4 | ????2 | ????3 | ????3 |
| ????2 | ????4 | ????1 | ????2 | ????3 |
| ????3 | ????4 | ????0 | ????2 | ????2 |
| ????4 | ????4 | ????0 | ????1 | ????3 |
| ????5 | ????3 | ????3 | ????3 | ????3 |
| ????6 | ????3 | ????2 | ????2 | ????3 |
| ????7 | ????3 | ????1 | ????1 | ????3 |
| ????8 | ????3 | ????1 | ????2 | ????2 |
| ????9 | ????3 | ????0 | ????1 | ????2 |
| ????10 | ????2 | ????2 | ????2 | ????2 |
| ????11 | ????2 | ????1 | ????1 | ????2 |
| ????12 | ????2 | ????0 | ????1 | ????1 |
Table 2
With match condition in the table 21 is example, in this case, draws according to the annexation of reality, two input pins sharing can only be placed on A and the C input port of two LUT3, model selection this moment Port Multiplier Smux, Cmux, the Configuration Values of Fmux is respectively 1,0, and 0.And the fan-in of original LUT3 order may need to readjust, and shares with A, the C end input of guaranteeing two LUT3, and the adjustment of LUT fan-in order directly has influence on the setting of LUT initial configuration value, therefore need recomputate LUT initial configuration value.8 memory cell are arranged among the LUT3, its initial configuration value can be shown by 2 16 system numerical tables, after Fig. 3 has showed that a LUT3 fan-in position is adjusted, Configuration Values is adjusted accordingly, In0 and In1 are the shared input of two LUT3, suppose to adjust that Configuration Values is 0x0F before the fan-in order, so In0, In1 are adjusted to A, C end after, recomputating and drawing the LUT3 Configuration Values is 0x33.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1, a kind of process mapping method at the multi-mode logical unit programmable gate array, it is characterized in that, this method comprises mapping and merges two steps, resolving at first to input with the irrelevant gate level circuit net table of concrete technology, and the result who resolves carried out the technology mapping, and then the technology mapping result is merged processing according to the constraint information of multi-mode LC, and calculate the pattern configurations value of multi-mode LC, obtain the relevant circuit meshwork list of technology of final optimization pass.
2, the process mapping method at the multi-mode logical unit programmable gate array according to claim 1, it is characterized in that, described result to parsing carries out adopting preferential partitioning algorithm in the technology mapping steps, and the irrelevant net of realization logic is shown the mapping of LUT net table.
3, the process mapping method at the multi-mode logical unit programmable gate array according to claim 2, it is characterized in that, described preferential partitioning algorithm avoid exhaustive all cut apart, only each node is calculated cutting apart of fixed number, cut apart the cutting apart to be called preferentially of this fixed number.
4, the process mapping method at the multi-mode logical unit programmable gate array according to claim 3, it is characterized in that, in described preferential partitioning algorithm, to cutting apart the target that the standard of carrying out priority calculating depends on mapping, for depth-first mapping, the degree of depth of cutting apart is as first standard, the situation that the degree of depth is identical, the input number of cutting apart is as second standard, and area is as last standard.
5, the process mapping method at the multi-mode logical unit programmable gate array according to claim 1, it is characterized in that, described constraint information according to multi-mode LC merges in the step of processing to the technology mapping result, be based on maximum radix coupling LUT net table merged optimization, specifically comprise:
Figure G can by one two tuple G (V, E) expression, the nodal set in the V representative graph wherein, E represent the line collection between the node, represents the relation between node and the node; The circuit meshwork list that merges before handling may comprise n the LUT unit smaller or equal to 3 inputs, the node v of figure G each all can be thought in these LUT unit
i({ 1,2,3...... n}), calculates per two LUT in all these LUT unit to i ∈ then
i, LUT
j(i, j ∈ 1,2, and 3......, input intersection number K (K=faninLUTi ∪ faninLUTj) n}), the time complexity of this process is O (n
2), when the K value is less than or equal to 4, the some v of these two LUT representatives
i, v
jJust be considered to abutment points each other, and these points are made marks, have a limit e between them
Ij, last, with among the figure G not with any node each other the node of abutment points cast out, just obtain a new simple graph G '; If (V E) is simple graph to G, the limit collection
If any two limits adjacency not among the M, claim that then M is coupling among the G, wherein with M in the node of frontier juncture connection be called saturation point, otherwise become unsaturated point, if M is the coupling of G, and do not exist other coupling M ' to make | M|＜| M ' |, claim that then M is the maximum radix coupling of G, is also referred to as maximum coupling; Can reduce a maximum radix coupling M who asks figure G ' towards area-optimized LUT merging process like this, the LUT of two node representatives that every limit e among the M is connected can merge among the same LC.
6, the process mapping method at the multi-mode logical unit programmable gate array according to claim 5 is characterized in that, after the described maximum of obtaining side circuit isoboles G ' is mated M, further comprises:
According to the maximum coupling M of the side circuit isoboles G ' that obtains, and the constraint of multi-mode LC library unit information, two relevant LUT are integrated with a LC, the more LUT of acquiescence input number is mapped to C-LUT3.
7, the process mapping method at the multi-mode logical unit programmable gate array according to claim 1, it is characterized in that, this method is that circuit meshwork list is converted into a figure, and maximum radix matching algorithm is applied to the merging of LUT, the pattern configurations value of the LC after being combined is at last calculated.
8, the process mapping method at the multi-mode logical unit programmable gate array according to claim 7 is characterized in that, described merging specifically comprises:
According to a pair of relevant LUT input intersection K (2≤K≤4), input union S (S=faninLUTi ∩ faninLUTj, 0≤S≤3) number, different one of the actual input number of S-LUT3 and the actual input number of C-LUT3 co-exists in 12 kinds of match condition, judge by these 12 kinds of situations during merging, calculate the Configuration Values of memory cell and three model selection MUX among the LC make new advances respectively.
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| CN102176673A (en) * | 2011-02-25 | 2011-09-07 | 中国科学院半导体研究所 | LUT4 (look up table), logical unit of FPGA (field programmed gate array) and logical block of FPGA |
| CN102375905A (en) * | 2010-08-27 | 2012-03-14 | 雅格罗技（北京）科技有限公司 | Technology mapping method for integrated circuits for improved logic cells |
| CN103259523A (en) * | 2012-02-17 | 2013-08-21 | 京微雅格（北京）科技有限公司 | Optimization method of addition chain and integrated circuit adopting addition chain |
| CN104021250A (en) * | 2014-06-09 | 2014-09-03 | 中国科学院微电子研究所 | Process mapping method for FPGA ROM storage data |
| WO2017084104A1 (en) * | 2015-11-20 | 2017-05-26 | 京微雅格（北京）科技有限公司 | Fpga-based look-up table technology mapping method and look-up table |
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| CN110543664A (en) * | 2019-07-22 | 2019-12-06 | 深圳市紫光同创电子有限公司 | Process mapping method for FPGA with special structure |
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| CN102375905A (en) * | 2010-08-27 | 2012-03-14 | 雅格罗技（北京）科技有限公司 | Technology mapping method for integrated circuits for improved logic cells |
| CN102375905B (en) * | 2010-08-27 | 2013-01-16 | 雅格罗技（北京）科技有限公司 | Technology mapping method for integrated circuits for improved logic cells |
| CN102176673B (en) * | 2011-02-25 | 2013-03-27 | 中国科学院半导体研究所 | LUT4 (look up table), logical unit of FPGA (field programmed gate array) and logical block of FPGA |
| CN102176673A (en) * | 2011-02-25 | 2011-09-07 | 中国科学院半导体研究所 | LUT4 (look up table), logical unit of FPGA (field programmed gate array) and logical block of FPGA |
| CN103259523A (en) * | 2012-02-17 | 2013-08-21 | 京微雅格（北京）科技有限公司 | Optimization method of addition chain and integrated circuit adopting addition chain |
| CN104021250B (en) * | 2014-06-09 | 2018-05-25 | 中国科学院微电子研究所 | Process mapping method for FPGA ROM storage data |
| CN104021250A (en) * | 2014-06-09 | 2014-09-03 | 中国科学院微电子研究所 | Process mapping method for FPGA ROM storage data |
| WO2017084104A1 (en) * | 2015-11-20 | 2017-05-26 | 京微雅格（北京）科技有限公司 | Fpga-based look-up table technology mapping method and look-up table |
| CN108512681A (en) * | 2017-02-28 | 2018-09-07 | 国网辽宁省电力有限公司 | A kind of method and apparatus for realizing optical distribution network deployment circuit |
| CN110543664A (en) * | 2019-07-22 | 2019-12-06 | 深圳市紫光同创电子有限公司 | Process mapping method for FPGA with special structure |
| CN110543664B (en) * | 2019-07-22 | 2022-11-18 | 深圳市紫光同创电子有限公司 | Process mapping method for FPGA with special structure |
| CN110457868A (en) * | 2019-10-14 | 2019-11-15 | 广东高云半导体科技股份有限公司 | The comprehensive optimization method and device of fpga logic, system |
| CN112926281A (en) * | 2019-12-06 | 2021-06-08 | 杭州起盈科技有限公司 | Intelligent module analysis method of digital integrated circuit |
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Open date: 20100224 |