CN110109898B - Hash connection acceleration method and system based on BRAM in FPGA chip - Google Patents
Hash connection acceleration method and system based on BRAM in FPGA chip Download PDFInfo
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- CN110109898B CN110109898B CN201910327778.6A CN201910327778A CN110109898B CN 110109898 B CN110109898 B CN 110109898B CN 201910327778 A CN201910327778 A CN 201910327778A CN 110109898 B CN110109898 B CN 110109898B
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
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- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
- G06F16/21—Design, administration or maintenance of databases
- G06F16/217—Database tuning
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
- G06F16/22—Indexing; Data structures therefor; Storage structures
- G06F16/2228—Indexing structures
- G06F16/2255—Hash tables
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- G06F16/22—Indexing; Data structures therefor; Storage structures
- G06F16/2282—Tablespace storage structures; Management thereof
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Abstract
The invention discloses a Hash connection acceleration method and a Hash connection acceleration system based on BRAM (block and branch management) in an FPGA (field programmable gate array) chip, belongs to the field of database acceleration, and aims to solve the technical problem of how to overcome the defect that a Hash connection software scheme occupies more CPU (central processing unit) calculation and I/O (input/output) resources. The method is that a plurality of dimension tables or a plurality of columns of the same dimension table are connected to a fact table in parallel through a plurality of channels, and comprises the following steps: in a hash connection construction stage, configuring a corresponding channel for each dimension table in an FPGA (field programmable gate array), and storing the hash table and an address table through BRAM (binary redundancy management) in an FPGA chip; and in the stage of Hash connection detection, routing the fact table to a corresponding channel, and connecting the row data of the matched fact table with the row data of the dimension table. The structure of the system comprises a BRAM in an FGPA chip configured on a PFGA, a plurality of channels, a hash calculation module, an extraction/hash module, a verification module, a connection module and a control module.
Description
Technical Field
The invention relates to the field of database acceleration, in particular to a Hash connection acceleration method and a Hash connection acceleration system based on BRAM in an FPGA chip.
Background
Business decision of enterprises, stock exchange of financial systems and the like in modern society increasingly depend on database systems with high efficiency and low delay, and particularly, the real-time performance is required to be high in data query and data analysis links. In the relational database, the Join operator, as an operation that needs to be executed frequently, occupies a considerable amount of CPU computing resources. Common Join operators include Sort Merge-Join (Sort Merge-Join), nested Loop-Join (Nested Loop-Join), and so on. However, with the continuous increase of the database scale, for the sorting and merging connection, if the result set obtained after applying the predicate condition specified in the target SQL is large and needs to be sorted, the execution efficiency of the sorting and merging connection is not high; for the nested loop connection, if the number of records of the driving result set corresponding to the driving table is large, even if there is an index on the connection column of the driven table, there is a problem that the execution efficiency is not high when the nested loop connection is used. The two software implementation schemes of the Join operator occupy a large amount of CPU computing resources, and when the data volume is large, the operation and time cost is high.
In order to solve the complexity problem of the two Join operators, a Hash connection (Hash-Join) operator is introduced into a large database: in the Hash connection, the optimizer firstly selects a smaller table of the two tables according to the statistical information, and establishes a Hash table based on a connection key of the table in a memory; the optimizer rescans the larger table in the table join, compares the data in the large table with the hash table, and if there is associated data, adds the data to the result set. Through Hash operation, the time complexity can be reduced from quadratic to linear, but more CPU calculation and I/O resources are still occupied.
How to overcome the problem of occupying more CPU calculation and I/O resources in the hash connection software scheme is a technical problem to be solved.
Disclosure of Invention
The technical task of the invention is to provide a hash connection acceleration method and a hash connection acceleration system based on BRAM in an FPGA chip to solve the problem of how to occupy more CPU (central processing unit) calculation and I/O (input/output) resources in a hash connection software scheme.
In a first aspect, the present invention provides a hash connection acceleration method based on BRAM in FPGA slice, which connects multiple dimension tables or multiple columns of the same dimension table to a fact table in parallel through multiple channels, including:
s100, configuring a corresponding channel for each dimension table in an FPGA (field programmable gate array) at a hash connection construction stage, calculating a hash value of column data of each dimension table to generate a hash table, linking the column data of the dimension tables with the same hash value to the same linked list to generate an address table, and storing the hash table and the address table through a BRAM (block counter) in an FPGA chip;
s200, in the hash connection detection stage, routing the fact table to a corresponding channel, calculating a hash value of column data of the fact table, and connecting the row data of the matched fact table with the row data of the dimension table.
Preferably, step S100 includes the following substeps:
s110, inputting the dimension tables into the FPGA in a sequential streaming manner according to the connection conditions, and configuring a corresponding associated channel for each dimension table in the FPGA;
s120, extracting a corresponding database page unit for each dimension table through the FPGA, and storing the database page unit through BRAM in the FPGA chip;
s130, calculating a hash value of column data of each dimension table through the FPGA, and storing the hash value in a hash table;
and S140, linking the column data of the dimension tables with the same hash value to the same linked list, and storing the linked list in an address table.
Preferably, each channel is provided with a proprietary resource that allows all the channels of the above configuration to be processed in parallel during the probing phase of the hash table.
Preferably, S200 includes the following steps;
s210, extracting and verifying the column data of the fact table through FFPGA, and routing the column data of the fact table to a corresponding channel according to a matching requirement;
s220, synchronously performing hash calculation on the column data of the fact table in each channel, verifying the columns of the fact table and the columns of the dimension table based on the hash values of the column data of the fact table, and executing the step S230 after the verification is successful;
and S230, comparing and matching the data flow type of the line data of the fact table with the data of the line data of the dimension table, connecting the data of the line data of the fact table with the data of the line data of the dimension table if the matching conditions are met, and discarding the corresponding data of the line data of the fact table if the matching conditions are not met. A join result is obtained and formatted into database page units of 4 KB.
Preferably, the hash calculation of the column data of the fact table in each channel synchronization in step S220, and the verification of the columns of the fact table and the columns of the dimension table based on the hash values of the column data of the fact table, includes:
calculating the column data hash value of each fact table, transmitting the column data hash value of the fact table to a hash table for verification, and judging whether the column data hash value of the fact table is the same as the column data hash value of the dimension table;
and if the column data hash value of the fact table is the same as the column data hash value of the dimension table, transmitting the column data of the fact table to the address table, and judging whether the column number of the fact table is the same as the column data of the dimension table.
Preferably, in step S230, after the line data of the fact table and the line data of the dimension table are linked, the linking result is formatted into a database page unit of 4 KB.
In the above embodiment, the database page unit of 4KB is transmitted to the database management system for later analysis processing.
In a second aspect, the present invention provides a hash connection acceleration system based on BRAM in FPGA slice, which includes:
the FGPA on-chip BRAM is used for storing a hash table, an address table and a database meta-unit;
a plurality of channels, each channel being provided with a proprietary resource allowing parallel processing of all the configured channels in a probing phase of a hash table;
the hash calculation module is used for calculating the hash value of the column data of the dimension table;
the extraction module is used for extracting a database page unit for each dimension table;
the extraction/hash module is used for matching the fact tables into the corresponding channels and calculating the column data hash value of each fact table;
the verification module is matched with the hash table and the address table and used for verifying the columns of the fact table and the columns of the dimension table; the connection module is used for connecting the line data of the matched fact table with the line data of the dimension table through a connection function;
and the control module is used for coordinating the work of each module through a state machine method, and comprises the steps of analyzing instructions from a database management system, and controlling data inflow, hash calculation and BRAM data access.
Preferably, the verification module is a module having the following functions:
judging whether the column data hash value of the fact table is the same as the column data hash value of the dimension table or not according to the column data hash value of the fact table on the basis of the hash table;
and if the column data hash value of the fact table is the same as the column data hash value of the dimension table, judging whether the column number of the fact table is the same as the column data of the dimension table or not based on the address table.
The hash connection acceleration method and system based on BRAM in the FPGA chip have the following advantages:
1. the FPGA retrieves the latest data from the system memory and executes the table connection operation with high parallelism, thereby realizing performance acceleration of several times compared with the traditional software scheme;
2. hash calculation is carried out in the FPGA, the Hash table and the address table are stored in the BRAM in the FPGA chip, and the BRAM in the FPGA chip can provide a quick searching function, so that a Hash operator can be directly operated in the FPGA without being externally connected with a DDR storage unit, and the application with quick processing response requirements is adapted;
3. the main module is stored in the high-speed Block RAM in the FPGA chip, so that the external main memory does not need to be frequently accessed, and the memory bottleneck in a CPU software scheme is overcome.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
The invention is further described below with reference to the accompanying drawings.
Fig. 1 is a flow diagram of a hash connection acceleration method based on BRAM in an FPGA slice in embodiment 1;
fig. 2 is a working principle block diagram of a hash connection construction stage in the hash connection acceleration method based on BRAM in FPGA slice in embodiment 1;
fig. 3 is a working principle box of a hash connection detection stage in the hash connection acceleration method based on BRAM in the FPGA slice in embodiment 1;
fig. 4 is a schematic block diagram of hash connection in the hash connection acceleration method based on BRAM on the FPGA slice in embodiment 1.
Detailed Description
The present invention is further described below with reference to the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and can implement the present invention, but the embodiments are not intended to limit the present invention, and the embodiments and technical features of the embodiments can be combined with each other without conflict.
It is to be understood that "a plurality" in the embodiments of the present invention means two or more.
The embodiment of the invention provides a Hash connection acceleration method and a Hash connection acceleration system based on BRAM in an FPGA chip, which are used for solving the technical problem of how to overcome the occupation of more CPU calculation and I/O resources in a Hash connection software scheme.
Example 1:
as shown in fig. 1-4, the hash connection acceleration method based on BRAM in FPGA slice of the present invention connects multiple dimension tables or multiple columns of the same dimension table to a fact table in parallel through multiple channels, including:
s100, configuring a corresponding channel for each dimension table in the FPGA at a hash connection construction stage, calculating the hash value of the column data of each dimension table to generate a hash table, linking the column data of the dimension tables with the same hash value to the same linked list to generate an address table, and storing the hash table and the address table through a BRAM (binary redundancy management) in an FPGA chip;
s200, in the hash connection detection stage, routing the fact table to a corresponding channel, calculating a hash value of column data of the fact table, and connecting the row data of the matched fact table with the row data of the dimension table.
In the hash join construction stage, the method comprises the following steps:
s110, the dimension tables are sequentially transmitted to an FPGA in a streaming mode by a database management system according to connection adjustment, the FPGA configures corresponding channels for each dimension table, each channel is provided with a proprietary resource, and the proprietary resource allows all the configured channels to be processed in parallel in a detection stage of the hash table;
s120, extracting a corresponding database page unit for each dimension table through the FPGA, storing the database page unit through BRAM (file management module) in an FPGA chip, directly reading the database page unit into a memory from a disk, and then transmitting the database page unit to the FPGA in a flowing manner;
s130, calculating a hash value of column data of each dimension table through the FPGA, and storing the hash value in a hash table;
and S140, linking the column data of the dimension tables with the same hash value to the same linked list, and storing the linked list in an address table.
Streaming dimension tables in order does not add significant overhead in the above steps, because dimension tables are typically smaller in size than fact tables.
The hash table is in the form of bitvector in the FPGA, namely, the hash table is a bit vector.
Step S200 includes the following sub-steps:
s210, extracting and verifying the column data of the fact table through FFPGA, and routing the column data of the fact table to a corresponding channel according to a matching requirement;
s220, synchronously performing hash calculation on the column data of the fact table in each channel, verifying the columns of the fact table and the columns of the dimension table based on the hash values of the column data of the fact table, and executing the step S230 after the verification is successful;
and S230, comparing and matching the data flow type of the data of the fact table with the data of the dimension table, connecting the data of the fact table with the data of the dimension table if the matching conditions are met, discarding the corresponding data of the rows of the fact table if the matching conditions are not met, obtaining a connection result, and formatting the connection result into a database page unit of 4 KB. And sends the 4KB database page unit to the database management system for later analysis processing.
In step S220, performing hash calculation on the column data of the fact table in each channel synchronization, and verifying the columns of the fact table and the columns of the dimension table based on the hash value of the column data of the fact table, including: and calculating the column data hash value of each fact table, transmitting the column data hash value of each fact table to a hash table for verification, judging whether the column data hash value of each fact table is the same as the column data hash value of each dimension table, if the column data hash value of each fact table is the same as the column data hash value of each dimension table, transmitting the column data of each fact table to an address table, and judging whether the column number of each fact table is the same as the column data of each dimension table.
In step S230, the line data of the fact table and the line data of the dimension table are connected by an address mapping method.
Example 2:
the invention provides a Hash connection acceleration subsystem based on BRAM in an FPGA (field programmable gate array) chip, which comprises the BRAM in the FGPA chip, a plurality of channels, a Hash calculation module, an extraction/Hash module, a verification module and a control module which are arranged on a PFGA (field programmable gate array).
The BRAM in the FGPA chip is used for storing a hash table, an address table and a database meta-unit.
Each channel is equipped with proprietary resources that allow all of the channels of the multiple above configurations to be processed in parallel during the probing phase of the hash table.
The hash calculation module is used for calculating a hash value of column data of the dimension table.
The extraction module is used for extracting a database page unit for each dimension table.
The decimation/hashing module is used for matching the fact tables into the corresponding channels and calculating the column data hash value of each fact table.
The verification module is matched with the hash table and the address table and used for verifying the columns of the fact table and the columns of the dimension table; and the connection module is used for connecting the line data of the matched fact table with the line data of the dimension table through a connection function.
And the control module is used for coordinating the work of each module through a state machine method, and comprises the steps of analyzing instructions from a database management system, and controlling data inflow, hash calculation and BRAM data access.
The verification module realizes verification through the following method: and judging whether the column data hash value of the fact table is the same as the column data hash value of the dimension table or not according to the column data hash value of the fact table on the basis of the hash table, and if so, judging whether the column number of the fact table is the same as the column data hash value of the dimension table on the basis of the address table.
The hash connection acceleration system based on the BRAM in the FPGA chip can realize the hash connection acceleration method based on the BRAM in the FPGA chip disclosed by the embodiment 1.
The above-mentioned embodiments are merely preferred embodiments for fully illustrating the present invention, and the scope of the present invention is not limited thereto. The equivalent substitution or change made by the technical personnel in the technical field on the basis of the invention is all within the protection scope of the invention. The protection scope of the invention is subject to the claims.
Claims (7)
1. The Hash connection acceleration method based on BRAM in FPGA chips is characterized in that a plurality of dimension tables are connected to a fact table in parallel through a plurality of channels, and comprises the following steps:
s100, configuring a corresponding channel for each dimension table in an FPGA (field programmable gate array) at a hash connection construction stage, calculating a hash value of column data of each dimension table to generate a hash table, linking the column data of the dimension tables with the same hash value to the same linked list to generate an address table, and storing the hash table and the address table through a BRAM (block counter) in an FPGA chip;
s200, in a hash connection detection stage, routing the column data of the fact table to a corresponding channel according to matching requirements, calculating a hash value of the column data of the fact table, and connecting the row data of the matched fact table with the row data of the dimension table;
wherein, S200 comprises the following steps;
s210, extracting and verifying the column data of the fact table through the FPGA, and routing the column data of the fact table to a corresponding channel according to a matching requirement;
s220, synchronously performing hash calculation on the column data of the fact table in each channel, verifying the columns of the fact table and the columns of the dimension table based on the hash values of the column data of the fact table, and executing the step S230 after the verification is successful;
and S230, comparing and matching the data flow type of the data of the fact table with the data of the dimension table, connecting the data of the fact table with the data of the dimension table if the matching conditions are met, discarding the corresponding data of the rows of the fact table if the matching conditions are not met, obtaining a connection result, and formatting the connection result into a database page unit of 4 KB.
2. The hash connection acceleration method based on BRAM on FPGA slice of claim 1, wherein the step S100 comprises the following sub-steps:
s110, inputting the dimension tables into the FPGA in a sequential streaming manner according to the connection conditions, and configuring a corresponding associated channel for each dimension table in the FPGA;
s120, extracting a corresponding database page unit for each dimension table through the FPGA, and storing the database page unit through BRAM in the FPGA chip;
s130, calculating a hash value of column data of each dimension table through the FPGA, and storing the hash value in a hash table;
and S140, linking the column data of the dimension tables with the same hash value to the same linked list, and storing the linked list in an address table.
3. The method of claim 2, wherein each channel is configured with proprietary resources that allow all of the configured channels to be processed in parallel during the probing phase of the hash table.
4. The hash connection acceleration method based on BRAM on FPGA slice of claim 1, wherein the step S220 performs hash calculation on the column data of the fact table at each channel synchronization, and verifies the columns of the fact table and the columns of the dimension table based on the hash value of the column data of the fact table, comprising:
calculating the column data hash value of each fact table, transmitting the column data hash value of the fact table to a hash table for verification, and judging whether the column data hash value of the fact table is the same as the column data hash value of the dimension table;
and if the column data hash value of the fact table is the same as the column data hash value of the dimension table, transmitting the column data of the fact table to the address table, and judging whether the column number of the fact table is the same as the column data of the dimension table.
5. The hash join acceleration method based on BRAM on FPGA slice as claimed in claim 1, wherein in step S230, after the line data of the fact table and the line data of the dimension table are joined, the join result is formatted into a database page unit of 4 KB.
6. Hash connection acceleration system based on BRAM in FPGA chip is characterized by comprising the following components configured on PFGA:
the FGPA on-chip BRAM is used for storing a hash table, an address table and a database meta-unit;
a plurality of channels, each channel being provided with a proprietary resource allowing parallel processing of all the configured channels in a probing phase of a hash table;
the hash calculation module is used for calculating the hash value of the column data of the dimension table;
the extraction module is used for extracting a database page unit for each dimension table;
the extraction and hash module is used for matching the fact tables into the corresponding channels and calculating the column data hash value of each fact table;
the verification module is matched with the hash table and the address table and used for verifying the columns of the fact table and the columns of the dimension table; the connection module is used for connecting the line data of the matched fact table with the line data of the dimension table through a connection function;
and the control module is used for coordinating the work of each module through a state machine method, and comprises the steps of analyzing instructions from a database management system, and controlling data inflow, hash calculation and BRAM data access.
7. The BRAM hash connection acceleration system in FPGA-based on-chip of claim 6, wherein the verification module is a module having functions of:
judging whether the column data hash value of the fact table is the same as the column data hash value of the dimension table or not according to the column data hash value of the fact table on the basis of the hash table;
and if the column data hash value of the fact table is the same as the column data hash value of the dimension table, judging whether the column number of the fact table is the same as the column data of the dimension table or not based on the address table.
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| CN111382158B (en) * | 2020-03-09 | 2023-04-28 | 北京东方金信科技股份有限公司 | Method and system for realizing parallel connection by adopting two-stage hash table structure |
| CN112069216A (en) * | 2020-09-18 | 2020-12-11 | 山东超越数控电子股份有限公司 | Join algorithm implementation method, system, device and medium based on FPGA |
| CN112256704A (en) * | 2020-10-23 | 2021-01-22 | 山东超越数控电子股份有限公司 | Quick join method, storage medium and computer |
| CN112765174B (en) * | 2021-01-20 | 2024-03-29 | 上海达梦数据库有限公司 | Hash connection-based detection method, device, equipment and storage medium |
| CN113296705B (en) * | 2021-05-27 | 2022-09-27 | 浙江萤火虫区块链科技有限公司 | Framework system for parallel computing Poseido Hash in Filecin |
| CN113468181B (en) * | 2021-07-14 | 2022-10-11 | 中国人民解放军军事科学院国防科技创新研究院 | Parallel Hash connection acceleration method and system based on FPGA |
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| US9817612B2 (en) * | 2014-11-20 | 2017-11-14 | International Business Machines Corporation | High-performance hash joins using memory with extensive internal parallelism |
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