CN102176673B - LUT4 (look up table), logical unit of FPGA (field programmed gate array) and logical block of FPGA - Google Patents
LUT4 (look up table), logical unit of FPGA (field programmed gate array) and logical block of FPGA Download PDFInfo
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Abstract
The invention discloses an LUT4 (look up table), a logical unit of an FPGA (field programmed gate array) and a logical block of the FPGA. The LUT4 comprises two LUT3s and four one-in-two multiplexers, wherein each LUT3 comprises a C-LUT3 and an S-LUT3, and each one-in-two multiplexer comprises an FMUX (flexible multiplexer), a CMUX, an SMUX and an F4MUX; output of data input ports A0, A1 and A2(0) respectively enter into three input ports of the C-LUT3 after the data input ports A0, A1 and A2(0) are selected by the CMUX; output of data input ports A0, A1(0) and A3(1) which are selected by the SMUX and output of the data input port A2(0) which is selected by the CMUX respectively enter into three input ports of the S-LUT3; output of a data input port A3(1) and logic '0' respectively enter into a control port of the F4MUX after the data input port A3(1) and the logic '0' are selected by the FMUX, and output (0) of the S-LUT3 is output by an output port F4 of the LUT4 after the S-LUT3 is selected by the F4MUX; and in the logical unit of the FPGA, Fmux, Smux and Cmux are respectively control bits of the FMUX, the SMUX and the CMUX. The LUT4, the logical unit of the FPGA and the logical block of the FPGA can improve logical density.
Description
Technical field
The present invention relates to semiconductor and microelectronics technology, relate in particular to a kind of 4 input look-up table (Look Up Table, be called for short LUT) LUT4, based on field programmable gate array (the Field Programmed Gate array of this LUT4, be called for short FPGA) logical block, and based on the fpga logic piece of above-mentioned fpga logic unit.
Background technology
With application-specific integrated circuit (ASIC) (Application Specific Integrated Circuits, be called for short ASIC) compare, the characteristics such as low and construction cycle of the R﹠D costs of FPGA is short make it become a kind of important core technology that realizes modern digital circuits and system, and its market share volume is also increasing year by year.As the elementary cell that is used for logic realization among the FPGA, logical block and directly had influence on to a great extent the performances such as the speed of FPGA and area utilization by the design of its logical block that consists of.
Existing document proves: LUT4 can make the fpga chip area utilization reach the highest.The most typical fpga logic of academic circles at present and industrial quarters unit is to be made of a traditional LUT4 and a D flip-flop.
Modern Commercial FPGA comprises that also some are used as the embedded IP kernel of special purpose, such as multiplication module and memory module.The Virtex series of Xilinx and the Cyclone series of Altera just provide abundant memory module resource for the user.However, need the application of a large amount of storage resources for some, for certain fpga chip, inner memory module resource is limited after all, so these memory modules or not enough.
Also have, for logical resource and the more application of low capacity storage resource consumption, if realize the memory of low capacity with jumbo memory module, will cause the waste of memory module residue storage resources, so the distributed RAM of low capacity just can satisfy such application.
Because the LUT of existing 4 inputs can not reduce logic density for the logic that realizes any 4 inputs, but for the logic that realizes any 3 inputs or 2 inputs, because the LUT of 4 inputs only has an output, so can only realize that one 3 is inputted or 2 logics of inputting, and based on the LUT4 of 3 input LUT 2 outputs need to be arranged, so just can realize that 23 are inputted or 2 logics of inputting, therefore the LUT logic density of existing 4 inputs are low.In realizing process of the present invention, the inventor recognizes that there is following defective in prior art: existing LUT4 logic density is low.
Summary of the invention
The technical problem that (one) will solve
For the problems referred to above, the present invention proposes a kind of LUT4 based on two LUT3, based on the fpga logic unit of this LUT4 and based on the fpga logic piece of this fpga logic unit.This LUT4 compares with existing LUT4, has improved logic density.
(2) technical scheme
According to an aspect of the present invention, a kind of 4 input look-up table LUT4 are provided.This LUT4 comprises: two 3 inputs look-up table LUT3 and four 2 select 1 multiplexer, and these two LUT3 are C-LUT3 and S-LUT3, and these four 2 are selected 1 multiplexer is FMUX, CMUX, SMUX and F4MUX.Data-in port A0, A1, and the output after A2 (0) the process CMUX selection enters respectively three input ports of C-LUT3.Output after data-in port A0, A1 (0) select through SMUX with A3 (1), and the output after A2 (0) the process CMUX selection enters respectively three input ports of S-LUT3.Output after data-in port A3 (1) and logic ' 0 ' are selected through FMUX enters the control port of F4MUX, and the output port F4 from this LUT4 after the output of S-LUT3 (0) is selected through F4MUX exports.In the fpga logic unit, Fmux, Smux and Cmux are respectively FMUX, the control bit of SMUX and CMUX.
Preferably, among the technical program LUT4, one of three input ports that the output after A2 (0) selects through CMUX enters respectively C-LUT3 are: the output after A2 (0) selects through CMUX with CI (1) enters respectively one of three input ports of C-LUT3.One of three input ports that output after A2 (0) selects through CMUX enters respectively S-LUT3 are: the output after A2 (0) selects through CMUX with CI (1) enters respectively one of three input ports of S-LUT3.Output port F4 from this LUT4 after the output of S-LUT3 (0) is selected through F4MUX is output as: the output port F4 from this LUT4 after the output CO (1) of C-LUT3 and the output (0) of S-LUT3 are selected through F4MUX exports.
Preferably, among the technical program LUT4, according to control bit Fmux, the various combination of Smux and Cmux, the mode of operation of configuration LUT4: work as Smux=0, Cmux=0, during Fmux=1, its mode of operation is LUT4; Or work as Smux=0, and Cmux=1, during Fmux=0, its mode of operation is carry chain; Or work as Smux=0, and Cmux=0, during Fmux=0, its mode of operation is the carry begin chain; Or work as Smux=1, and Cmux=0, during Fmux=0, its mode of operation is multiplier.
According to another aspect of the present invention, provide a kind of on-site programmable gate array FPGA logical block.This fpga logic unit comprises that above LUT4, D flip-flop and four 2 select 1 multiplexer BMUX, F5MUX, DMUX0 and DMUX1.D flip-flop comprises: data-in port D, data-out port XQ, control inputs port CE and SR, input end of clock mouth CK, overall set-reset port GSR.The input port of fpga logic unit comprises: the data-in port A0 of 4 input LUT, A1, A2, A3 and data-in port B, F5I; The output port of fpga logic unit comprises: the data-out port F4 of 4 input LUT and data-out port XB, XF, XQ.The output port CO (0) of data-in port B (1) and C-LUT3 exports XB through behind the BMUX; The output port F4 (0) of data-in port F5I (1) and LUT4 enters 1 input port of DMUX1 through the output behind the F5MUX, F4 enters 0 input port of DMUX1, and DMUX1 is output as XF; Output entered the data-in port D of D flip-flop after XF (1) and B (0) selected through DMUX0, and the output port of D flip-flop is as the data-out port XQ of fpga logic unit.Bmux, Dmux1 and Dmux0 are respectively B5MUX, the control bit of DMUX1 and DMUX0.
Preferably, in the technical program fpga logic unit, CI is as the Carry Chains input port of fpga logic unit; CO is as the Carry Chains output port of fpga logic unit.
Preferably, in the technical program fpga logic unit, Fmux, Smux, Cmux, Bmux, Dmux1 and Dmux0 are 5 transistor memory units.
Preferably, in the technical program fpga logic unit, in the fpga logic unit, according to control bit Bmux, the various combination of Dmux1 and Dmux0, the signal of configuration fpga logic unit flows to: work as Bmux=0, F5mux=0, Dmux0=0 is during Dmux1=0/1, signal flows to as CO drives XB, and B drives D; Or work as Bmux=0, and F5mux=0, Dmux0=1, during Dmux1=0/1, signal flows to as CO drives XB, and LUT4 drives D; Or work as Bmux=0, and F5mux=1, Dmux0=0, during Dmux1=0/1, signal flows to as CO drives XB, and B drives D; Or work as Bmux=0, and F5mux=1, Dmux0=1, during Dmux1=0/1, signal flows to as CO drives XB, and LUT4 drives D; Or work as Bmux=1, and F5mux=0, Dmux0=0, during Dmux1=0/1, signal flows to as B drives XB, and B drives D; Or work as Bmux=1, and F5mux=0, Dmux0=1, during Dmux1=0/1, signal flows to as B drives XB, and LUT drives D; Or work as Bmux=1, and F5mux=1, Dmux0=0, during Dmux1=0/1, signal flows to as B drives XB, and B drives D; Or work as Bmux=1, and F5mux=1, Dmux0=1, during Dmux1=0/1, signal flows to as B drives XB, and LUT4 drives D.
Preferably, in the technical program fpga logic unit, d type flip flop comprises: core register and 42 select 1 multiplexer CKPOLMUX, SRSYNCMUX, SRSELMUX, QTYPEMUX; This d type flip flop input comprises data input D, clock CK, and clock enables CE, and set/reset SR and overall set/reset GSR are output as data output Q; Output after SR (0) and logic ' 0 ' (1) process SRSYNCMUX select, this output and GSR carry out or logic, or the output of logic is respectively the set/reset end of core register through SRSELMUX output generation S (0) and R (1); CK (1) and～CK (0) selects to enter the CK end of core register through CKPOLMUX, the input QL (0) of core register and QF (1) select to input Q through QTYPEMUX; 2 select 1 multiplexer CKPOLMUX, SRSYNCMUX, and SRSELMUX, the control bit of QTYPEMUX is respectively ckpol, srsync, srsel, qtype is according to control bit ckpol, srsync, srsel, the various combination of qtype, d type flip flop are configured to dissimilar register or latch.
Preferably, in the technical program fpga logic unit, in the d type flip flop, according to control bit ckpol, d type flip flop is configured to just along triggering or the negative edge triggering; And/or according to control bit srsync, d type flip flop is configured to synchronous or asynchronous; And/or according to control bit srsel, d type flip flop is configured to set or resets; And/or according to control bit qtype, d type flip flop is configured to register or latch.
According to another aspect of the present invention, provide a kind of fpga logic piece.This logical block comprises: the first fpga logic unit, and the second fpga logic unit, local interlinkage, and distributed RAM logic, wherein the first fpga logic unit and the second fpga logic unit are fpga logic unit above; The port of this fpga logic piece comprises 2 overall input port-G＜1:0 〉, 12 input port-I＜11:0,8 output port-O＜7:0, Carry Chains input port-CI, Carry Chains output port-CO and 1 overall set-reset port-SR and 1 global write enable port-GWE; Local interlinkage comprises: being connected between logical block overall situation input port and logical block clock port and the control inputs port; Being connected between logical block input port and the logical block input port; Feedback link between logical block output port and the logical block data input port; Connection between logic ' 0 ' and logic ' 1 ' and the logical block input port; Being connected between logical block output port and the logical block output port.
Preferably, in the technical program fpga logic piece, distributed RAM logic comprises: SYN register, write control module, write multiplexer, read multiplexer, two logical blocks of this distributed RAM and fpga logic piece are shared data input A0[3:0], A1[3:0], B0, B1, SR, CK shares data output XF0 and XF1.The data that SYN register is used for writing synchronously, address and write control signal; Write the trend that control module is used for controlling data writing; Write multiplexer and be used for position with the memory cell of new data writing address appointment; Reading multiplexer is 4 input LUT of logical block in the fpga logic piece.According to the opposed polarity of control ramckpol, distributed RAM can be configured to clock just edge or negative edge data writing.Control bit S1 with write enable signal WE (SR is through the output after depositing) respectively in writing control module through carrying out and logic with door WENAND0 and WENAND1, all enter with the output of logic and to write writing of multiplexer control data; Control bit S2 controls writing of data by control transmission gate S2PASS in writing control module; Control bit S3 controls the selection that S3MUX0 and S3MUX1 control write address in SYN register, and in writing control module and Din1orA4 (B1 is through the output after depositing) be data input or the 5th address by carrying out controlling B1 with logic with door A4NAND; Control bit D controls the selection that DMUX controls write address in SYN register, and control transmission gate DPASS controls writing of data in writing control module; Control bit ramckpol controls RAMCKPOLMUX; The fpga logic piece has different mode of operations according to the difference of control bit (S1, S2, S3, D) polarity.
Preferably, in the technical program fpga logic piece, being connected between logical block overall situation input port and logical block clock port and the control inputs port comprises: overall input port G＜1〉directly link to each other overall input port G＜0 with the CK of two logical blocks〉control and can be connected with SR or CE by control bit.Being connected between logical block input port and the logical block input port comprises: data-in port I＜6 〉, I＜0 〉, I＜9 〉, I＜3〉respectively with the data-in port A0 of the first fpga logic unit, A1, A2, A3 directly connects, I＜8 〉, I＜2 〉, I＜11 〉, I＜5〉respectively with the A0 of the second fpga logic unit, A1, A2, A3 directly connects, I＜7〉directly be connected with the B0 of the first fpga logic unit, I＜1〉B1 of the second fpga logic unit directly connects I＜10〉directly be connected I＜4 with CE〉directly be connected with SR.The logical block output port comprises with feedback link between the logical block data input port: output F4 in the first fpga logic unit directly is connected with the second fpga logic unit input F5i, and output F4 in the second fpga logic unit inputs F5i with the first fpga logic unit and directly is connected.Connection between logic ' 0 ' and logic ' 1 ' and the logical block input port comprises: logic ' 0 ' is connected with logic and 1 ' can be connected with the first fpga logic unit input B0, logic ' 0 ' is connected with logic and 1 ' can be connected with the second fpga logic unit input B1, logic ' 0 ' and logic ' 1 ' can with the common input CE of two logical blocks in the fpga logic piece, SR, CE connects.Being connected between logical block output port and the logical block output port comprises: output port O (0) is by output port XQ0 and the XB0 of the first logical block, the output port XF1 output of the second logical block, output port O (1) is by the output port XF0 of the first logical block, the output port XQ1 of the second logical block and XB1 output, output port O (2) is by the output port XQ0 of the first logical block, the output port XF1 output of the second logical block, output port O (3) is by output port XF0 and the XB0 of the first logical block, the output port XQ1 output of the second logical block, output port O (4) is by the output port XQ0 of the first logical block, the output port XF1 of the second logical block and XB1 output, output port O (5) is by the output port XF0 of the first logical block, the output port XQ1 output of the second logical block, output port O (6) is by the output port XQ0 of the first logical block, the output port XF1 output of the second logical block, output port O (7) is by the output port XF0 of the first logical block, and the output port XQ1 of the second logical block exports.
Preferably, in the technical program fpga logic piece, S1=0; S2=0; S3=0; During D=0, the mode of operation of logical block is LUT; Or S1=1; S2=0; S3=0; During D=0, the mode of operation of logical block is single port 16 * 1RAM; Or S1=1; S2=1; S3=0; During D=0, the mode of operation of logical block is single port (16 * 1) * 2RAM; Or S1=1; S2=0; S3=1; During D=0, the mode of operation of logical block is single port 32 * 1RAM; Or S1=1; S2=0; S3=0; During D=1, the mode of operation of logical block is dual-port 16 * 1RAM.
Preferably, in the technical program fpga logic piece, when the fpga logic piece was realized the Fast Carry Logic logic: the carry input mouth CI of fpga logic piece directly was connected with the carry input mouth CI of the first fpga logic unit, the carry output port CO of the first fpga logic unit directly is connected with the carry input mouth CI of the second fpga logic unit, and the carry output port CO of the second fpga logic unit is by the carry output port CO output of logical block.
Preferably, in the technical program fpga logic piece, the CO port of fpga logic piece links to each other with the CI port of adjacent fpga logic piece; And/or the CO port of the CI port of fpga logic piece fpga logic piece adjacent with another links to each other.
Preferably, in the technical program fpga logic piece, when the fpga logic piece was realized the shift register chain logic, the logical block input port B directly or after being deposited was passed logical block.
(3) beneficial effect
1, LUT4 of the present invention not only can realize any Boolean logic of one 4 input, can also realize the Boolean logic of two 3 inputs.This LUT4 compares with existing LUT4, has improved logic density.
2, in the fpga logic of the present invention unit, according to the difference of control bit, this fpga logic unit can be configured to 8 kinds of mode of operations, and wherein the most frequently used have 4 kinds: LUT4, carry chain, carry begin chain and multiplier.The advantage of this fpga logic unit maximum can improve logic density exactly.
3, in the fpga logic piece of the present invention LUT is used as distributed RAM, the application of concentrating for storage resources can remedy the deficiency of memory module resource, and stores the application of concentrating for low capacity and can improve resource utilization.
Description of drawings
Fig. 1 is the logical construction schematic diagram of embodiment of the invention LUT4;
Fig. 2 is the logical construction schematic diagram of embodiment of the invention fpga logic unit;
Fig. 3 is the structural representation that is used for 5 transistor memory units of control bit storage information in the embodiment of the invention fpga logic unit;
Fig. 4 is the logical construction schematic diagram of d type flip flop in the embodiment of the invention fpga logic unit;
Fig. 5 is embodiment of the invention fpga logic piece port distribution and schematic layout pattern;
Fig. 6 is the schematic diagram of embodiment of the invention fpga logic piece local interlinkage;
Fig. 7 is the building-block of logic of distributed RAM in the embodiment of the invention fpga logic piece;
Fig. 8 is the connection diagram that embodiment of the invention fpga logic piece is realized the Fast Carry Logic logic;
Fig. 9 is the connection diagram that embodiment of the invention fpga logic piece is realized the chain of registers logic;
Figure 10 embodiment of the invention fpga logic piece is as the logical construction schematic diagram of single port 32 * 1RAM;
Figure 11 is that embodiment of the invention fpga logic piece is as the logical construction schematic diagram of two-port RAM.
Table 1 is embodiment of the invention fpga logic unit four kinds of mode of operations commonly used;
Table 2 is that the signal of embodiment of the invention fpga logic unit flows to;
Table 3 is the mode of operation of d type flip flop in the embodiment of the invention fpga logic unit;
The mode of operation that table 4 is realized according to the setting of control bit for embodiment of the invention fpga logic piece;
Signal source when table 5 works in LUT pattern and single port pattern ram for the fpga logic piece;
Signal source when table 6 works in LUT pattern and two-port RAM pattern for the fpga logic piece.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
One, 4 input LUT (LUT4)
The present embodiment at first discloses a kind of LUT4, and Fig. 1 is the logical construction schematic diagram of embodiment of the invention LUT4.As shown in Figure 1, this LUT4 comprises: two 3 inputs look-up table LUT3 and four 2 select 1 multiplexer.These two LUT3 are C-LUT3 and S-LUT3, and these four 2 are selected 1 multiplexer is FMUX, CMUX, SMUX and F4MUX.Data-in port A0, A1, and the output after A2 (0) the process CMUX selection enters respectively three input port A of C-LUT3, B, C.Output after data-in port A0, A1 (0) select through SMUX with A3 (1), and the output after A2 (0) the process CMUX selection enters respectively three input port A of S-LUT3, B, C.Output after data-in port A3 (1) selects through FMUX with logic ' 0 ' (0) enters the control port of F4MUX.Output port F4 from this LUT4 after the output (0) of output CO (1) S-LUT3 of C-LUT3 is selected through F4MUX exports.Among this LUT4, Fmux, Smux and Cmux are respectively described FMUX, the control bit of SMUX and CMUX.For convenience of description, be connected with 0 port of alternative multiplexer MUX and be abbreviated as 0, be connected with 1 port and be abbreviated as 1.For the LUT4 of the present embodiment, can realize the logic of 4 inputs and the logic of 3 inputs according to user's needs, specifically:
1) as described Smux=0, Cmux=0, during Fmux=0, its mode of operation is for realizing the logic of two 3 inputs, the input of two 3 input logics is A0, A1, A2; Or as described Smux=0, Cmux=0, during Fmux=1, its mode of operation is input as A0, A1, A2, A3 for realizing 14 input logic;
2) as described Smux=0, Cmux=1, during Fmux=0, its mode of operation is for realizing two 3 input logics, the input of two 3 input logics is A0, A1, CI;
3) as described Smux=0, Cmux=1, during Fmux=1, its mode of operation is input as A0, A1, A2, A3 for realizing 14 input logic;
4) as described Smux=1, Cmux=0, during Fmux=0, its mode of operation is two 3 input logics of realization for its mode of operation, the 1st 3 input logics are input as A0, A1, A2; The 2nd 3 input logics are input as A0, A3, A2;
5) as described Smux=1, Cmux=0, during Fmux=1, its mode of operation is input as A0, A1, CI, A3 for realizing 14 input logic;
6) as described Smux=1, Cmux=1, during Fmux=0, its mode of operation is for realizing the logic of two 3 inputs, the 1st 3 input logics are input as A0, A1, CI; The 2nd 3 input logics are input as A0, A3, CI;
7) as described Smux=1, Cmux=1, during Fmux=1, its mode of operation is input as A0, A1, CI, A3 for its mode of operation is to realize 14 input logic.
Further, in above-described embodiment, one of three input ports that the output after described A2 (0) selects through CMUX enters respectively C-LUT3 are: the output after A2 (0) selects through CMUX with CI (1) enters respectively one of three input ports of described C-LUT3; One of three input ports that output after described A2 (0) selects through CMUX enters respectively S-LUT3 are: the output after A2 (0) selects through CMUX with CI (1) enters respectively one of three input ports of described S-LUT3; Output port F4 from this LUT4 after the output of described S-LUT3 (0) is selected through F4MUX is output as: the output port F4 from this LUT4 after the output CO (1) of C-LUT3 and the output (0) of S-LUT3 are selected through F4MUX exports.
Four kinds of mode of operations that table 1 embodiment of the invention LUT4 is commonly used
Based on SMUX, the various combination mode of the control bit of CMUX and FMUX, this LUT4 can be configured to 8 kinds of patterns.Table 1 has provided four kinds of the most frequently used patterns of the present embodiment LUT4.
Pattern 1: use as a common LUT4, can realize the Boolean logic of any four inputs.For example we to realize one 4 the input with logic y=abcd, the SRAM memory cell of LUT4 configuration layer is configured to 80 (16 systems), then just can according to input obtain the correspondence with the result.
Pattern 2: as the Fast Carry Logic.LUT4 is configured to one-bit full addres,
With
The SRAM memory cell of logical block configuration layer is configured to 96E8 (16 system), the CI port is by the CO port driver of other logical blocks, replace I2 and enter two LUT3, sum logic and carry logic are finished by S-LUT3 and C-LUT3 respectively, input I3 does not enter LUT3 but removes to control F4MUX and makes SUM output, and the CO port is exported to the CI port of other logical blocks.Saved half area than realize one-bit full addres with traditional LUT4.
Mode 3: be used for entirely adding logic, during two addend lowest order additions, do not have the input of CI port this moment, therefore the CI port is not linked to each other with LUT3.
Pattern 4: be used for realizing multiplier logic.Under this pattern, two LUT3 can be by XB and XF simultaneously with I0﹠amp; I1, I2﹠amp; The result of I3 output, a LUT4 can obtain two partial products simultaneously, and then and a LUT4 combination that is operated under the pattern 2, partial product is cumulative, draw final multiplication result.Fig. 3 is the structural representation that is used for 5 transistor memory units of control bit storage information in the embodiment of the invention fpga logic unit.
In sum, the present embodiment LUT4 can realize the function of various modes flexibly in conjunction with follow-up every setting, has greatly improved logic density.But the LUT4 in the present embodiment can only realize combinational logic, and can not realize sequential logic.In order to realize sequential logic, need to introduce the trigger device, this will be problem to be solved in the fpga logic unit.
Two, fpga logic unit
Logical block is the minimum unit that is used for logic realization among the FPGA.The present embodiment discloses a kind of fpga logic unit.Fig. 2 is the logical construction schematic diagram of embodiment of the invention fpga logic unit.As shown in Figure 2, this fpga logic unit selects 1 multiplexer (BMUX, F5MUX, DMUX0 and DMUX1) to consist of by 2 of the LUT4 in an above-described embodiment, a D flip-flop and four responsible data flow selections.The port of logical block comprises data-in port (A0, A1, A2, A3, B, F5I), control inputs port (CE, SR), input end of clock mouth (CK), overall set-reset port (GSR), Carry Chains input port (CI), Carry Chains output port (CO) and data-out port (F4, XB, XF, XQ).
Wherein, this LUT4 selects multiplexer (FMUX, CMUX, SMUX and F4MUX) and two 3 LUT (C-LUT3 and S-LUT3) that input of 1 to consist of by four 2.Output after data-in port A0, A1 and A2 (0) and CI (1) select through CMUX enters respectively three input port A of C-LUT3, B, C.Output after data-in port A0, A1 (0) and A3 (1) tied SMUX and select and A2 (0) and CI (1) output after through the CMUX selection enters respectively three input port A of S-LUT3, B, C.Output after data input A3 and logic ' 0 ' are selected through FMUX enters the control port of F4MUX.The output port that is output as LUT4 after the output CO (1) of C-LUT3 and the output (0) of S-LUT3 are selected through F4MUX is F4.Fmux, Smux and Cmux are respectively FMUX, and the control port of SMUX and CMUX is 5 transistor memory units.
Wherein, the output port CO (0) of data-in port B (1) and C-LUT3 exports XB through behind the BMUX.The output port F4 (0) of data-in port F5I (1) and 4-LUT enters 1 input port of DMUX1 through the output behind the F5MUX, F4 enters 0 input port of DMUX1, and DMUX1 is output as XF.Output entered DFF data-in port D after XF (1) and B (0) selected through DMUX0.Bmux, Dmux1 and Dmux0 are respectively B5MUX, and the control port of DMUX1 and DMUX0 is 5 transistor memory units.Data-in port B is the control port of F5MUX.
Further, in the above-described embodiments, described CI is as the Carry Chains input port of described fpga logic unit; Described CO is as the Carry Chains output port of described fpga logic unit.In a lot of Logic applications a large amount of adder logic is arranged, such logical block just can both can realize the sum logic at one's own department or unit, can also provide carry for the addition of a high position, so the Fast Carry Logic was gushed out in actual applications very large.
The signal of table 2 embodiment of the invention fpga logic unit flows to
Wherein, this d type flip flop can be configured to dissimilar register or latch.The DFF port comprises data-in port D, control inputs port (CE, SR), input end of clock mouth (CK), overall set-reset port (GSR), data-out port (XQ).
Bypass input B listed by table 2 and LUT exports according to control bit Bmux, F5mux, and the unlike signal of the various combination of Dmux0 and Dmux1 polarity flows to.For example when Bmux=' 1 ' and Dmux0=' 1 ', XB is driven by B, and register input D is driven by LUT output.This signal flows to relevant with the realization of follow-up fpga logic piece, will describe in detail in subsequent embodiment.
The mode of operation of d type flip flop in table 3 embodiment of the invention fpga logic unit
Attention: the inner not band _ 1 of register element symbol (with F beginning) be just along triggering, band _ 1 be that negative edge triggers, the inner not band _ 1 of latch element symbol (with the L beginning) be that high level triggers, band _ 1 be that low level triggers.
Fig. 4 is the logical construction schematic diagram of d type flip flop in the embodiment of the invention fpga logic unit.With reference to Fig. 4, this d type flip flop comprises that core register and 42 select 1 multiplexer CKPOLMUX, SRSYNCMUX, SRSELMUX, QTYPEMUX is according to their control bit ckpol, srsync, srsel, the various combination of qtype, d type flip flop can be configured to dissimilar register or latch.This d type flip flop input comprises D (data input), CK (clock), and CE (clock enables), SR (set/reset) and GSR (overall set/reset) are output as Q (data output).SR (0) and logic ' 0 ' (1) are exported after selecting through SRSYNCMUX, and this output is carried out or logic with GSR, or the output of logic is respectively the set/reset end of core register through SRSELMUX output generation S (0) and R (1).CK (1) and～CK (0) selects to enter the CK end of core register through CKPOLMUX.The input QL (0) of core register and QF (1) select input Q through QTYPEMUX.
Table 3 is the mode of operation table of d type flip flop in the embodiment of the invention fpga logic unit.As shown in table 3, according to control bit ckpol, srsync, srsel, the various combination of qtype, d type flip flop can be configured to dissimilar register or latch.So just for the user provides very large flexibility, the user is according to the type that should be used for mask register of oneself, such as with the register of asynchronous set or with the register of synchronous set.
Control bit ckpol: different according to control bit ckpol polarity, d type flip flop can be configured to just trigger along triggering or negative edge, and such as the ckpol=' 1 ' of FD, along triggering, the ckpol=' 0 ' of FD_1 is for negative edge triggers for just.Two d type flip flops share a clock input in the logical block, and its polarity can be configured respectively.The CE signal is effectively high, and two shared clocks of D tentaculums enable in the logical block.If the d type flip flop that configures is not used CE, its default conditions are effectively, are defaulted as height such as the CE of FDC.
Control bit srsync:SR signal be high effectively, can be configured as synchronous or asynchronous according to the polarity of control bit srsync.
Control bit srsel: can be configured as set or reset according to control bit srsel, such as srsync=' 0 ' and the srsel=' 0 ' of FDCE, be the register that enables with asynchronous reset and clock.Two d type flip flops share the SR signal in the logical block.If the d type flip flop that the configures SR of using signal useless, its acquiescence attitude is invalid, is defaulted as low such as the SR of FDE.
Control bit qtype: the polarity according to control bit qtype can be configured to d type flip flop register or latch, such as the qtpye=' 0 ' of LD, is latch.
The advantage of the present embodiment fpga logic unit maximum can improve logic density exactly.And, through adding the multiplexer of d type flip flop and other four alternatives, having realized the sequential logic of fpga logic unit, can in logical block, be applied.
Three, fpga logic piece
The present embodiment discloses a kind of fpga logic piece.This logical block comprises: two fpga logic unit, fpga logic unit-first and the second fpga logic unit, local interlinkage and distributed RAM logics as describing among the above-mentioned embodiment.
Fig. 5 is embodiment of the invention fpga logic piece port distribution and schematic layout pattern.As shown in Figure 5, the port of this fpga logic piece comprises 2 overall input port-G＜1:0 〉, 12 input port-I＜11:0,8 output port-O＜7:0, Carry Chains input port-CI, Carry Chains output port-CO and 1 overall set-reset port-SR and 1 global write enable port-GWE.The logical block input/output port is evenly distributed on around the rectangle logical block, and the input/output port of logical block is connected to logical block input/output port of the same type all around equably, and these all are conducive to improve completion rate.
In the present embodiment fpga logic piece, local interlinkage comprises: being connected between logical block overall situation input port and logical block clock port and the control inputs port; Being connected between logical block input port and the logical block input port; Feedback link between logical block output port and the logical block data input port; Connection between logic ' 0 ' and logic ' 1 ' and the logical block input port; Being connected between logical block output port and the logical block output port.
Fig. 6 is the schematic diagram of embodiment of the invention fpga logic piece local interlinkage.
As shown in Figure 6, being connected between logical block overall situation input port and logical block clock port and the control inputs port comprises: overall input port G＜1〉directly link to each other overall input port G＜0 with the CK of two logical blocks〉control and can be connected with SR or CE by control bit.
As shown in Figure 6, being connected between logical block input port and the logical block input port comprises: data-in port I＜6 〉, I＜0 〉, I＜9, I＜3〉respectively with the data-in port A0 of the first fpga logic unit, A1, A2, A3 directly connects, I＜8 〉, I＜2 〉, I＜11 〉, I＜5 respectively with the A0 of the second fpga logic unit, A1, A2, A3 directly connects, I＜7〉directly be connected I＜1 with the B0 of the first fpga logic unit〉directly be connected with the B1 of the second fpga logic unit, I＜10〉directly be connected I＜4 with CE〉directly be connected with SR.
As shown in Figure 6, the logical block output port comprises with feedback link between the logical block data input port: output F4 in the first fpga logic unit directly is connected with the second fpga logic unit input F5i, and output F4 in the second fpga logic unit inputs F5i with the first fpga logic unit and directly is connected.
As shown in Figure 6, connection between logic ' 0 ' and logic ' 1 ' and the logical block input port comprises: logic ' 0 ' is connected with logic and 1 ' can be connected with the first fpga logic unit input B0, logic ' 0 ' is connected with logic and 1 ' can be connected with the second fpga logic unit input B1, logic ' 0 ' and logic ' 1 ' can with the common input CE of two logical blocks in the fpga logic piece, SR, CE connects.
As shown in Figure 6, being connected between logical block output port and the logical block output port comprises: output port O (0) is by output port XQ0 and the XB0 of the first logical block, the output port XF1 output of the second logical block, output port O (1) is by the output port XF0 of the first logical block, the output port XQ1 of the second logical block and XB1 output, output port O (2) is by the output port XQ0 of the first logical block, the output port XF1 output of the second logical block, output port O (3) is by output port XF0 and the XB0 of the first logical block, the output port XQ1 output of the second logical block, output port O (4) is by the output port XQ0 of the first logical block, the output port XF1 of the second logical block and XB1 output, output port O (5) is by the output port XF0 of the first logical block, the output port XQ1 output of the second logical block, output port O (6) is by the output port XQ0 of the first logical block, the output port XF1 output of the second logical block, output port O (7) is by the output port XF0 of the first logical block, and the output port XQ1 of the second logical block exports.
Fig. 7 is the building-block of logic of distributed RAM in the embodiment of the invention fpga logic piece.Two logical blocks of distributed RAM and fpga logic piece are shared data input A0[3:0], A1[3:0], B0, B1, SR, CK shares data output XF0 and XF1.This minute, face formula RAM mainly comprised SYN register, write control module, write multiplexer, read multiplexer.The data B0 that SYN register is used for writing synchronously and B1, address A0[3:0] and A1[3:0] and write control signal WE.Write the trend that control module is used for controlling data writing.Write multiplexer and be used for position with the memory cell of new data writing address appointment.Reading multiplexer is 4 input LUT of logical block in the fpga logic piece, so the time of reading is consistent with the transmission delay of LUT.Logical block has different mode of operations according to the difference of control bit (S1, S2, S3, D) polarity, and is as shown in table 4, and for example logical block is used as LUT when S1=' 0 ', and logical block is used as distributed RAM when S1=' 1 '.During control bit ramckpol=' 0 ', just along writing new data, during ramckpol=' 1 ', RAM writes new data in the clock negative edge to RAM at clock.
Fig. 8 is the connection diagram that embodiment of the invention fpga logic piece is realized the Fast Carry Logic logic.As shown in Figure 8, the CO port of each logical block directly links to each other with the CI port of the logical block of adjacent upside, the CO port of the second logical block directly links to each other with the CI port of bottom, adjacent right side logical block in the logical block of fpga chip top, just can form the Fast Carry Logic logic.
Fig. 9 is the connection diagram that embodiment of the invention fpga logic piece is realized the chain of registers logic.By-passing signal B directly passes logical block by XB when Bmux=' 1 '.When Dmux0=' 0 ', by-passing signal B enters register and exports by XQ, if XQ enters the identical adjacent logical block of configuration by B, has just formed chain of registers.Its purposes is quite extensive.The mode of operation that table 4 the present embodiment fpga logic piece is realized according to the setting of control bit
The mode of operation that table 4 is realized according to the setting of control bit for embodiment of the invention fpga logic piece.It can be configured to single port RAM and two-port RAM.A logical block can be configured to one 16 * 1, the single port RAM of (16 * 1) * 2,32 * 1 or one 's 16 * 1 two-port RAM.Single port RAM tool is with a synchronous write port and an asynchronous read port.Two-port RAM has a synchronous write port and two asynchronous read ports, and any read-write operation all can simultaneously or independently carry out.Utilize other logical blocks the distributed RAM of register read synchronously also can realize.
Be controlled by global write enable signal (GWE) and part and write enable signal (WE), the write operation of distributed RAM is clock along triggering, and just can be configured to along triggering or negative edge triggers.For RAM content after guaranteeing initialization is not damaged, be invalid at the layoutprocedure GWE of fpga chip.GWE was released after configuration finished.As GWE and WE simultaneously effectively the time, write into the selected memory cell in address at clock along new content.The time of reading of distributed RAM equals the logical transport time-delay of LUT.Distributed RAM content is initialised in the layoutprocedure of FPGA.FGPA chip one powers on, and all distributed ram memory cells are cleared, and then are written into the User Defined initial value.If the user is definition not, the acquiescence initial value is zero.
Single port RAM has three kinds of mode of operations: 16 * 1, and (16 * 1) * 2,32 * 1.16 * 1 patterns comprise one 16 ram memory cell array, and it comprises a decoder with 4 bit address, a data input and a data output.(16 * 1) * 2 pattern comprises two 16 ram memory cell array.Each array comprises a decoder with 4 bit address, a data input and a data output, and the read operation of these two arrays is independently.32 * 1 patterns comprise one 32 ram memory cell array, and it comprises a decoder with 5 bit address, a data input and a data output.
Signal source when table 5 works in LUT pattern and single port pattern ram for the fpga logic piece.Figure 10 embodiment of the invention fpga logic piece is as the logical construction schematic diagram of single port 32 * 1RAM.Chart 5 and shown in Figure 10, under this pattern, the bypass input B0 of LC0 inputs as data, and the bypass input B1 of the second logical block LC1 is as the 5th address bit in the fpga logic piece, and the SR signal uses as the WE signal.
Signal source when table 5FPGA logical block works in LUT pattern and single port pattern ram
| The RAM signal | Function | The LUT mode signal |
| DIN0 and DIN1 | The data input | B0 and B1 |
| A[3:0] | The address | A0[3:0] or A1[3:0] |
| A4 (only for 32 * 1) | The address | B1 |
| WE | Write and enable | SR |
| WCLK | Clock | CK |
| SPO | Single port output | XF0 or XF1 |
Dual-port 16 * 1RAM comprises two 16 ram memory cell arrays.Each port comprises 4 bit address decoders.A port has a data input and a data output, and another port comprises the data output by another group address appointment.
Signal source when table 6FPGA logical block works in LUT pattern and two-port RAM pattern
Signal source when table 6 works in LUT pattern and two-port RAM pattern for the fpga logic piece.Figure 11 is that embodiment of the invention fpga logic piece is as the logical construction schematic diagram of two-port RAM.Such as table 6 and shown in Figure 11, under this pattern, A0[3:0] be the read/write address of first port and the write address of second port, A1[3:0] be that the address is read in the special use of second port.Based on the ability that reads while write of two-port RAM, its data processing speed is more fast again than single port RAM.
The application of distributed RAM must be decided according to sequential requirement and resource utilization.16 * 1 RAM can cascade up and be formed on RAM storage array larger on the degree of depth and the width.Relatively disperse owing to forming the used logical block of jumbo RAM, will cause address wire to have large fan-out and long access time.A method that addresses this problem is to utilize the pipeline design, and output is deposited in data and address output, and it can improve operating frequency by the fan-out that reduces address wire.When distributed RAM was carried out logical mappings, control bit S1, S2, S3, D configured control circuit and are used for the transmission of data and address.Such as, by-passing signal B1 under single port (16 * 1) * 2 pattern as the data input, and under single port 32 * 1 patterns as the 5th address bit.Write MUX and be used for the defeated assigned address that transmits data to.As shown in figure 11, for keep the write capability of 5 transistor memory units, write enable nmos pass transistor M1 size must and the consistent size of the N-type transfer tube M2 of 5 transistor memory units.Read multiplexer and LUT pattern and share, so the logical time delay of the time of reading of distributed RAM and LUT is consistent.
In the fpga logic piece of the present invention, use the application of concentrating for storage resources can remedy the deficiency of memory module resource as distributed RAM LUT, and store the application of concentrating for low capacity and can improve resource utilization.The advantage of distributed RAM maximum is the time-delay that can shorten between storage and its driving logic, and this mainly is because logical block both can be used as logical resource and also can be used as storage resources.Because distributed two-port RAM has the asynchronous ability of reading, so the data processing speed of its twice can be saved a clock cycle.In a word, use LUT as distributed RAM, in the situation that the very little larger performance results of FGPA that exchanged for of area cost.
Four: the application that a plurality of logical blocks connect
The present embodiment has provided a plurality of logical blocks and has been connected to each other, and realizes the example of each function.Hereinafter having particular application as example with three describes.
1) when described fpga logic piece is realized the Fast Carry Logic logic: the carry input mouth CI of described fpga logic piece directly is connected with the carry input mouth CI of the first fpga logic unit, the carry output port CO of the first fpga logic unit directly is connected with the carry input mouth CI of the second fpga logic unit, and the carry output port CO of the second fpga logic unit is by the carry output port CO output of logical block;
2) when a plurality of logical block Combination application, the CO port of described fpga logic piece links to each other with the CI port of the fpga logic piece of adjacent top; The CO port of the PGA logical block on certain column logic block top links to each other with the CI port of the fpga logic piece of its adjacent columns bottom, the right;
3) when described fpga logic piece is realized the shift register chain logic, the logical block input port B directly or pass logical block output after being deposited, this output can be led to the input port B that wiring channel enters logical block in the logical block of right side.
As can be seen from the above-described embodiment: by said method, can realize the connection of a plurality of logical blocks, thereby realize complicated logic function.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (19)
1. an on-site programmable gate array FPGA logical block is characterized in that, this fpga logic unit comprises that 4 input look-up table LUT4, D flip-flop and four 2 select 1 multiplexer BMUX, F5MUX, DMUX0 and DMUX1;
Described D flip-flop comprises: data-in port D, data-out port XQ, control inputs port CE and SR, input end of clock mouth CK, overall set-reset port GSR;
The input port of described fpga logic unit comprises: the data-in port A0 of described LUT4, A1, A2, A3 and data-in port B, F5i; The output port of described fpga logic unit comprises: the data-out port F4 of described LUT4 and data-out port XB, XF, XQ;
Wherein, the output port CO (0) of data-in port B (1) and C-LUT3 exports XB through behind the BMUX; The output port F4 (0) of data-in port F5i (1) and LUT4 enters 1 input port of DMUX1 through the output behind the F5MUX, F4 enters 0 input port of DMUX1, and DMUX1 is output as XF; Output entered the data-in port D of D flip-flop after XF (1) and B (0) selected through DMUX0, and the output port of described D flip-flop is as the data-out port XQ of described fpga logic unit;
Bmux, Dmux1 and Dmux0 are respectively B5MUX, the control bit of DMUX1 and DMUX0;
Wherein, this LUT4 comprises: two 3 inputs look-up table LUT3 and four 2 select 1 multiplexer, and these two LUT3 are C-LUT3 and S-LUT3, and these four 2 are selected 1 multiplexer is FMUX, CMUX, SMUX and F4MUX; Data-in port A0, A1, and the output after A2 (0) the process CMUX selection enters respectively three input ports of C-LUT3; Output after data-in port A0, A1 (0) select through SMUX with A3 (1), and the output after A2 (0) the process CMUX selection enters respectively three input ports of S-LUT3; Output after data-in port A3 (1) and logic ' 0 ' are selected through FMUX enters the control port of F4MUX, and the output port F4 from this LUT4 after the output of S-LUT3 (0) is selected through F4MUX exports; Among the described LUT4, Fmux, Smux and Cmux are respectively described FMUX, the control bit of SMUX and CMUX; One of three input ports that output after described A2 (0) selects through CMUX enters respectively C-LUT3 are: the output after A2 (0) selects through CMUX with CI (1) enters respectively one of described three input ports of described C-LUT3; One of three input ports that output after described A2 (0) selects through CMUX enters respectively S-LUT3 are: the output after A2 (0) selects through CMUX with CI (1) enters respectively one of described three input ports of described S-LUT3; Output port F4 from this LUT4 after the output of described S-LUT3 (0) is selected through F4MUX is output as: the output port F4 from described LUT4 after the output CO (1) of C-LUT3 and the output (0) of S-LUT3 are selected through F4MUX exports.
2. fpga logic according to claim 1 unit is characterized in that,
Described CI is as the Carry Chains input port of described fpga logic unit; Described CO is as the Carry Chains output port of described fpga logic unit.
3. fpga logic according to claim 1 unit is characterized in that, described Fmux, and Smux, Cmux, Bmux, Dmux1 and Dmux0 are 5 transistor memory units.
4. fpga logic according to claim 1 and 2 unit is characterized in that, in the described fpga logic unit, and according to control bit Bmux, the various combination of Dmux1 and Dmux0, the signal that configures described fpga logic unit flows to:
Work as Bmux=0, F5mux=0, Dmux0=0, during Dmux1=0/1, described signal flows to as CO drives XB, and B drives D; Or
Work as Bmux=0, F5mux=0, Dmux0=1, during Dmux1=0/1, described signal flows to as CO drives XB, and LUT4 drives D; Or
Work as Bmux=0, F5mux=1, Dmux0=0, during Dmux1=0/1, described signal flows to as CO drives XB, and B drives D; Or
Work as Bmux=0, F5mux=1, Dmux0=1, during Dmux1=0/1, described signal flows to as CO drives XB, and LUT4 drives D; Or
Work as Bmux=1, F5mux=0, Dmux0=0, during Dmux1=0/1, described signal flows to as B drives XB, and B drives D; Or
Work as Bmux=1, F5mux=0, Dmux0=1, during Dmux1=0/1, described signal flows to as B drives XB, and LUT4 drives D; Or
Work as Bmux=1, F5mux=1, Dmux0=0, during Dmux1=0/1, described signal flows to as B drives XB, and B drives D; Or
Work as Bmux=1, F5mux=1, Dmux0=1, during Dmux1=0/1, described signal flows to as B drives XB, and LUT4 drives D.
5. fpga logic according to claim 1 and 2 unit is characterized in that, described d type flip flop comprises: core register and 42 select 1 multiplexer CKPOLMUX, SRSYNCMUX, SRSELMUX, QTYPEMUX;
This d type flip flop input comprises data input D, clock CK, and clock enables CE, and set/reset SR and overall set/reset GSR are output as data output Q;
Output after SR (0) and logic ' 0 ' (1) are selected through SRSYNCMUX, this output and GSR carry out or logic, output described or logic is exported through SRSELMUX and is produced S (0) and R (1), is respectively the set/reset end of core register;
CK (1) and～CK (0) selects to enter the CK end of core register through CKPOLMUX, the input QL (0) of core register and QF (1) select to input Q through QTYPEMUX;
Described 2 select 1 multiplexer CKPOLMUX, SRSYNCMUX, and SRSELMUX, the control bit of QTYPEMUX is respectively ckpol, srsync, srsel, qtype is according to control bit ckpol, srsync, srsel, the various combination of qtype, d type flip flop are configured to dissimilar register or latch.
6. fpga logic according to claim 5 unit is characterized in that, in the described d type flip flop,
According to control bit ckpol, d type flip flop is configured to just along triggering or the negative edge triggering; And/or
According to control bit srsync, d type flip flop is configured to synchronous or asynchronous; And/or
According to control bit srsel, d type flip flop is configured to set or resets; And/or
According to control bit qtype, d type flip flop is configured to register or latch.
7. a fpga logic piece is characterized in that, this logical block comprises: the first fpga logic unit, the second fpga logic unit, local interlinkage, and distributed RAM logic, wherein the first fpga logic unit and the second fpga logic unit are fpga logic as claimed in claim 1 or 2 unit;
The port of this fpga logic piece comprises 2 overall input port-G＜1:0 〉, 12 input port-I＜11:0,8 output port-O＜7:0, Carry Chains input port-CI, Carry Chains output port-CO and 1 overall set-reset port-SR and 1 global write enable port-GWE;
Described local interlinkage comprises: being connected between logical block overall situation input port and logical block clock port and the control inputs port; Being connected between logical block input port and the logical block input port; Feedback link between logical block output port and the logical block data input port; Connection between logic ' 0 ' and logic ' 1 ' and the logical block input port; Being connected between logical block output port and the logical block output port.
8. fpga logic piece according to claim 7, it is characterized in that: described distributed RAM logic comprises: SYN register, write control module, and write multiplexer, read multiplexer, two logical blocks of this distributed RAM and fpga logic piece are shared data input A0[3:0], A1[3:0], B0, B1, SR, CK shares data output XF0 and XF1;
The data that described SYN register is used for writing synchronously, address and write control signal; Describedly write the trend that control module is used for controlling data writing; The described multiplexer of writing is used for position with the memory cell of new data writing address appointment; Described read multiplexer be in the fpga logic piece logical block 4 the input LUT;
Opposed polarity according to control ramckpol, distributed RAM can be configured to clock just edge or negative edge data writing, control bit S1 with write enable signal WE respectively in writing control module through carrying out and logic with door WENAND0 and WENAND1, all enter with the output of logic and to write writing of multiplexer control data; Control bit S2 controls writing of data by control transmission gate S2PASS in writing control module; Control bit S3 controls the selection that S3MUX0 and S3MUX1 control write address in SYN register, and in writing control module and Din1orA4 be data input or the 5th address by carrying out controlling B1 with logic with door A4NAND; Control bit D controls the selection that DMUX controls write address in SYN register, and control transmission gate DPASS controls writing of data in writing control module; Control bit ramckpol controls RAMCKPOLMUX; Described fpga logic piece has different mode of operations according to the difference of control bit (S1, S2, S3, D) polarity.
9. fpga logic piece according to claim 7 is characterized in that:
Being connected between described logical block overall situation input port and logical block clock port and the control inputs port comprises: overall input port G＜1〉directly link to each other overall input port G＜0 with the CK of two logical blocks〉control and can be connected with SR or CE by control bit;
Being connected between logical block input port and the logical block input port comprises: data-in port I＜6 〉, I＜0 〉, I＜9 〉, I＜3〉respectively with the data-in port A0 of the first fpga logic unit, A1, A2, A3 directly connects, I＜8 〉, I＜2 〉, I＜11 〉, I＜5〉respectively with the A0 of the second fpga logic unit, A1, A2, A3 directly connects, I＜7〉directly be connected with the B0 of the first fpga logic unit, I＜1〉directly be connected I＜10 with the B1 of the second fpga logic unit〉directly be connected I＜4 with CE〉directly be connected with SR;
The logical block output port comprises with feedback link between the logical block data input port: output F4 in the first fpga logic unit directly is connected with the second fpga logic unit input F5i, and output F4 in the second fpga logic unit inputs F5i with the first fpga logic unit and directly is connected;
Connection between logic ' 0 ' and logic ' 1 ' and the logical block input port comprises: logic ' 0 ' is connected with logic and 1 ' can be connected with the first fpga logic unit input B0, logic ' 0 ' is connected with logic and 1 ' can be connected with the second fpga logic unit input B1, logic ' 0 ' and logic ' 1 ' can with the common input CE of two logical blocks in the fpga logic piece, SR, CE connects;
Being connected between logical block output port and the logical block output port comprises: output port O (0) is by output port XQ0 and the XB0 of the first fpga logic unit, the output port XF1 output of the second fpga logic unit, output port O (1) is by the output port XF0 of the first fpga logic unit, the output port XQ1 of the second fpga logic unit and XB1 output, output port O (2) is by the output port XQ0 of the first fpga logic unit, the output port XF1 output of the second fpga logic unit, output port O (3) is by output port XF0 and the XB0 of the first fpga logic unit, the output port XQ1 output of the second fpga logic unit, output port O (4) is by the output port XQ0 of the first fpga logic unit, the output port XF1 of the second fpga logic unit and XB1 output, output port O (5) is by the output port XF0 of the first fpga logic unit, the output port XQ1 output of the second fpga logic unit, output port O (6) is by the output port XQ0 of the first fpga logic unit, the output port XF1 output of the second fpga logic unit, output port O (7) is by the output port XF0 of the first fpga logic unit, and the output port XQ1 of the second fpga logic unit exports.
10. fpga logic piece according to claim 8 is characterized in that: in this fpga logic piece,
S1=0; S2=0; S3=0; During D=0, the mode of operation of described logical block is LUT; Or
S1=1; S2=0; S3=0; During D=0, the mode of operation of described logical block is single port 16 * 1RAM; Or
S1=1; S2=1; S3=0; During D=0, the mode of operation of described logical block is single port (16 * 1) * 2RAM; Or
S1=1; S2=0; S3=1; During D=0, the mode of operation of described logical block is single port 32 * 1RAM; Or
S1=1; S2=0; S3=0; During D=1, the mode of operation of described logical block is dual-port 16 * 1RAM.
11. fpga logic piece according to claim 10 is characterized in that: when the mode of operation of described logical block is single port 16 * 1RAM, single port (16 * 1) * 2RAM, when single port 32 * 1RAM or dual-port 16 * 1RAM:
During ramckpol=' 0 ', just along writing new data, during ramckpol=' 1 ', RAM writes new data in the clock negative edge to RAM at clock.
12. fpga logic piece according to claim 11, it is characterized in that: when the mode of operation of described fpga logic piece is described single port 16 * 1RAM, single port (16 * 1) * 2RAM, single port 32 * 1RAM, GWE is the global write enable signal of distributed RAM
The RAM signal is DIN0 and DIN1; Function is the data inputs; The logical block signal is B0 and B1;
The RAM signal is A[3:0]; Function is the address; The logical block signal is A0[3:0] or A1[3:0];
The RAM signal is the A4 for 32 * 1; Function is the address; The logical block signal is B1;
The RAM signal is WE; Function enables for writing; The logical block signal is SR;
The RAM signal is WCLK; Function is clock; The logical block signal is CK;
The RAM signal is SPO; Function is single port output; The logical block signal is XF0 or XF1.
13. fpga logic piece according to claim 10 is characterized in that: when the mode of operation of described fpga logic piece is described dual-port 16 * 1RAM:
The RAM signal is DIN; Function is the data inputs; The logical block signal is B0;
The RAM signal is A[3:0]; Function is that single port RAM reads address or single two-port RAM write address; The logical block signal is A0[3:0];
The RAM signal is DPRA[3:0]; Function is the two-port RAM write address; The logical block signal is A1[3:0];
The RAM signal is WE; Function enables for writing; The logical block signal is SR;
The RAM signal is WCLK; Function is clock; The logical block signal is CK;
The RAM signal is SPO; Function is single port RAM output; The logical block signal is XF0;
The RAM signal is DPO; Function is two-port RAM output; The logical block signal is XF1.
14. fpga logic piece according to claim 10 is characterized in that, when the mode of operation of described fpga logic piece is LUT4:
The output port F4 of the first fpga logic unit directly is connected with the second fpga logic unit input F5i, and the output port F4 of the second fpga logic unit directly is connected with the input F5i of the first fpga logic unit.
15. each described fpga logic piece according to claim 7-14, it is characterized in that: the local interlinkage of fpga logic piece inside all adopts the part interconnection pattern and is equally distributed, fpga logic piece input/output port is evenly distributed on around the logical block, and the input/output port of fpga logic unit is connected to fpga logic piece input/output port of the same type all around equably.
16. each described fpga logic piece according to claim 7-14 is characterized in that: CK, CE and SR port are shared in described the first fpga logic unit and the second fpga logic unit.
17. fpga logic piece according to claim 7 is characterized in that: when described fpga logic piece is realized the Fast Carry Logic logic:
The carry input mouth CI of described fpga logic piece directly is connected with the carry input mouth CI of the first fpga logic unit, the carry output port CO of the first fpga logic unit directly is connected with the carry input mouth CI of the second fpga logic unit, and the carry output port CO of the second fpga logic unit is by the carry output port CO output of logical block.
18. fpga logic piece according to claim 17 is characterized in that: the CO port of described fpga logic piece links to each other with the CI port of adjacent fpga logic piece; And/or the CO port of the CI port of described fpga logic piece fpga logic piece adjacent with another links to each other.
19. fpga logic piece according to claim 7 is characterized in that: when described fpga logic piece was realized the shift register chain logic, the logical block input port B directly or after being deposited was passed logical block.
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| US9287868B1 (en) * | 2014-08-27 | 2016-03-15 | Quicklogic Corporation | Logic cell for programmable logic device |
| CN106133838B (en) * | 2014-12-30 | 2019-01-22 | 京微雅格（北京）科技有限公司 | A kind of expansible configurable FPGA storage organization and FPGA device |
| CN106815381B (en) * | 2015-11-30 | 2019-10-18 | 中国科学院电子学研究所 | The mapping method of logical node in sparse look-up table and FPGA |
| CN108153549B (en) * | 2017-12-13 | 2020-08-28 | 京微齐力(北京)科技有限公司 | FPGA chip of distributed multi-functional-layer structure |
| CN108182303B (en) | 2017-12-13 | 2020-08-28 | 京微齐力(北京)科技有限公司 | Programmable device structure based on mixed function memory unit |
| CN109714042A (en) * | 2018-11-16 | 2019-05-03 | 京微齐力(北京)科技有限公司 | A kind of multiplexing method of look-up table |
| CN113971159B (en) * | 2021-10-28 | 2024-02-20 | 山东芯慧微电子科技有限公司 | Programmable logic block based on improved lookup table structure |
| CN114859218B (en) * | 2022-03-16 | 2023-06-23 | 厦门智多晶科技有限公司 | Detection circuit and detection method for lookup table in FPGA chip |
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