CN112926281A - Intelligent module analysis method of digital integrated circuit - Google Patents
Intelligent module analysis method of digital integrated circuit Download PDFInfo
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Abstract
The invention discloses an intelligent module analysis method of a digital integrated circuit, which comprises the following steps: s10, performing preliminary arrangement on the original netlist; s20, for the modules, calculating a correlation coefficient between the modules: traversing all current modules, sequentially selecting one module M, and calculating the correlation coefficient of the module M and each other module; s30, selecting a module, and searching whether the maximum matching item meets the merging condition; s40, if yes, merging the modules; s50, if not, judging whether the module is the last module; s60, if the module is the last module, judging whether the preset sorting requirement is met, if so, ending; otherwise, returning to S20; not the last module, return to S30. The invention analyzes the digital circuit netlist, intelligently arranges the devices into different modules by analyzing the interrelation among the devices in the netlist, and can greatly improve the analysis and arrangement efficiency of the digital circuit netlist.
Description
Technical Field
The invention belongs to the field of electronic circuits, and particularly relates to an intelligent module analysis method of a digital integrated circuit.
Background
In the inverse analysis technique of integrated circuits, the analysis and sorting of digital circuits is an important branch. With the improvement of the production process of the integrated circuit, the number of devices integrated in a chip is increased exponentially, and higher requirements are provided for circuit analysis and arrangement.
In the forward design of an integrated circuit, an engineer divides modules according to design requirements, referring to fig. 1, into modules 1-5, respectively describes functions of the relevant modules by using a high-level hardware description language, and then obtains a final device layout after processing by integrating, laying out and routing tool software.
The reverse analysis is a completely reverse process, and an engineer firstly faces a cobweb-like huge and disordered device network, see fig. 2, and is only a part of a device netlist, and then understands the relationship and the application of the devices little by little through combing, and finally divides the devices into different modules layer by layer according to functions. Usually, an engineer needs to sort and modularize devices according to his own experience, and the process of sorting modules is a process of understanding a netlist step by step while understanding sorting. This manual analysis process is not only time consuming, but also very demanding on the ability of the engineer. Sometimes, the connection relationship of the devices is particularly complex, even the engineers are led to be on the spot and spend a lot of time and are difficult to be inched.
Disclosure of Invention
In view of the technical problems, the invention is used for providing a method for analyzing a digital circuit netlist, intelligently arranging the devices into different modules by analyzing the interrelation among the devices in the netlist, and greatly improving the analysis and arrangement efficiency of the digital circuit netlist.
The following technical scheme is adopted:
s10, preliminary arrangement of the original netlist: devices in the digital circuit netlist are divided into combinational logic devices, triggers and latches, and according to the device types, the most initial module combination is carried out on the strongly related devices;
s20, for the modules, calculating a correlation coefficient between the modules: traversing all current modules, sequentially selecting one module M, and calculating the correlation coefficient of the module M and each other module;
s30, selecting a module, and searching whether the maximum matching item meets the merging condition;
s40, if yes, merging the modules;
s50, if not, judging whether the module is the last module;
s60, if the module is the last module, judging whether the preset sorting requirement is met, if so, ending; otherwise, returning to S20;
if not, return to S30;
the same procedure as above is also applied to the device in S20.
Preferably, the preliminary collation of the original netlist comprises the following steps:
s11, traversing all combinational logic devices in the netlist, and merging all combinational logic cones into an independent module;
and S12, traversing all the network wires in the netlist, analyzing a device list driven by the network wires, namely analyzing all the devices with one or more input pins connected to the network wires, and combining the driven devices into an independent module if the devices driven by the network wires are the same type of device and the number of the devices is less than a preset value.
Preferably, the correlation coefficient between the calculation modules is a correlation coefficient calculation formula of one module M and another module S:
CMS＝KMS_Inputs×CMS_Inputs+KMS_Outputs×CMS_Outputs+KSM_Outputs×CSM_Outputs；
wherein, KMS_Inputs、KMS_Outputs、KSM_OutputsThree preset constants are used for adjusting the weights of different correlation coefficients;
the method comprises the following steps:
s21, inputting a correlation coefficient CMS_InputsReflecting the correlation degree of the input pins of the two modules, traversing all the input pins, and calculating a correlation value V for the network cables simultaneously input into one module M and the other module Snet_inputAnd accumulated to the input correlation coefficient CMS_Inputs；
Vnet_input(number of net load devices in M + number of net load devices in S)/number of net total load devices)/number of M input pins;
s22, outputting the correlation coefficient CMS_OutputsReaction-dieThe correlation degree between the output pins of the block M and the input pins of the other module S, and the correlation value V is calculated by traversing all the output pins of one module M, corresponding to the network cables connected to the input pins of the other module Snet_outputAnd accumulated to an output correlation coefficient CMS_Outputs；
Vnet_output(number of net load devices in M + number of net load devices in S)/number of net total load devices)/number of M output pins;
s23, outputting the correlation coefficient CSM_OutputsReflecting the correlation degree between the output pin of another module S and the input pin of a module M, traversing all the output pins of another module S, correspondingly connecting to the network cable of the input pin of a module M, and calculating the correlation value Vnet_outputAnd accumulated to an output correlation coefficient CSM_Outputs；
Vnet_output(number of net load devices in S + number of net load devices in M)/total number of net load devices)/number of S output pins.
Preferably, the selecting one module searches whether the maximum matching item meets the merging condition, and selects another module S with the highest correlation coefficient for traversing the correlation coefficient list of one module M; searching a correlation coefficient list of another module S, and judging whether the module M has the highest correlation coefficient or the highest sum of the correlation coefficients; the method is also consistent with the above determination method for the device.
Preferably, the merging module performs pre-merging first, and performs formal merging after the pre-merging is passed; the reasons for the failure of pre-merging include the excessive number of devices after merging or the excessive reduction of the module efficiency factor after merging, wherein the module efficiency factor is the sum of the number of module devices divided by the number of module input/output pins.
The invention has the following beneficial effects: the method completely fills the blank of analysis and arrangement of the combinational logic loop in the current digital circuit netlist, and the current industry is basically completely dependent on manual processing aiming at the lack of an automatic processing method of the combinational logic loop, or the manual logic analysis is simplified, or the manual constraint processing is not needed, so that great obstacles are caused to the analysis work of the digital circuit netlist. The method is realized by a programming method, so that the manual workload of an integrated circuit reverse analysis engineer can be greatly reduced, and the speed and the accuracy of processing the combinational logic loop are improved.
The invention provides an intelligent module analysis method of a digital integrated circuit in the digital integrated circuit, which is characterized in that the original digital netlist is initially sorted, and initial combination is carried out according to the device type and the basic connection relation; traversing the modules/devices in the initially sorted netlist, calculating the correlation coefficient between every two modules/devices, and judging whether a proper merging target exists or not according to the correlation coefficient; and combining the modules/devices which meet the judgment condition until the netlist arrangement meets the preset requirement. Compared with the analysis and arrangement method in the prior art, the method has at least the following advantages:
1. by a programming method, initially numerous and jumbled and disordered devices are continuously intelligently merged according to the algorithm and automatically grown into modules with reasonable functions;
2. the traditional manual work of understanding first and finishing later is changed into the manual work of finishing first and finishing later, so that the workload of engineers is greatly reduced.
Drawings
FIG. 1 is a block diagram of a prior art digital integrated circuit partitioning module;
FIG. 2 is a schematic diagram of a prior art device network;
FIG. 3 is a flowchart illustrating the steps of a method for intelligent module analysis of a digital integrated circuit according to an embodiment of the present invention;
FIG. 4 shows the correlation coefficient C of the S21 input of the intelligent module analysis method of the digital integrated circuit according to the embodiment of the present inventionMS_InputsTraversing the schematic diagram;
FIG. 5 shows the correlation coefficient C output from S22 in the method for analyzing the intelligent module of the digital integrated circuit according to the embodiment of the present inventionMS_OnputsAnd traversing the schematic diagram.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
Referring to fig. 3, the present invention discloses an intelligent module analysis method of a digital integrated circuit,
the method comprises the following steps:
s10, preliminary arrangement of the original netlist: devices in the digital circuit netlist are divided into combinational logic devices, triggers and latches, and according to the device types, the most initial module combination is carried out on the strongly related devices;
s20, for the modules, calculating a correlation coefficient between the modules: traversing all current modules, sequentially selecting one module M, and calculating the correlation coefficient of the module M and each other module;
s30, selecting a module, and searching whether the maximum matching item meets the merging condition;
s40, if yes, merging the modules;
s50, if not, judging whether the module is the last module;
s60, if the module is the last module, judging whether the preset sorting requirement is met, if so, ending; otherwise, returning to S20;
if not, return to S30;
the same procedure as above is also applied to the device in S20.
Specific embodiment of S10
In the preliminary arrangement of the original netlist, appropriate parameters need to be selected according to specific project conditions in combination, the obtained result is not necessarily an optimal solution, and the processing time of a subsequent algorithm can be greatly saved. The subsequent processing time is proportional to the square of the number of modules or devices, and the number of modules or devices is usually less than one third of the original netlist after the preliminary arrangement, so that the time saving is very remarkable.
The method specifically comprises the following steps:
s11, traversing all combinational logic devices in the netlist, and merging all combinational logic cones into an independent module; the combinational logic cone refers to a group of combinational logic devices, after the combinational logic cone is combined into a module, the output of the module is the output of one of the combinational logic devices (which may be a single pin or a plurality of pins), and the outputs of other combinational logic devices are directly or indirectly connected to the input of the combinational logic device and are not connected with any other device outside the module.
And S12, traversing all the network wires in the netlist, analyzing a device list driven by the network wires, namely analyzing all the devices with one or more input pins connected to the network wires, and combining the driven devices into an independent module if the devices driven by the network wires are the same type of device and the number of the devices is less than a preset value.
Specific embodiment of S20
Calculating the correlation coefficient between the modules, which is a correlation coefficient calculation formula of one module M and the other module S:
CMS＝KMS_Inputs×CMS_Inputs+KMS_Outputs×CMS_Outputs+KSM_Outputs×CSM_Outputs；
wherein, KMS_Inputs、KMS_Outputs、KSM_OutputsThree preset constants are used for adjusting the weights of different correlation coefficients;
the method comprises the following steps:
s21, inputting a correlation coefficient CMS_InputsReflecting the correlation degree of the input pins of the two modules, traversing all the input pins, and calculating a correlation value V for the network cables simultaneously input into one module M and the other module Snet_inputAnd accumulated to the input correlation coefficient CMS_Inputs；
Vnet_input(number of net load devices in M + number of net load devices in S)/number of net total load devices)/number of M input pins;
referring to fig. 4, in the n input network lines of the module M, input 1, input 2, etc. are simultaneously input into the module S. These nets may also be simultaneously input to other modules or devices X1-Xj, Y1-Yj.
S22, outputting the correlation coefficient CMS_OutputsReflecting the correlation degree of the output pin of one module M and the input pin of the other module S, traversing all the output pins of one module M, correspondingly connecting to the network cable of the input pin of the other module S, and calculating a correlation value Vnet_outputAnd accumulated to an output correlation coefficient CMS_Outputs；
Vnet_output(number of net load devices in M + number of net load devices in S)/number of net total load devices)/number of M output pins;
referring to fig. 5, of the n output network lines of the module M, output 1, output 2, etc. are input to the module S. These nets may also be simultaneously input to other modules or devices X1-Xj, Y1-Yj.
S23, outputting the correlation coefficient CSM_OutputsReflecting the correlation degree between the output pin of another module S and the input pin of a module M, traversing all the output pins of another module S, correspondingly connecting to the network cable of the input pin of a module M, and calculating the correlation value Vnet_outputAnd accumulated to an output correlation coefficient CSM_Outputs；
Vnet_output(number of net load devices in S + number of net load devices in M)/total number of net load devices)/number of S output pins.
Specific embodiment of S30
Selecting one module, searching whether the maximum matching item meets the merging condition, traversing a correlation coefficient list of one module M, and selecting another module S with the highest correlation coefficient; searching a correlation coefficient list of another module S, and judging whether the module M has the highest correlation coefficient or the highest sum of the correlation coefficients; the method is also consistent with the above determination method for the device.
Specific embodiment of S40
The merging module is used for performing pre-merging firstly and performing formal merging after the pre-merging is passed; the reasons for the failure of pre-merging include the excessive number of devices after merging or the excessive reduction of the module efficiency factor after merging, wherein the module efficiency factor is the sum of the number of module devices divided by the number of module input/output pins.
S50, if the last module or device is not judged, the steps S30-S40 are repeated until all modules or devices are traversed. At this time, after a period of searching and merging of the modules or devices, the number of the modules or devices is reduced, and if the preset sorting requirement is met, for example, the number of the top module/device is less than a certain value, the netlist sorting is finished; otherwise, continuously repeating the steps S20-S40 until the preset sorting requirement is met.
The method provided by the invention completely fills the blank of analyzing and sorting the current digital circuit netlist. Currently, in the industry, an automated processing method is lacked for digital circuit arrangement, and the processing is basically completely performed by manpower, and the arrangement is performed while understanding, or the arrangement is performed after understanding, so that a lot of time is consumed, and the processing is also required to be repeated continuously. The method is realized by a programming method, a large amount of data analysis is utilized to intelligently arrange the modules in advance, and an engineer understands the netlist by contrasting the modules. The working mode of sorting and understanding can greatly reduce the manual workload of reverse analysis engineers of the integrated circuit and improve the efficiency and quality of digital circuit analysis and sorting.
It is to be understood that the exemplary embodiments described herein are illustrative and not restrictive. Although one or more embodiments of the present invention have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.
Claims (5)
1. An intelligent module analysis method of a digital integrated circuit is characterized by comprising the following steps:
s10, preliminary arrangement of the original netlist: devices in the digital circuit netlist are divided into combinational logic devices, triggers and latches, and according to the device types, the most initial module combination is carried out on the strongly related devices;
s20, for the modules, calculating a correlation coefficient between the modules: traversing all current modules, sequentially selecting one module M, and calculating the correlation coefficient of the module M and each other module;
s30, selecting a module, and searching whether the maximum matching item meets the merging condition;
s40, if yes, merging the modules;
s50, if not, judging whether the module is the last module;
s60, if the module is the last module, judging whether the preset sorting requirement is met, if so, ending; otherwise, returning to S20;
if not, return to S30;
the same procedure as above is also applied to the device in S20.
2. A method for intelligent block analysis of a digital integrated circuit as recited in claim 1, wherein the preliminary refinement of the original netlist comprises the steps of:
s11, traversing all combinational logic devices in the netlist, and merging all combinational logic cones into an independent module;
and S12, traversing all the network wires in the netlist, analyzing a device list driven by the network wires, namely analyzing all the devices with one or more input pins connected to the network wires, and combining the driven devices into an independent module if the devices driven by the network wires are the same type of device and the number of the devices is less than a preset value.
3. The intelligent module analysis method of a digital integrated circuit according to claim 1, wherein the correlation coefficient between the calculation modules is a correlation coefficient calculation formula of one module M and another module S:
CMS＝KMS_Inputs×CMS_Inputs+KMS_Outputs×CMS_Outputs+KSM_Outputs×CSM_Outputs；
wherein, KMS_Inputs、KMS_Outputs、KSM_OutputsThree preset constants are used for adjusting the weights of different correlation coefficients;
the method comprises the following steps:
s21, input phaseCoefficient of correlation CMS_InputsReflecting the correlation degree of the input pins of the two modules, traversing all the input pins, and calculating a correlation value V for the network cables simultaneously input into one module M and the other module Snet_inputAnd accumulated to the input correlation coefficient CMS_Inputs；
Vnet_input(number of net load devices in M + number of net load devices in S)/number of net total load devices)/number of M input pins;
s22, outputting the correlation coefficient CMS_OutputsReflecting the correlation degree of the output pin of one module M and the input pin of the other module S, traversing all the output pins of one module M, correspondingly connecting to the network cable of the input pin of the other module S, and calculating a correlation value Vnet_outputAnd accumulated to an output correlation coefficient CMS_Outputs；
Vnet_output(number of net load devices in M + number of net load devices in S)/number of net total load devices)/number of M output pins;
s23, outputting the correlation coefficient CSM_OutputsReflecting the correlation degree between the output pin of another module S and the input pin of a module M, traversing all the output pins of another module S, correspondingly connecting to the network cable of the input pin of a module M, and calculating the correlation value Vnet_outputAnd accumulated to an output correlation coefficient CSM_Outputs；
Vnet_output(number of net load devices in S + number of net load devices in M)/total number of net load devices)/number of S output pins.
4. The method of claim 1, wherein said selecting one module, looking up whether its largest matching term satisfies the merging condition, for traversing the correlation coefficient list of one module M, selecting another module S with the highest correlation coefficient; searching a correlation coefficient list of another module S, and judging whether the module M has the highest correlation coefficient or the highest sum of the correlation coefficients; the method is also consistent with the above determination method for the device.
5. The method as claimed in claim 1, wherein the merging module performs pre-merging first, and performs formal merging after the pre-merging is passed; the reasons for the failure of pre-merging include the excessive number of devices after merging or the excessive reduction of the module efficiency factor after merging, wherein the module efficiency factor is the sum of the number of module devices divided by the number of module input/output pins.
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