CN107863958A - A kind of conversion method of conventional logic gates - Google Patents
A kind of conversion method of conventional logic gates Download PDFInfo
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- CN107863958A CN107863958A CN201710880132.1A CN201710880132A CN107863958A CN 107863958 A CN107863958 A CN 107863958A CN 201710880132 A CN201710880132 A CN 201710880132A CN 107863958 A CN107863958 A CN 107863958A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- G—PHYSICS
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- G06F30/30—Circuit design
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Abstract
The present invention relates to a kind of conversion method of conventional logic gates, belong to Digital Electronic Technique field.The NOT gate of the conventional logic gates of the present invention, with door, OR gate, nor gate, XOR gate, respectively converted by using one or several NAND gates with OR gate.The present invention commonly uses the conversion method of gate circuit by designing, and can make full use of resources of chip, and processing can be replaced with other chips in time in a certain chip shortage, so as to improve resource utilization, and being capable of flexible design circuit.
Description
Technical field
The present invention relates to a kind of conversion method of conventional logic gates, belong to Digital Electronic Technique field.
Background technology
, it is necessary to which the logical function of complexity is converted into specifically in integrated circuit design process in Digital Electronic Technique
Digital circuit, the logic circuit generally applied to have with door, NOT gate, NAND gate, OR gate, nor gate, XOR gate, with OR gate seven
Kind, include multigroup gate circuit inside each logic circuit chip, during a variety of gate circuit Combination Designs, the gate circuit of segment chip
It can not be fully utilized, the wasting of resources can be caused, in addition, when needing to use one of which gate circuit, but can not find, now
Can constructs urgent need using gate circuit conversion method of the present invention.
The content of the invention
The technical problem to be solved in the present invention is：The present invention provides a kind of conversion method of conventional logic gates, passes through
The conversion method of the conventional gate circuit of design, can make full use of resources of chip, it can be used in time in a certain chip shortage
He replaces processing by chip, so as to improve resource utilization, and being capable of flexible design circuit.
The technical scheme is that：A kind of conversion method of conventional logic gates, the NOT gate of conventional logic gates,
With door, OR gate, nor gate, XOR gate, respectively converted by using one or several NAND gates with OR gate.
The conversion method of one NOT gate is：One NOT gate is equivalent to by a NAND gate V two inputs
A, formed after B connections.
Conversion method described in one with door is：Described in one with door by two NAND gates converted, the NAND gate
V1 two inputs A1, B1 are connected to NAND gate V2 two inputs simultaneously as input, NAND gate V1 output end Y1
A2, B2 are held, NAND gate V2 output end Y2 is as output end.
The conversion method of one OR gate is：One OR gate is converted by three NAND gates, the NAND gate
V1 two inputs A1, B1 connection, its output end Y1 are connected to NAND gate V3 input A3, NAND gate V2 two inputs
A2, B2 connection are held, its output end Y2 is connected to NAND gate V3 input B3, and NAND gate V3 output end Y3 is as output end.
The conversion method of one nor gate is：One nor gate is converted by four NAND gates, it is described with
NOT gate V1 two inputs A1, B1 connection, NAND gate V2 two inputs A2, B2 connection, the output end of NAND gate V1, V2
Y1, Y2 respectively connected NAND gate V3 input A3, B3, NAND gate V3 output end two inputs with NAND gate V4 simultaneously
A4, B4 connection are held, NAND gate V4 output end Y4 is as output end.
The conversion method of one XOR gate is：One XOR gate is converted by 5 NAND gates, NAND gate V1
Two inputs A1, B1 connection after be connected to NAND gate V4 input A4, NAND gate V2 two inputs A2, B2 connection
NAND gate V3 input B3 is connected to afterwards, and output end Y1, Y2 of NAND gate V1, V2 respectively connected the defeated of NAND gate V3, V4
Enter and hold A3, B4, output end Y3, Y4 of NAND gate V3, V4 respectively connected NAND gate V5 input A5, B5, NAND gate V5's
Output end Y5 is as output end.
The conversion method of one same OR gate is：One same OR gate is converted by 5 NAND gates, it is described with it is non-
Door V2 input A2 is connected to NAND gate V1 two inputs A1, B1 simultaneously, and NAND gate V2 input B2 is connected simultaneously
NAND gate V3 two inputs A3, B3, output end Y1, Y3 of NAND gate V1, V3 respectively connected NAND gate V4 input
A4, B4 are held, output end Y2, Y4 of NAND gate V2, V4 respectively connected NAND gate V5 two inputs A5, B5, NAND gate V5
Output end Y5 as output end.
The beneficial effects of the invention are as follows：The present invention commonly uses the conversion method of gate circuit by designing, and can make full use of core
Piece resource, processing can be replaced with other chips in time in a certain chip shortage, so as to improve resource utilization, and energy
Enough flexible design circuits.
Brief description of the drawings
Fig. 1 is the not circuit schematic diagram that the present invention is formed；
Fig. 2 be the present invention form with gate circuit schematic diagram；
Fig. 3 is the OR circuit schematic diagram that the present invention is formed；
Fig. 4 is the OR-NOT circuit schematic diagram that the present invention is formed；
Fig. 5 is the NOR gate circuit schematic diagram that the present invention is formed；
Fig. 6 is the same OR circuit schematic diagram that the present invention is formed.
Embodiment
Below in conjunction with the accompanying drawings and specific embodiment, the invention will be further described.
Embodiment 1：As shown in figures 1 to 6, a kind of conversion method of conventional logic gates, conventional logic gates it is non-
Door, with door, OR gate, nor gate, XOR gate, respectively converted by using one or several NAND gates with OR gate.
The conversion method of one NOT gate is：One NOT gate is equivalent to by a NAND gate V two inputs
A, formed after B connections.
Conversion method described in one with door is：Described in one with door by two NAND gates converted, the NAND gate
V1 two inputs A1, B1 are connected to NAND gate V2 two inputs simultaneously as input, NAND gate V1 output end Y1
A2, B2 are held, NAND gate V2 output end Y2 is as output end.
The conversion method of one OR gate is：One OR gate is converted by three NAND gates, the NAND gate
V1 two inputs A1, B1 connection, its output end Y1 are connected to NAND gate V3 input A3, NAND gate V2 two inputs
A2, B2 connection are held, its output end Y2 is connected to NAND gate V3 input B3, and NAND gate V3 output end Y3 is as output end.
The conversion method of one nor gate is：One nor gate is converted by four NAND gates, it is described with
NOT gate V1 two inputs A1, B1 connection, NAND gate V2 two inputs A2, B2 connection, the output end of NAND gate V1, V2
Y1, Y2 respectively connected NAND gate V3 input A3, B3, NAND gate V3 output end two inputs with NAND gate V4 simultaneously
A4, B4 connection are held, NAND gate V4 output end Y4 is as output end.
The conversion method of one XOR gate is：One XOR gate is converted by 5 NAND gates, NAND gate V1
Two inputs A1, B1 connection after be connected to NAND gate V4 input A4, NAND gate V2 two inputs A2, B2 connection
NAND gate V3 input B3 is connected to afterwards, and output end Y1, Y2 of NAND gate V1, V2 respectively connected the defeated of NAND gate V3, V4
Enter and hold A3, B4, output end Y3, Y4 of NAND gate V3, V4 respectively connected NAND gate V5 input A5, B5, NAND gate V5's
Output end Y5 is as output end.
The conversion method of one same OR gate is：One same OR gate is converted by 5 NAND gates, it is described with it is non-
Door V2 input A2 is connected to NAND gate V1 two inputs A1, B1 simultaneously, and NAND gate V2 input B2 is connected simultaneously
NAND gate V3 two inputs A3, B3, output end Y1, Y3 of NAND gate V1, V3 respectively connected NAND gate V4 input
A4, B4 are held, output end Y2, Y4 of NAND gate V2, V4 respectively connected NAND gate V5 two inputs A5, B5, NAND gate V5
Output end Y5 as output end.
The present invention operation principle be：
A, NOT gate：Input A, B in NAND gate V connect be equal to two inputs input signal it is consistent, i.e., such as table 1
The truth table of not circuit conversion is shown, during input A, B input low level signal, output end Y output high level signals are defeated
When entering to hold A, B input high level signal, output end Y output low level signals；
B, and door：It is the truth table with gate circuit conversion as shown in table 2, when NAND gate V1 input A1, B1 input low level
During signal, its output end Y1 output high level signals, NAND gate V2 two inputs A2, B2 while input high level signal,
Its output end Y2 exports low level signal；
When NAND gate V1 input A1 input low level signals, its input B1 input high level signals, its output end Y1
High level signal is exported, input high level signal, its output end Y2 export low electricity simultaneously by NAND gate V2 two inputs A2, B2
Ordinary mail number；
When NAND gate V1 input A1 input high level signals, its input B1 input low level signals, its output end Y1
High level signal is exported, input high level signal, its output end Y2 export low electricity simultaneously by NAND gate V2 two inputs A2, B2
Ordinary mail number；
When NAND gate V1 input A1, B1 input high level signal, its output end Y1 output low level signals, NAND gate V2
Two inputs A2, B2 simultaneously input low level signal, its output end Y2 output high level signal；
C, OR gate：It is as shown in table 3 the truth table of OR circuit conversion, when NAND gate V1 two inputs A1, B1 are simultaneously defeated
Enter low level signal, NAND gate V2 two inputs A2, B2 simultaneously input low level signal when, NAND gate V1 output end Y1
High level signal is exported, NAND gate V2 output end Y2 exports high level signal, now, NAND gate V3 two input A3,
Input high level signal, its output end Y3 export low level signal to B3 simultaneously；
As NAND gate V1 two inputs A1, B1, input low level signal, NAND gate V2 two inputs A2, B2 are same simultaneously
When input high level signal when, NAND gate V1 output end Y1 output high level signal, NAND gate V2 output end Y2 output it is low
Level signal, now, NAND gate V3 two inputs A3, B3 difference input high level signal and low level signal, it is exported
Hold Y3 output high level signals；
As NAND gate V1 two inputs A1, B1, input high level signal, NAND gate V2 two inputs A2, B2 are same simultaneously
When input low level signal when, NAND gate V1 output end Y1 output low level signals, NAND gate V2 output end Y2 outputs are high
Level signal, now, NAND gate V3 two inputs A3, B3 difference input low level signal and high level signal, it is exported
Hold Y3 output high level signals；
As NAND gate V1 two inputs A1, B1, input high level signal, NAND gate V2 two inputs A2, B2 are same simultaneously
When input high level signal when, NAND gate V1 output end Y1 output low level signal, NAND gate V2 output end Y2 output it is low
Level signal, now, input low level signal, its output end Y3 outputs are high electric simultaneously by NAND gate V3 two inputs A3, B3
Ordinary mail number；
D, nor gate：It is as shown in table 4 the truth table of OR-NOT circuit conversion, when NAND gate V1 two inputs A1, B1 are same
When input low level signal, NAND gate V2 two inputs A2, B2 simultaneously input low level signal when, NAND gate V1 output
Y1 output high level signals are held, NAND gate V2 output end Y2 exports high level signal, now, NAND gate V3 two inputs
Input high level signal, its output end Y3 output low level signals, NAND gate V4 two inputs A4, B4 are same simultaneously by A3, B3
When input low level signal, its output end Y4 output high level signal；
As NAND gate V1 two inputs A1, B1, input low level signal, NAND gate V2 two inputs A2, B2 are same simultaneously
When input high level signal when, NAND gate V1 output end Y1 output high level signal, NAND gate V2 output end Y2 output it is low
Level signal, now, NAND gate V3 two inputs A3, B3 difference input high level signal and low level signal, it is exported
Y3 output high level signals are held, input high level signal, its output end Y4 are exported simultaneously by NAND gate V4 two inputs A4, B4
Low level signal；
As NAND gate V1 two inputs A1, B1, input high level signal, NAND gate V2 two inputs A2, B2 are same simultaneously
When input low level signal when, NAND gate V1 output end Y1 output low level signals, NAND gate V2 output end Y2 outputs are high
Level signal, now, NAND gate V3 two inputs A3, B3 difference input low level signal and high level signal, it is exported
Y3 output high level signals are held, input high level signal, its output end Y4 are exported simultaneously by NAND gate V4 two inputs A4, B4
Low level signal；
As NAND gate V1 two inputs A1, B1, input high level signal, NAND gate V2 two inputs A2, B2 are same simultaneously
When input high level signal when, NAND gate V1 output end Y1 output low level signal, NAND gate V2 output end Y2 output it is low
Level signal, now, input low level signal, its output end Y3 outputs are high electric simultaneously by NAND gate V3 two inputs A3, B3
Ordinary mail number, input high level signal, its output end Y4 export low level signal simultaneously by NAND gate V4 two inputs A4, B4；
E, XOR gate：It is as shown in table 5 the truth table of NOR gate circuit conversion, when NAND gate V1 two inputs A1, B1 are same
When input low level signal, NAND gate V2 two inputs A2, B2 simultaneously input low level signal when, NAND gate V1 output
Y1 output high level signals are held, NAND gate V2 output end Y2 exports high level signal, now, NAND gate V3 two inputs
A3, B3 distinguish input high level signal and low level signal, and its output end Y3 exports high level signal, and two of NAND gate V4 are defeated
Enter to hold A4, B4 difference input low level signal and high level signal, its output end Y4 output high level signals, the two of NAND gate V5
Input high level signal, NAND gate V5 output end Y5 export low level signal simultaneously by individual input A5, B5；
As NAND gate V1 two inputs A1, B1, input low level signal, NAND gate V2 two inputs A2, B2 are same simultaneously
When input high level signal when, NAND gate V1 output end Y1 output high level signal, NAND gate V2 output end Y2 output it is low
Level signal, now, NAND gate V3 two inputs A3, B3 difference input high level signal and high level signal, it is exported
Y3 output low level signals are held, NAND gate V4 two inputs A4, B4 distinguish input low level signal and low level signal, its
Output end Y4 exports high level signal, NAND gate V5 two inputs A5, B5 difference input low level signal and high level letter
Number, NAND gate V5 output end Y5 output high level signals；
As NAND gate V1 two inputs A1, B1, input high level signal, NAND gate V2 two inputs A2, B2 are same simultaneously
When input low level signal when, NAND gate V1 output end Y1 output low level signals, NAND gate V2 output end Y2 outputs are high
Level signal, now, NAND gate V3 two inputs A3, B3 difference input low level signal and low level signal, it is exported
Y3 output high level signals are held, NAND gate V4 two inputs A4, B4 distinguish input high level signal and high level signal, its
Output end Y4 exports low level signal, NAND gate V5 two inputs A5, B5 difference input high level signal and low level letter
Number, NAND gate V5 output end Y5 output high level signals；
As NAND gate V1 two inputs A1, B1, input high level signal, NAND gate V2 two inputs A2, B2 are same simultaneously
When input high level signal when, NAND gate V1 output end Y1 output low level signal, NAND gate V2 output end Y2 output it is low
Level signal, now, NAND gate V3 two inputs A3, B3 difference input low level signal and high level signal, it is exported
Y3 output high level signals are held, NAND gate V4 two inputs A4, B4 distinguish input high level signal and low level signal, its
Output end Y4 exports high level signal, NAND gate V5 two inputs A5, B5 difference input high level signal and high level letter
Number, NAND gate V5 output end Y5 output low level signals；
F, same to OR gate：It is the truth table with OR circuit conversion as shown in table 6, when NAND gate V1 two inputs A1, B1 are same
When input low level signal, NAND gate V3 two inputs A3, B3 simultaneously input low level signal when, NAND gate V1 output
Y1 output high level signals are held, NAND gate V3 output end Y3 exports high level signal, now, NAND gate V2 two inputs
A2, B2 distinguish input low level signal and low level signal, and its output end Y2 exports high level signal, and two of NAND gate V4 are defeated
Enter to hold A4, B4 difference input high level signal and high level signal, its output end Y4 output low level signals, the two of NAND gate V5
Individual input A5, B5 difference input high level signal and low level signal, NAND gate V5 output end Y5 output high level signals；
As NAND gate V1 two inputs A1, B1, input low level signal, NAND gate V3 two inputs A3, B3 are same simultaneously
When input high level signal when, NAND gate V1 output end Y1 output high level signal, NAND gate V3 output end Y3 output it is low
Level signal, now, NAND gate V2 two inputs A2, B2 difference input low level signal and high level signal, it is exported
Y2 output high level signals are held, NAND gate V4 two inputs A4, B4 distinguish input high level signal and low level signal, its
Output end Y4 exports high level signal, NAND gate V5 two inputs A5, B5 difference input high level signal and high level letter
Number, NAND gate V5 output end Y5 output low level signals；
As NAND gate V1 two inputs A1, B1, input high level signal, NAND gate V3 two inputs A3, B3 are same simultaneously
When input low level signal when, NAND gate V1 output end Y1 output low level signals, NAND gate V3 output end Y3 outputs are high
Level signal, now, NAND gate V2 two inputs A2, B2 difference input high level signal and low level signal, it is exported
Y2 output high level signals are held, NAND gate V4 two inputs A4, B4 distinguish input low level signal and high level signal, its
Output end Y4 exports high level signal, NAND gate V5 two inputs A5, B5 difference input high level signal and high level letter
Number, NAND gate V5 output end Y5 output low level signals；
As NAND gate V1 two inputs A1, B1, input high level signal, NAND gate V3 two inputs A3, B3 are same simultaneously
When input high level signal when, NAND gate V1 output end Y1 output low level signal, NAND gate V3 output end Y3 output it is low
Level signal, now, NAND gate V2 two inputs A2, B2 difference input high level signal and high level signal, it is exported
Y2 output low level signals are held, NAND gate V4 two inputs A4, B4 distinguish input low level signal and low level signal, its
Output end Y4 exports high level signal, NAND gate V5 two inputs A5, B5 difference input low level signal and high level letter
Number, NAND gate V5 output end Y5 output high level signals；
The specific embodiment of the present invention is explained in detail above in conjunction with accompanying drawing, but the present invention is not limited to above-mentioned implementation
Example, in those of ordinary skill in the art's possessed knowledge, can also make on the premise of present inventive concept is not departed from
Go out various change.
Claims (7)
- A kind of 1. conversion method of conventional logic gates, it is characterised in that：The NOT gate of conventional logic gates, with door or It is door, nor gate, XOR gate, respectively converted by using one or several NAND gates with OR gate.
- 2. the conversion method of conventional logic gates according to claim 1, it is characterised in that：Turn of one NOT gate The method of changing is：One NOT gate is equivalent to composition after two inputs A, B connection by a NAND gate V.
- 3. the conversion method of conventional logic gates according to claim 1, it is characterised in that：Described in one with door turn The method of changing is：Converted by two NAND gates with door described in one, two inputs A1, B1 of the NAND gate V1 are as defeated Enter end, NAND gate V1 output end Y1 is connected to NAND gate V2 two inputs A2, B2, NAND gate V2 output end Y2 simultaneously As output end.
- 4. the conversion method of conventional logic gates according to claim 1, it is characterised in that：Turn of one OR gate The method of changing is：One OR gate is converted by three NAND gates, two inputs A1, B1 connection of the NAND gate V1, Its output end Y1 is connected to NAND gate V3 input A3, NAND gate V2 two inputs A2, B2 connection, and its output end Y2 connects Then NAND gate V3 input B3, NAND gate V3 output end Y3 are as output end.
- 5. the conversion method of conventional logic gates according to claim 1, it is characterised in that：One nor gate Conversion method is：One nor gate is converted by four NAND gates, and two inputs A1, B1 of the NAND gate V1 connect Connect, NAND gate V2 two inputs A2, B2 connection, output end Y1, Y2 of NAND gate V1, V2 respectively connected NAND gate V3's Input A3, B3, NAND gate V3 output end are connected with NAND gate V4 two inputs A4, B4 simultaneously, and NAND gate V4's is defeated Go out to hold Y4 as output end.
- 6. the conversion method of conventional logic gates according to claim 1, it is characterised in that：One XOR gate Conversion method is：One XOR gate is converted by 5 NAND gates, after NAND gate V1 two inputs A1, B1 connection NAND gate V4 input A4 is connected to, NAND gate V3 input is connected to after NAND gate V2 two inputs A2, B2 connection B3 is held, output end Y1, Y2 of NAND gate V1, V2 respectively connected input A3, B4 of NAND gate V3, V4, NAND gate V3, V4 Output end Y3, Y4 respectively connected NAND gate V5 input A5, B5, and NAND gate V5 output end Y5 is as output end.
- 7. the conversion method of conventional logic gates according to claim 1, it is characterised in that：One same OR gate Conversion method is：One same OR gate is converted by 5 NAND gates, and the input A2 of the NAND gate V2 is connected to simultaneously NAND gate V1 two inputs A1, B1, NAND gate V2 input B2 be connected to simultaneously NAND gate V3 two input A3, B3, output end Y1, Y3 of NAND gate V1, V3 respectively connected NAND gate V4 input A4, B4, the output of NAND gate V2, V4 End Y2, Y4 respectively connected NAND gate V5 two inputs A5, B5, and NAND gate V5 output end Y5 is as output end.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111555751A (en) * | 2020-06-02 | 2020-08-18 | 杭州电子科技大学 | Three-value exclusive-or and exclusive-or logic gate circuit based on memristor |
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2017
- 2017-09-26 CN CN201710880132.1A patent/CN107863958A/en active Pending
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| 林春: "《电工与电子技术实验》", 31 July 2012 * |
| 黄培根 等: "《Multisim&电子技术实验》", 28 February 2005 * |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111555751A (en) * | 2020-06-02 | 2020-08-18 | 杭州电子科技大学 | Three-value exclusive-or and exclusive-or logic gate circuit based on memristor |
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Application publication date: 20180330 |