CN103605590A

CN103605590A - Novel built-in system memory testing structure and method

Info

Publication number: CN103605590A
Application number: CN201310613654.7A
Authority: CN
Inventors: 周美娣; 何文涛; 殷明; 黄璐; 冯华星
Original assignee: JIAXING MICROELECTRONICS AND SYSTEMS ENGINEERING CENTER CHINESE ACADEMY OF SCIENCES
Current assignee: JIAXING MICROELECTRONICS AND SYSTEMS ENGINEERING CENTER CHINESE ACADEMY OF SCIENCES; Jiaxing Microelectronics and Systems Engineering of CAS
Priority date: 2013-11-27
Filing date: 2013-11-27
Publication date: 2014-02-26

Abstract

The invention discloses a built-in system memory testing structure which is built in an SoC (system on chip). The testing structure comprises a CPU (central processing unit), a controller, a system bus, an SPI (serial peripheral interface) and a multiplexer. The CPU is connected with a memory array in the SoC through the system bus; the controller is connected with an external testing machine through the SPI; one input end of the multiplexer is connected with the system bus while another input end of the same is connected with the controller, and an output end of the multiplexer is connected to zero position SRAM (static random access memory); the SPI is an SPI Slave external interface, and four connection wires are arranged between the external interface and the external testing machine. The invention further discloses a built-in system memory testing method applied to the built-in system memory testing structure. Through the built-in CPU, software based testing of the memory array in the SoC is realized; the SPI is easy to implement, fewer in the wires and high in communication speed, so that testing time is saved.

Description

Test structure and the method for novel embedded system storer

Technical field

The present invention relates to integrated circuit testing field, relate in particular to a kind of test structure and method of embedded system storer of novelty.

Background technology

Because storer is middle-level darker in the design of fairly large integrated circuit, its defect type is different from the defect type of general logic, ATPG(Automatic Test Pattern Generation, automatic test vector generation method) conventionally can not provide complete memory test solution, and embedded memory test technology (Memory Build in self test circuit, MBIST) can address these problems.BIST(Build In Self Test, embedded self testing circuit) can under the prerequisite of not sacrificing detection quality, provide a kind of memory test solution, under many circumstances, the needs that outside test vector generated to (and ATE machine memory span) and test application time can thoroughly be eliminated or reduce to greatest extent to BIST structure.Designer can carry out embedded memory test circuit in certain design inside, and realizes at full speed and testing easily due to the contiguous tested storer of embedded memory test circuit.

Therefore, current embedded system memory test adopts embedded self-testing structure mostly.Embedded self-testing structure, by testing algorithm Hardware, is embedded into internal system.Basic method is the requirement according to algorithm, and each piece SRAM is carried out to write operation, then reads result and expected result is compared, if in full accord, determine memory test is passed through, otherwise determine memory test failure.But the method is limited to the algorithm of Hardware, can not cover all faults, if a certain inefficacy is not in algorithm requires, will cause erroneous judgement, to producing, impact.

Therefore, those skilled in the art is devoted to develop a kind of test structure and method of embedded system storer of novelty, make the test of embedded system storer no longer be limited to hardware, only need outside sheet, to storer, test by composition memory test procedure.

Summary of the invention

Because the above-mentioned defect of prior art, technical matters to be solved by this invention is to provide a kind of test structure and method of embedded system storer, by using Embedded CPU, be convenient to realize various Test Algorithms for Memory with software, for memory test.

For achieving the above object, the invention provides a kind of test structure of embedded system storer, be embedded in SoC chip, it is characterized in that, comprise CPU, controller, system bus, SPI interface and MUX, described CPU is connected with the memory array in described SoC chip by described system bus, described controller is connected with external testing machine by described SPI interface, described memory array comprises a plurality of SRAM and ROM, described system bus connects an input end of described MUX, the output terminal of described MUX connects a SRAM in described SRAM array.

Further, the address of the described SRAM that the output terminal of described MUX connects is 0.

Further, another input end of described MUX connects described controller.

Further, described controller is time sequence conversion circuit, for SPI sequential is converted to SRAM sequential.

Further, described SPI interface is SPI Slave external interface.

Further, between described SPI Slave external interface and described external testing machine, there are 4 wiring, connect respectively pin SPICS, pin SPICLK, pin MOSI and the pin MISO of described SPI Slave external interface.

Further, described pin SPICS is input pin, and described pin SPICLK is input pin, and described pin MOSI is input pin, and described pin MISO is output pin.

The present invention also provides a kind of method of testing of embedded system storer, and the test structure for above-mentioned embedded system storer, is characterized in that, comprises

External testing machine setup test program described in step 301;

Described in step 302, the described SoC chip of external testing machine is set to memory test patterns;

Described in step 303, external testing machine sends to described SoC chip by described test procedure;

Described in step 304, controller receives described test procedure, and is kept in described zero-bit SRAM;

Described in step 305, external testing machine carries out reset operation to described SOC chip, and described CPU moves described test procedure from described zero-bit SRAM then;

Described in step 306, controller outputs test result to described external testing machine, and described test result is passed through or test failure for testing.

Further, also comprise:

If the test result in the described step 306 of step 307 is test failure, described controller is to described external testing machine output detecting information.

In preferred embodiments of the present invention, a kind of test structure of embedded system storer of the SoC of being embedded in chip is provided, comprise embedded CPU, controller, system bus, SPI interface and MUX.CPU is connected with the memory array in SoC chip by system bus; Controller is connected with external testing machine by SPI interface, for SPI sequential is converted to SRAM sequential; Memory array in SoC chip comprises a plurality of SRAM and ROM; An input end of MUX is connected with system bus, and another input end connects controller, and the SRAM(that output terminal is connected in SRAM array is zero-bit SRAM); SPI interface is SPI Slave external interface, between itself and external testing machine, has 4 wiring.In preferred embodiments of the present invention, a kind of method of testing of embedded system storer is also provided, comprise step: external testing machine setup test program; SoC chip is set to memory test patterns; Test procedure is sent to SoC chip; Receive test procedure, and be kept in zero-bit SRAM; CPU is from zero-bit SRAM operation test procedure; And output test result.And can, when test result is test failure, provide the analysis to test result.

As can be seen here, the test structure of embedded system storer of the present invention and method, by using Embedded CPU, realized the test based on software to the memory array in SoC chip, this test is not limited to the structure of hardware, can after chip production, write flexibly testing algorithm, search out of memory reason locate failure position; And can feed back according to test result, once find the inefficacy that some does not cover, can revise flexibly test procedure, search failure cause locate failure position, greatly improve thus test coverage.In addition, the memory test program that the present invention uses SPI Slave external interface to send from test machine, and feedback test result, realize and extraneous communicating by letter, this SPI Interface realization is simple, and outside connection only needs four lines, and spi bus traffic rate is higher, has saved the test duration thus.

Below with reference to accompanying drawing, the technique effect of design of the present invention, concrete structure and generation is described further, to understand fully object of the present invention, feature and effect.

Accompanying drawing explanation

Fig. 1 is the structured flowchart of the test structure of embedded system storer of the present invention.

Fig. 2 is the process flow diagram of the method for testing of embedded system storer of the present invention, for the test structure of embedded system storer of the present invention.

Embodiment

The test structure of embedded system storer of the present invention is embedded in SoC chip, and as shown in Figure 1, it comprises CPU, controller, system bus, SPI interface and MUX MUX.Wherein, CPU is embedded CPU, and it is connected with the memory array in SoC chip by system bus.Controller is connected with external testing machine by SPI interface, and it is a time sequence conversion circuit, for SPI sequential is converted to SRAM sequential.Memory array in SoC chip comprises a plurality of SRAM and ROM, as shown in Figure 1 SRAM0, SRAM1 ..., SRAMn and ROMn.SRAM0 is wherein called zero-bit SRAM in the present embodiment, and its address is 0; SRAM1 represents first SRAM ..., SRAMn represents n SRAM, ROMn represents n ROM.

CPU by the SRAM1 in system bus and memory array ..., SRAMn and ROMn be connected one by one, and be connected with SRAM0 with MUX MUX by system bus.Particularly, an output terminal of system bus is connected with an input end of MUX MUX, and it is SRAM0 that the output terminal of MUX MUX is connected to zero-bit SRAM(), another input end of MUX MUX connects the output terminal of controller.

In the present embodiment, SPI interface is SPI Slave external interface, between itself and external testing machine, there are 4 wiring, pin SPICS, the pin SPICLK, pin MOSI and the pin MISO that connect respectively SPI Slave external interface, pin SPICS is input pin, pin SPICLK is input pin, and pin MOSI is input pin, and pin MISO is output pin.Pin SPICS in the present embodiment, pin SPICLK, pin MOSI and pin MISO are all industrywide standard, and wherein SPICS is chip selection signal, and SPICLK is clock signal, and MOSI is input signal, and MISO is output signal.

Fig. 2 shows the process flow diagram of the method for testing of embedded system storer of the present invention, and it,, for the test structure of embedded system storer of the present invention, comprises the following steps particularly:

Step 301, external testing machine setup test program, so that the memory array in SoC chip is tested, it is in particular generation test vector, i.e. a series of pumping signals that are used for testing memory array, its form of expression that is test procedure.

Step 302, external testing machine SoC chip is set to memory test patterns, starts thus the memory array in SoC chip to test, and correspondingly, MUX MUX selection path is that controller arrives zero-bit SRAM.

Step 303, external testing machine sends to SoC chip by test procedure.Be in particular, the test procedure of preparing in external testing machine step 301 sends to the controller of the test structure that is embedded in the embedded system storer of the present invention in SoC chip by SPI Slave external interface.

Step 304, controller receives test procedure, and is kept in zero-bit SRAM.Be in particular: controller receives the test procedure that external testing machine sends in step 304, and by the path that MUX MUX selects in step 302, the test procedure of reception be saved in to zero-bit SRAM.

Step 305, external testing machine carries out reset operation to SOC chip, and CPU moves test procedure from zero-bit SRAM then, thereby the memory array in SoC chip is tested, and this test can be the comprehensive test to the memory array in SoC chip.

Step 306, controller outputs test result to outside test machine, and test result is passed through or test failure for testing.Test is by being that each SRAM and ROM tested in memory array meets testing standard, and test failure is that in memory array, one or more SRAM and/or ROM exist fault.

When test result is test failure, the method for testing of embedded system storer of the present invention can also provide the analysis to test result, comprises:

Step 307, if the test result in step 306 is test failure, controller is to outside test machine output detecting information.This detecting information comprises each SRAM in memory array and the concrete test data of ROM, and external testing machine, by analyzing these concrete test datas, can be searched failure cause the locate failure position of memory array.

More than describe preferred embodiment of the present invention in detail.Should be appreciated that those of ordinary skill in the art just can design according to the present invention make many modifications and variations without creative work.Therefore, all those skilled in the art, all should be in the determined protection domain by claims under this invention's idea on the basis of existing technology by the available technical scheme of logical analysis, reasoning, or a limited experiment.

Claims

1. the test structure of an embedded system storer, be embedded in SoC chip, it is characterized in that, comprise CPU, controller, system bus, SPI interface and MUX, described CPU is connected with the memory array in described SoC chip by described system bus, described controller is connected with external testing machine by described SPI interface, described memory array comprises a plurality of SRAM and ROM, described system bus connects an input end of described MUX, and the output terminal of described MUX connects a SRAM in described SRAM array.

2. the test structure of embedded system storer as claimed in claim 1, the address of the described SRAM that the output terminal of wherein said MUX connects is 0.

3. the test structure of embedded system storer as claimed in claim 2, another input end of wherein said MUX connects described controller.

4. the test structure of embedded system storer as claimed in claim 3, wherein said controller is time sequence conversion circuit, for SPI sequential is converted to SRAM sequential.

5. the test structure of embedded system storer as claimed in claim 4, wherein said SPI interface is SPI Slave external interface.

6. the test structure of embedded system storer as claimed in claim 5, between wherein said SPI Slave external interface and described external testing machine, there are 4 wiring, connect respectively pin SPICS, pin SPICLK, pin MOSI and the pin MISO of described SPI Slave external interface.

7. the test structure of embedded system storer as claimed in claim 6, wherein said pin SPICS is input pin, and described pin SPICLK is input pin, and described pin MOSI is input pin, and described pin MISO is output pin.

8. a method of testing for embedded system storer, the test structure for embedded system storer as claimed in claim 7, is characterized in that, comprises

The described external testing machine of step (301) setup test program;

The described SoC chip of the described external testing machine of step (302) is set to memory test patterns;

The described external testing machine of step (303) sends to described SoC chip by described test procedure;

The described controller of step (304) receives described test procedure, and is kept in described zero-bit SRAM;

The described external testing machine of step (305) carries out reset operation to described SOC chip, and described CPU moves described test procedure from described zero-bit SRAM then;

The described controller of step (306) outputs test result to described external testing machine, and described test result is passed through or test failure for testing.

9. the method for testing of embedded system storer as claimed in claim 8, wherein also comprises:

Step (307) is if the test result in described step (306) is test failure, and described controller is to described external testing machine output detecting information.