CN103839590B

CN103839590B - The measurement apparatus of memorizer time sequence parameter, method and memory chip

Info

Publication number: CN103839590B
Application number: CN201410100910.7A
Authority: CN
Inventors: 刘慧�; 齐子初
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2014-03-18
Filing date: 2014-03-18
Publication date: 2016-09-21
Anticipated expiration: 2034-03-18
Also published as: CN103839590A

Abstract

The present invention provides measurement apparatus, method and the memory chip of a kind of memorizer time sequence parameter.The measurement apparatus of memorizer time sequence parameter provided by the present invention includes: scan chain and clock control module；Described scan chain includes the many groups of scanning triggering groups being arranged on the chip of memorizer place, and often group scanning triggering group corresponds respectively to a port to be measured of described memorizer, and described scanning triggering group includes at least one sweep trigger；Multiple sweep triggers are connected to constitute described scanning triggering group, and multiple scanning triggering groups are connected to constitute described scan chain.The present invention can measure the time sequence parameter obtained corresponding to each port of memorizer, and its certainty of measurement is higher.

Description

Measuring device and method for time sequence parameters of memory and memory chip

Technical Field

The invention relates to the field of integrated circuits, in particular to a device and a method for measuring time sequence parameters of a memory and a memory chip.

Background

With the continuous development of integrated circuit technology, more and more high performance processor chips and complex System On Chip (SOC) chips are applied to integrated circuits. Most of these high performance processor chips and SOCs integrate, for example, a Random Access Memory (RAM), a 4-port register file, a content-addressable Memory (CAM), and the like. These memories must be rigorously tested after fabrication to ensure that the performance parameters meet the requirements.

The testing of the memory includes functional testing and performance testing. The functional test of the memory is mainly to test the basic functions of the memory, such as read operation, write operation, search operation, and the like. A common method for testing the basic functions of a Memory is a Built-in self-Test (MBIST) method of the Memory, in which a BIST circuit is Built into a chip on which the Memory is located during design and manufacture to Test the read/write operations of the Memory. In addition to testing the frequency of read and write operations, performance testing of a memory also requires measurement of some timing parameters, such as a setup time (setup time) parameter, a hold time (hold time) parameter, and an access time (access time) parameter. Establishing a time T_setupIs the time that the data input needs to reach stability before the clock arrives; maintenance time T_holdIs the time after the clock arrives when the data input must still be valid; access time T_accessIs the time from the arrival of the clock until the memory outputs valid data. In the prior art, whether the time sequence meets the requirement or not is judged by operating the BIST circuit, and only the time sequence parameter of the whole memory can be measured, but the time sequence parameter of each input or output port cannot be measured.

In the prior art, the time sequence parameter of each input or output port of the memory cannot be measured, and the precision of the time sequence parameter is low.

Disclosure of Invention

The invention provides a measuring device and method of a time sequence parameter of a memory and a memory chip, and aims to solve the problem of low measuring precision of the time sequence parameter in the prior art.

The invention provides a measuring device of a memory time sequence parameter, comprising: a scan chain and a clock control module; the scan chain comprises at least one group of scan trigger groups arranged on a chip where a memory is located, each group of scan trigger groups respectively corresponds to a port to be tested of the memory, and each scan trigger group comprises at least one scan trigger; at least one of the scan flip-flops is connected in series to form the scan trigger group, and at least one of the scan trigger groups is connected in series to form the scan chain; the scan chain is used for providing a test signal for the memory; the test signal comprises write configuration information and read configuration information and is used for indicating the memory to execute write operation according to the write configuration information and execute read operation according to the read configuration information;

the clock control module is respectively connected with the scan chain and the memory and used for providing a first clock signal for the scan chain, providing a second clock signal for the memory, updating the second clock signal by adjusting the delay between the capturing period of the first clock signal and the capturing period of the second clock signal when the memory executes write operation or read operation until the execution time sequence of the memory is not satisfied, and determining the time sequence parameter of the port to be tested according to the adjusted delay.

The invention also provides a memory chip which comprises the memory timing sequence parameter measuring device.

The invention also provides a measuring method of the time sequence parameter of the memory, the chip on which the memory is arranged is provided with at least one group of scanning trigger groups, each group of scanning trigger groups respectively corresponds to one port to be measured of the memory, and each scanning trigger group comprises at least one scanning trigger; at least one of the scan flip-flops is connected in series to form the scan trigger group, and at least one of the scan trigger groups is connected in series to form the scan chain; the method comprises the following steps:

providing a first clock signal for the scan chain, and controlling the scan chain to serially shift a test signal into a scan flip-flop in the scan chain in a shift period of the first clock signal, wherein the test signal comprises write configuration information and read configuration information;

providing a second clock signal for the memory, controlling the memory to capture the test signal in a capture period of the second clock signal, executing write operation according to the write configuration information, and executing read operation according to the read configuration information;

updating the second clock signal by adjusting a delay between a capture period of the first clock signal and a capture period of the second clock signal when the memory performs a write operation or a read operation until an execution timing of the memory is satisfied to be unsatisfied;

and determining the time sequence parameter of the port to be measured according to the adjusted delay.

The invention also provides a measuring device for the time sequence parameters of the memory, wherein the chip on which the memory is arranged is provided with at least one group of scanning trigger groups, each group of scanning trigger groups respectively corresponds to one port to be tested of the memory, and each scanning trigger group comprises at least one scanning trigger; at least one of the scan flip-flops is connected in series to form the scan trigger group, and at least one of the scan trigger groups is connected in series to form the scan chain; the measuring device comprises:

the first control module is used for providing a first clock signal for the scan chain and controlling the scan chain to serially shift a test signal into a scan flip-flop in the scan chain in a shift period of the first clock signal, wherein the test signal comprises write configuration information and read configuration information;

the second control module is used for providing a second clock signal for the memory, controlling the memory to capture the test signal in the capture period of the second clock signal, executing write operation according to the write configuration information, and executing read operation according to the read configuration information;

an adjusting module, configured to update the second clock signal by adjusting a delay between a capture period of the first clock signal and a capture period of the second clock signal when the memory performs a write operation or a read operation until an execution timing of the memory is not satisfied from a satisfied timing;

and the determining module is used for determining the time sequence parameter of the port to be measured according to the adjusted delay.

The invention provides a measuring device and a method for timing sequence parameters of a memory and a memory chip.

Drawings

FIG. 1 is a schematic structural diagram of an apparatus for measuring timing parameters of a memory according to an embodiment of the present invention;

FIG. 2 is a schematic diagram illustrating a connection between a measuring device for measuring timing parameters of a memory and the memory according to a second embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating a connection between a measuring device for measuring timing parameters of a memory and the memory according to a third embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating another measurement apparatus for measuring timing parameters of a memory according to a third embodiment of the present invention;

FIG. 5 is a schematic diagram illustrating a connection between a measuring device and a memory according to a fourth embodiment of the present invention;

fig. 6 is a schematic structural diagram of a clock control module in the measurement apparatus according to the fourth embodiment of the present invention;

fig. 7 is a schematic structural diagram of a memory chip according to a fifth embodiment of the present invention;

FIG. 8 is a flowchart illustrating a method for measuring timing parameters of a memory according to a sixth embodiment of the present invention;

FIG. 9 is a flowchart illustrating a method for measuring timing parameters of a memory according to a seventh embodiment of the present invention;

FIG. 10 is a flowchart illustrating a method for measuring timing parameters of a memory according to an eighth embodiment of the present invention;

FIG. 11 is a flowchart illustrating a method for measuring timing parameters of a memory according to a ninth embodiment of the present invention;

fig. 12 is a schematic structural diagram of a memory timing parameter measurement apparatus according to a tenth embodiment of the present invention;

FIG. 13 is a schematic diagram illustrating a connection between a measuring device for measuring timing parameters of a memory and the memory according to an eleventh embodiment of the present invention;

FIG. 14 is a flowchart illustrating a method for measuring memory access time according to an eleventh embodiment of the present invention;

FIG. 15 is a timing diagram of access time and clock according to an eleventh embodiment of the present invention;

FIG. 16 is a flowchart illustrating a method for measuring a memory setup time according to an eleventh embodiment of the present invention;

FIG. 17 is a diagram illustrating a relationship between a set-up time and a clock according to an eleventh embodiment of the present invention;

FIG. 18 is a flowchart illustrating a method for measuring retention time of a memory according to an eleventh embodiment of the present invention;

FIG. 19 is a timing diagram of the hold time and the clock according to the eleventh embodiment of the present invention.

Detailed Description

Example one

Fig. 1 is a schematic structural diagram illustrating a connection between a measuring device for a memory timing parameter and a memory according to an embodiment of the present invention. As shown in fig. 1, the measurement apparatus 100 includes a scan chain 101 and a clock control module 102. Wherein, the scan chain 101 includes at least one scan trigger group 104 disposed on the chip where the memory 103 is located. The memory chip may be a Printed Circuit Board (PCB) on which the memory is located, or integrated with the memory inside one chip.

Each scan trigger group 104 corresponds to a port to be tested of the memory, and includes at least one scan trigger 105. At least one of the scan flip-flops 105 is serially connected to form a scan flip-flop group 104, and at least one of the scan flip-flop groups 104 is serially connected to form a scan chain 101.

Specifically, the ports to be tested of the memory can be input ports and output ports of the memory. The input ports of the memory comprise an input data IN port, a write enable WEN port, a write address WADDR port, a read enable REN port and a read address RADDR port. The output port of the memory is an output data OUT port. The scanning trigger group corresponding to the IN port can be an input data scanning trigger group and is represented by IN _ s; the scanning trigger group corresponding to the WEN port can be a write-enable scanning trigger group, and is represented by WEN _ s; the scanning trigger group corresponding to the WADDR port can be a write address scanning trigger group and is represented by WADDR _ s; the scan trigger group corresponding to the REN port may be a read enable scan trigger group, which is represented by REN _ s; the scan trigger set corresponding to the RADDR port may be a read address scan trigger set, which is denoted by RADDR _ s. It should be noted that the memory may have 1 port, i.e. one write port and one read port, and may also have a plurality of ports, e.g. 2 ports, 4 ports, etc., and correspondingly, the scan chain includes the scan trigger group corresponding thereto.

When the data transmitted by the port to be tested is a one-bit binary system, the scanning trigger group corresponding to the port to be tested comprises a scanning trigger; when the data transmitted by the port to be tested is a multi-bit binary system, the scanning trigger group corresponding to the port to be tested comprises a plurality of triggers corresponding to the number of the transmitted data bits. One of the flip-flops stores only one binary datum at a time. Such as the write data, the write address, and the read address information, are difficult to represent by 1 flip-flop. Therefore, at least one scan flip-flop is sequentially connected in series to form a corresponding scan flip-flop group. Specifically, a data trigger group IN _ s is input into a scan trigger group of the scan chain; a write address trigger group WADDR _ s; the read address trigger groups RADDR _ s may include more than 1 flip-flops, respectively; for the write enable trigger group WEN and the read enable trigger group REN _ s, only one flip-flop is required.

A scan chain 101 for providing a test signal to the memory; the test signal includes write configuration information and read configuration information, and is used for instructing the memory to execute write operation according to the write configuration information and to execute read operation according to the read configuration information.

In particular, the scan chain provides a test signal to the memory, the corresponding test signal being actually provided to the memory by at least one scan trigger group comprised by the scan chain. The write configuration information may include information corresponding to each scan trigger set of WEN _ s, WADDR _ s, and DATA _ s. If the scan chain provides the memory with the write configuration information, the values corresponding to the rest scan trigger groups can be all 0. The read configuration information may include information corresponding to each scan trigger set of REN _ s and RADDR _ s, and the values corresponding to the remaining scan triggers may be 0.

The memory performs a write operation according to the write configuration information, actually writes predetermined data to a predetermined address, performs a read operation according to the read configuration information, and actually reads the data previously written to the predetermined address. If the port to be tested is a write address WADDR port, the information corresponding to the WADDR _ s in the write configuration information is different from the value of the RADDR _ s in the read configuration information; if the port to be tested is other than the write address WADDR port, the information corresponding to the WADDR _ s in the write configuration information and the RADDR _ s in the read configuration information have the same assignment. (when the port to be tested is WADDR, the read address and the write address of the same cycle are the same, but the address of each cycle is different)

And the clock control module 102 is respectively connected with the scan chain 101 and the memory and used for providing a first clock signal CLK1 for the scan chain 101, providing a second clock signal CLK2 for the memory 103, updating the second clock signal CLK2 by adjusting the delay between the capturing period of the first clock signal CLK1 and the capturing period of the second clock signal CLK2 when the memory performs a write operation or a read operation until the execution timing of the memory is not satisfied, and determining the timing parameter of the port to be tested according to the adjusted delay.

At least one of the scan flip-flops is serially connected to form a scan trigger group, and at least one of the scan trigger groups is serially connected to form the scan chain, so that the input information received by the scan chain is shifted into the flip-flops of the scan trigger groups of the scan chain in a serial shifting manner during the shifting period of the first clock signal. Since the timing requirements for data processing are relatively high during the capture period of the first clock signal, the capture period of CLK1 includes at least one high-speed clock pulse. However, the shift period of the first clock signal, which is mainly to shift the write configuration information or the read configuration information to the scan chain flip-flops in series, is mainly required to be high in accuracy of transferring information, and thus the shift period of the CLK1 includes at least one low-speed pulse.

The timing parameters include: setup time, hold time, access time. The setup time and the hold time belong to a write timing parameter, and the access time belongs to a read timing parameter. If the timing parameter to be tested corresponding to the port to be tested is a write timing parameter, the clock control module adjusts the delay between the capture period of the CLK1 and the capture period of the CLK2 when the memory performs the write operation to update the CLK 2; if the timing parameter to be tested corresponding to the port to be tested is a read timing parameter, the clock control module adjusts a delay between the capture period of the CLK1 and the capture period of the CLK2 when the memory performs a read operation to update the CLK 2.

When the execution time sequence of the memory is satisfied, the data read by executing the read operation is the same as the write data, and when the execution time sequence of the memory is not satisfied, the data read by executing the read operation is different from the write data. The timing of the memory is satisfied to be not satisfied, for example, by determining whether the data read by the memory performing a read operation is the same as the write data. If the time sequence parameter to be measured is a write time sequence parameter, the memory needs to perform write operation, read operation and the like again according to the updated CLK2 until it is determined that the data read by the memory and the data written by the memory are changed from the same data to different data. If the timing parameter to be measured is a read timing parameter, the memory needs to perform read operation again according to the updated CLK2, and the like until it is determined that the data read by the memory and the data written by the memory are changed from the same value to different values.

When the memory executes the write operation or the read operation, the second clock signal is updated by adjusting the delay between the capturing period of the first clock signal CLK1 and the capturing period of the second clock signal CLK2 until the execution timing of the memory is not satisfied, and the timing parameter of the port to be tested is determined according to the adjusted delay.

The scan chain may be directly provided in the memory chip, or may be formed by serially connecting flip-flops in a BIST circuit of the memory chip having the BIST circuit. For the scan chain directly arranged in the memory chip, the hardware area can be effectively reduced.

In the measurement apparatus provided in this embodiment, because the scan chain includes the scan trigger group corresponding to the port to be measured of the memory, the measurement of the timing parameter of the port to be measured is realized through the clock control module and the scan trigger group corresponding to the port to be measured, so as to improve the measurement accuracy of the timing parameter of the memory.

Example two

Fig. 2 is a schematic connection diagram of a measuring device for memory timing parameters and a memory according to a second embodiment of the present invention. In the above embodiment, the testing apparatus 100 further includes: and an input control module 201 arranged between the scan chain 101 and the memory 103.

The clock control module 102 is further configured to provide the input control module 201 with a third clock signal CLK3, wherein the third clock signal CLK3 is a clock signal having no shift period compared to the first clock signal CLK 1.

The input control module 201 is used for capturing the data currently stored in the scan chain 101 during the capturing period of the third clock signal CLK3, and providing the data currently stored in the input control module 201 for the memory during the capturing period of the second clock signal CLK 2.

Specifically, the data currently stored in the scan chain is actually the data stored in the corresponding scan flip-flop in each scan flip-flop group of the scan chain. The input control module captures the data currently stored in the scan chain during the capture period of CLK3, and in effect captures the data stored by each scan flip-flop in the scan flip-flop group corresponding to the memory input port in each scan flip-flop group in the scan chain.

In the above scheme, the input control module 201 includes control trigger groups 202 corresponding to the input ports of the memory one to one; the control trigger group 202 includes at least one control trigger 203.

After capturing the data currently stored in the scan chain, the input control module transmits the data to the corresponding input port of the memory in parallel. The control trigger groups of the input control module correspond to input ports of the memory respectively, and the scanning trigger groups of the scan chain correspond to ports of the memory respectively. When the port of the memory is an input port of the memory, the control trigger group corresponds to the scan trigger group.

According to the scheme of the embodiment, the input control module is arranged between the scan chain and the memory, so that the establishment time of the port to be tested of the memory can be measured more accurately.

EXAMPLE III

Fig. 3 is a schematic connection diagram of a measuring device for memory timing parameters and a memory according to a third embodiment of the present invention. In the above embodiment, the scan chain 101 includes the first sub scan chain 301 and the second sub scan chain 302. An input terminal of the first sub scan chain 301 serves as an input terminal of the scan chain 101, an output terminal of the first sub scan chain 301 is connected with an input terminal of the second sub scan chain 302, and an output terminal of the second sub scan chain 302 serves as an output terminal of the scan chain 101.

Specifically, an input terminal of the scan chain 101, i.e., an input terminal of the first sub scan chain 301, is used for receiving a test signal input by a user.

The first sub-scan chain 301 comprises at least one first group of scan triggers 303, the first group of scan triggers 303 corresponding to a write enable WEN port of the memory 103, the first group of scan triggers 303 each being triggered by a first clock edge.

The second sub scan chain 302 comprises at least one second scan trigger group 304, the second scan trigger group 304 corresponds to a port other than the write enable WEN port among the ports of the memory 103, and the second scan trigger groups 304 are all triggered by a second clock edge which belongs to the same clock cycle as the first clock edge and is located before the first clock edge.

IN order to distinguish the timing violation of the write enable WEN port of the memory from other write input ports, such as the timing violation of the input data IN port or the write address WADDR port, the first scan trigger group IN the scan trigger group corresponding to the write enable WEN port IN the scan chain and the scan triggers IN the scan trigger group corresponding to the other ports, that is, the second scan trigger group, have different trigger edges. The first clock edge and the second clock edge are two different clock edges, including a rising edge and a falling edge. When the first clock edge is a rising edge, the second clock edge is a falling edge; when the first clock edge is a falling edge, the second clock edge is a rising edge.

The measurement device also includes a maintenance control module 305.

The sustain control module 305 is coupled to the scan chain 101 for sending a sustain control signal to the scan chain 101 to control the scan chain 101 to update the data stored in the second scan trigger group 304 according to the sustain control signal during the capture period of the first clock signal CLK1, and update the write enable signal stored in the first scan trigger group 301 to be invalid for write enable.

If the write enable port of the memory is in logic high validity, updating the write enable signal stored in the first scanning trigger group to be invalid, namely updating the write enable signal to be invalid value 0; correspondingly, if the write enable port of the memory is active at logic low, the write enable signal stored in the first scan trigger group is updated to be invalid, that is, the write enable signal is updated to be invalid value 1.

And updating the data stored in the second scan trigger group, specifically, according to the maintenance time control signal, negating the data stored in the scan trigger group corresponding to the current port to be tested, and maintaining the original stored data in the rest scan chain trigger groups. Through the maintenance control module, the transmitted maintenance time control signal respectively controls the data stored in each scanning trigger group of the memory and respectively controls the data input into the input port of the memory, so that the measuring device can more accurately measure the time sequence parameters of each input port of the memory.

In the scheme of the embodiment, the input data are ensured to reach the memory to be stable through the trigger time of each scanning trigger group of the scan chain, so that the measured time sequence parameters of the port to be tested of the memory are ensured to be more accurate without being influenced by the time sequence parameters of each trigger of the scan chain; meanwhile, the control module is maintained to respectively control the input data of each input port, so that the accurate time sequence parameters of each port to be measured of the memory are obtained through measurement.

FIG. 4 is a schematic diagram of another measuring apparatus for memory timing parameters according to a third embodiment of the present invention connected to a memory. As shown in fig. 4, the maintenance control module 305 includes: a first control unit 401 and a decoder 402.

Wherein, the output terminal of the first control unit 401 is connected to the input terminal of each first scan trigger group 303 for providing the write enable signal for invalidating the write enable to the first sub scan chain 301.

An input end of the decoder 402, configured to receive port information to be tested, where the decoder 402 includes output ends corresponding to the second scan trigger groups 304 in the second sub scan chain 301 one to one, each output end of the decoder 402 is connected to an input end of each second scan trigger group 304 through an one-out-of-two selector 403, an output end of the decoder 402 is connected to a control end of the one-out-of-two selector 403, a first input end of the one-out-of-two selector 403 is connected to an output end of the second scan trigger 304 corresponding to the one-out-of-two selector 403 through an inverter 404, and a second input end of the one-out-of-two selector 403 is directly connected to an output end of the second scan trigger 304 corresponding to the one-out-of-two selector 403.

The decoder 402 may be a thirty-eight decoder. The maintenance control module 305 decodes the information of the port to be tested input by the first control unit 401 through the decoder 402 and sends the decoded information to the control port of the corresponding one-out-of-two selector 403, and simultaneously feeds back the currently output data of the second scan trigger set to the first input port of the one-out-of-two selector 403, and also feeds back the non-value of the currently output data of the second scan trigger set to the one-out-of-two selector through the inverter 404. If the port information to be tested is the data information corresponding to the input data IN port, the alternative selector obtains the non-value of the currently stored data of the second scanning trigger group corresponding to the port to be tested according to the control signal received by the control port, and the current value of the currently stored data of the second scanning trigger groups corresponding to the other ports.

Specifically, the alternative selector controls to perform or operation on the non-value of the data currently output by the second scanning trigger group and the non-value of the data currently output by the second scanning trigger group according to the control signal received by the control port, so as to obtain the current value of the stored data of the corresponding second scanning trigger group; and the control and operation of the non-value of the data currently output by the second scanning trigger group and the non-value of the data currently output by the second scanning trigger group can obtain the non-value of the corresponding data stored in the second scanning trigger group. It should be noted that the alternative selector controls the currently output data of the second scan trigger group and the currently output data of the second scan trigger group according to the control signal received by the control port of the alternative selector, and updating the data stored in the second scan trigger group may be performed in other manners, which is not described herein again.

Further, in the above embodiment, the control trigger groups corresponding to the write enable WEN ports of the memory 103 in the input control module 201 are all triggered by the first clock edge;

the control flip-flops in the input control module 201 corresponding to the ports of the memory 103 except the write enable port are all triggered by the second clock edge.

Specifically, the trigger clock edge of the control trigger group corresponding to the write enable port in the input control module is actually the same type as the trigger clock edge of the scan trigger group corresponding to the write enable port in the scan chain; and the control trigger groups corresponding to the ports of the memory except the write enable port in the input control module are the same as the trigger clock types of the scanning trigger groups corresponding to the other ports except the write enable port in the scanning chain. For example, if the trigger clock edge of the scan trigger group corresponding to the write enable port in the scan chain is a falling edge, the control trigger group corresponding to the write enable port in the input control module is also a falling edge. Correspondingly, the clock trigger edge of the scan trigger group corresponding to the other ports except the write enable port in the scan chain is a rising edge, and then the control trigger group corresponding to the ports except the write enable port in the memory in the input control module is also a rising edge.

In this embodiment, each control trigger group of the input control module is configured with a corresponding trigger time, so that the influence of the timing parameters of each trigger in each control trigger group of the input control module on the timing parameters of the port to be tested of the memory is avoided, and it is ensured that the timing parameters of the port to be tested of the memory obtained through measurement are more accurate.

Example four

The fourth embodiment of the invention also provides a measuring device. Fig. 5 is a schematic diagram illustrating a connection between a measuring device and a memory according to a fourth embodiment of the present invention. As shown in fig. 5, the measurement apparatus includes a third sub scan chain 501 in the scan chain 101, where the third sub scan chain 501 includes at least one third scan trigger group 502; the third scan trigger set 502 corresponds to an output port of the memory 103.

The third scan trigger group 502 is configured to capture read data obtained by performing a read operation, and shift the read data to an off-chip device, so that the off-chip device compares the read data with write data written by a write operation performed before the read operation is performed, and when the read data is different from the write data, the execution timing of the memory is not satisfied.

The third scan trigger group 502 captures read data obtained by performing a read operation on the memory 102, that is, capturing the read data into a flip-flop corresponding to the third scan trigger group 502, and serially shifting the read data to an off-chip device through an output end of the third scan trigger group 502. The off-chip device may be, for example, an automatic tester. Because the measuring devices are all arranged on the chip where the memory is arranged, due to the limitation of the chip area, a more accurate processor is difficult to configure to compare the data, and therefore data comparison is carried out through off-chip equipment.

Fig. 6 is a schematic structural diagram of a clock control module in the measurement apparatus according to the fourth embodiment of the present invention. As shown in fig. 6, the clock control module 102 in the above embodiment specifically includes: an On-chip-control (OCC) unit 601, a first clock delay chain 602, and a delay chain control unit 603;

the OCC unit 601 is configured to provide a first clock signal for the scan chain according to the type of the timing parameter to be tested of the port to be tested.

The OCC unit 601 is further configured to provide a second clock signal to the memory through the first clock delay chain 602 according to the type of the timing parameter to be tested of the port to be tested.

Because the types of the timing sequence parameters to be tested of the port to be tested are different, the timing sequence conditions met by the timing sequence of the read-write operation executed corresponding to different memories are met, and therefore a clock signal needs to be generated according to the types of the timing sequence parameters to be tested of the port to be tested.

Specifically, the OCC unit further includes a Phase Locked Loop (PLL) clock and a low-speed scan clock therein to generate different clock signals corresponding to the capture period and the shift period. A high-speed clock signal having high-speed pulses is generated by the PLL clock if the CLK1 capture period, and a low-speed clock signal is generated by the low-speed scan clock if the CLK1 shift period. And correspondingly configuring the beat number of the high-speed clock according to the type of the time sequence parameter to be detected and different operations of the memory.

A first input of the first clock delay chain 602 is configured to receive the first clock signal, a second input of the first clock delay chain is connected to the delay chain control unit 603 for receiving a clock delay control signal, and an output of the first clock delay chain 602 is configured to output the second clock signal.

Since the transmission paths of CLK1 and CLK2 are different, in order to ensure that CLK1 and CLK2 transmitted from the OCC unit are delay balanced, the clock signals generated by the OCC modules need to be trimmed by buffers or inverters.

A delay chain control unit 603, configured to generate the clock delay control signal until the execution timing of the memory is not satisfied when the execution timing of the memory is satisfied, so that the first clock delay chain 602 updates the second clock signal according to the clock delay control signal and generates an adjusted delay.

Specifically, the first clock delay chain updates the second clock signal and generates the adjusted delay, which may be a step-by-step delay adjustment by adjusting the number of steps of the first clock delay chain. The size of each stage of delay in the first clock delay chain is related to the design and manufacturing process of the delay chain. The accuracy of the timing parameter of the memory measured by the measuring device depends on the accuracy of the first clock delay chain. Delay chain

Further, the clock control module 102 further includes: a second clock delay chain 604 having the same delay chain structure as the first clock delay chain 602.

The output of the second clock delay chain 604 is connected to the first input of the second clock delay chain 604 through an inverter 605, the second input of the second clock delay chain 604 is connected to the delay chain control unit 603, and the period of the clock signal output from the output of the second clock delay chain 604 is twice the adjusted delay.

Specifically, a second input end of the second clock delay chain is connected to the delay chain control unit, and is configured to receive a clock delay control signal that is the same as that received by the first clock delay chain, and control the second clock delay chain to generate a delay clock signal that is the same as that adjusted by the first clock delay chain. That is, the second clock edge clock chain receives the same clock delay control signal as the first clock edge clock chain, in addition to having the same physical structure. At the same time, the output of the second clock delay chain is connected to the first input of the second clock delay chain through an inverter to generate a delayed clock signal that is twice the adjusted delay. Therefore, the adjusted delay can be obtained by measuring the period of the clock signal output by the output end of the second clock delay chain, and then the corresponding timing parameter can be obtained according to the adjusted delay. Specifically, the error of the finally measured timing parameter can be controlled within a few picoseconds (ps for short) through the second clock delay chain. If the frequency of the clock signal output by the second clock delay chain is too high, the clock signal can be subjected to period measurement after frequency division.

According to the scheme, the clock signal can be adjusted step by adjusting the stage number of the first clock delay chain, so that the clock signal can be updated more finely, and meanwhile, the adjusted delay information can be obtained more accurately by having the same structure and configuration information as the first clock delay chain, so that the time sequence parameter of the port to be measured of the memory obtained by measurement is more accurate.

EXAMPLE five

The embodiment also provides a memory chip. Fig. 7 is a schematic structural diagram of a memory chip according to a fifth embodiment of the present invention. As shown in fig. 7, the memory chip 701 includes a memory timing parameter measuring device 702. The measuring device 702 for the memory timing parameter may be any one of the measuring devices described in the above embodiments.

The memory chip described in this embodiment includes the measurement apparatus described in any of the above embodiments, and thus the specific structure and beneficial effects of the measurement apparatus in this embodiment are similar to those of the above embodiments, and are not described herein again.

EXAMPLE six

The sixth embodiment of the invention also provides a measuring method of the time sequence parameters of the memory. The chip on which the memory is arranged is provided with at least one group of scanning trigger groups, each group of scanning trigger groups respectively corresponds to one port to be tested of the memory, and each scanning trigger group comprises at least one scanning trigger; at least one of the scan flip-flops is connected in series to form the scan trigger group, and at least one of the scan trigger groups is connected in series to form the scan chain.

Fig. 8 is a flowchart of a method for measuring a memory timing parameter according to a sixth embodiment of the present invention. As shown in fig. 8, the method specifically includes the following steps:

step 801, providing a first clock signal for the scan chain, and controlling the scan chain to serially shift a test signal into a scan flip-flop in the scan chain in a shift period of the first clock signal, where the test signal includes write configuration information and read configuration information.

Step 802, providing a second clock signal for the memory, controlling the memory to capture the test signal in a capture period of the second clock signal, executing a write operation according to the write configuration information, and executing a read operation according to the read configuration information.

It should be noted that, for different types of timing parameter measurements, different first clock signals and second clock signals need to be configured.

Step 803, updating the second clock signal by adjusting the delay between the capturing period of the first clock signal and the capturing period of the second clock signal when the memory performs a write operation or a read operation until the execution timing of the memory is not satisfied.

And step 804, determining the time sequence parameter of the port to be measured according to the adjusted delay.

In the method for measuring timing parameters of a memory according to this embodiment, because the scan chains include the scan trigger groups corresponding to the ports to be measured of the memory, when the timing parameters of one of the ports are measured, the scan trigger groups of the scan chains can be respectively controlled to be configured to ensure that the timings of the ports other than the ports to be measured meet, so as to ensure that the timing parameters obtained by measurement are the timing parameters corresponding to the ports to be measured. Therefore, the timing parameter measuring method of the embodiment can obtain the timing parameter corresponding to each port of the memory, and the measurement accuracy is higher.

Preferably, on the basis of the above scheme, wherein the first clock signal includes a first shift period, a second shift period, a first capture period, and a second capture period; the second clock signal includes a third capture period and a fourth capture period; the first capture period is between the first shift period and the second shift period, and the write operation timing of the memory is satisfied between the first capture period and the third capture period; the second capture period is after the second shift period, and the read operation timing of the memory is satisfied between the second capture period and the fourth capture period.

EXAMPLE seven

The embodiment also provides a measuring method of the time sequence parameter of the memory. The port to be tested is an output port of the memory, and the time sequence parameter comprises an access time parameter. Fig. 9 is a flowchart of a method for measuring a memory timing parameter according to a seventh embodiment of the invention. As shown in fig. 9, the method specifically provides a first clock signal to the scan chain in step 801 of the above scheme, and controls the scan chain to serially shift a test signal into scan flip-flops in the scan chain in a shift period of the first clock signal, specifically including:

step 901, controlling the scan chain to shift a write configuration information in a first shift period, where the write configuration information includes port parameters in one-to-one correspondence with at least one write input port.

The at least one write input port includes: a write enable WEN port, an input IN port, a write address WADDR port, and a chip select enable CSN port. The write configuration information at least includes parameters corresponding to the at least one write input port. For example, the write configuration information may be, for example, CSN-0, WEN-1, IN-Data 0, and WADDR-a 0. It should be noted that, since the memory is usually enabled with the chip select enable low, if the chip select enable CSN port of the memory is enabled with the chip select enable high, the CSN in the write configuration information may also be 1; the write enable WEN port of the memory is active high, and if the write enable WEN port of the memory is active low, the WEN in the write configuration information may also be 0.

Step 902, controlling the scan chain to shift read configuration information in a second shift period, where the read configuration information includes port parameters in one-to-one correspondence with at least one read input port.

The at least one read input port includes: a read enable REN port, a read address RADDR port, and a chip select enable CSN port. The read configuration information at least includes parameters corresponding to the at least one write input port. For example, the write configuration information may be, for example, CSN ═ 0, REN ═ 1, and WADDR ═ a 0. It should be noted that the address information in the read configuration information needs to be the same as the address information in the write configuration information.

In step 802 of the foregoing embodiment, providing the second clock signal to the memory, controlling the memory to capture the test signal in the capture period of the second clock signal, executing a write operation according to the write configuration information, and executing a read operation according to the read configuration information includes:

step 903, controlling the memory to capture the write configuration information shifted in by the scan chain in the first shift period in the third capture period, and executing a write operation according to the captured write configuration information.

Step 904, controlling the memory to capture the read configuration information of the scan chain shifted in the second shift period in the fourth capture period, and executing the read operation according to the captured read configuration information.

In step 803 of the foregoing embodiment, updating the second clock signal by adjusting the delay between the capturing period of the first clock signal and the capturing period of the second clock signal when the memory performs a write operation or a read operation until the execution timing of the memory is not satisfied includes:

step 905, before the memory performs a read operation each time, increasing a delay between a second capture period of the first clock signal and a fourth capture period of the second clock signal to update the second clock signal until read data is different from write data.

In step 804 in the embodiment, determining a timing parameter of the port to be tested according to the adjusted delay specifically includes:

step 906, determining an access time parameter of the port to be tested according to a delay between the second capturing period of the first clock signal and the fourth capturing period of the second clock signal.

The access time parameter is measured to ensure that the timing of the memory performing the write operation is satisfied, that is, the delay of the first capture period of the first clock signal and the third capture period of the second clock signal is kept unchanged, and the timing of the read operation is continuously adjusted. The second clock signal is updated by adjusting the delay of the second capture period of the first clock signal and the fourth capture period of the second clock signal.

Further, in the foregoing solution, the first clock signal further includes a fourth shift period, and after the second capture period of the first clock signal, the scan chain is controlled to serially shift the read data to the off-chip device in the fourth shift period, so that the off-chip device compares the read data with the write data.

The timing parameter measurement method provided in the embodiment is specifically described by measuring an access time parameter, so that the access time parameter corresponding to each port of the memory can be obtained.

Example eight

The embodiment also provides a measuring method of the time sequence parameter of the memory. The port to be tested is a write input port, and the timing parameter further comprises a holding time parameter. The write input port comprises an input data port, a write enable port and a write address port. The embodiment can measure and obtain the maintenance time parameter corresponding to any port in the write input port.

Fig. 10 is a flowchart of a memory timing parameter measurement method according to an eighth embodiment of the present invention. As shown in fig. 10, the method further includes:

step 1001, controlling a scan trigger group corresponding to a write enable port to be triggered by a first clock edge, and controlling a scan trigger group corresponding to a write input port other than the write enable port to be triggered by a second clock edge, where the second clock edge and the first clock edge belong to a same clock cycle and the second clock edge is located before the first clock edge.

The second clock edge is a different type of clock-triggered edge, rising edge or falling edge than the first clock edge.

In the above scheme, the providing a first clock signal for a scan chain in step 801, and controlling the scan chain to serially shift a test signal into a scan flip-flop in the scan chain in a shift period of the first clock signal includes:

step 1002, controlling the scan chain to shift write configuration information in a first shift period, where the write configuration information includes port parameters in one-to-one correspondence with at least one write input port.

Step 1003, controlling the scan chain to update the port parameter corresponding to the port to be tested in the write configuration information in the first capture period and updating the write enable signal in the write configuration information into an invalid signal.

If the first clock edge is a falling edge and the second clock edge is a rising edge, the updating of the write enable signal to the invalid signal in the write configuration information may be the updating of the write enable signal to 0.

Step 1004, controlling the scan chain to shift the read configuration information in the second shift period, where the read configuration information includes port parameters in one-to-one correspondence with at least one read input port.

In the above scheme, step 802 provides a second clock signal for the memory, controls the memory to capture the test signal in a capture period of the second clock signal, performs a write operation according to the write configuration information, and performs a read operation according to the read configuration information, and specifically includes:

step 1005, controlling the memory to capture the currently stored write configuration information of the scan chain in the third capture period, and executing a write operation according to the captured write configuration information.

The input control module in this embodiment requires a high speed clock of 2 beats. At the high-speed clock of the first beat, the input control module captures the local value of the write configuration information, and at the high-speed clock of the second beat, the input control module captures the updated write configuration information. The memory captures information corresponding to each control trigger group in the input control module by adopting a one-beat high-speed clock, and executes write operation according to the captured information. For example, if the port to be tested is a value corresponding to the input data IN port IN the write configuration information is a0, the updated value corresponding to the input data IN port IN the write configuration information is a non-value of a 0. If the memory timing is satisfied, the memory writes a0, if the memory timing is not satisfied, the memory writes a0 not. It should be noted that, if the port to be tested is the other write input ports, the scan chain may update the value corresponding to the port to be tested in the write configuration information to be a non-value.

Step 1006, controlling the memory to capture the read configuration information stored in the scan chain in the second shift period in the fourth capture period, and executing a read operation according to the captured read configuration information.

When the write operation of the memory does not have hold timing violation, the data obtained by the read operation is A0; if there is a hold timing violation for a write operation to memory, the data read is the non-value of A0.

In the above scheme, step 803 updates the second clock signal by adjusting the delay between the capture period of the first clock signal and the capture period of the second clock signal when the memory performs a write operation or a read operation, until the execution timing of the memory is not satisfied, specifically including:

step 1007, before the memory performs the write operation each time, the delay between the first capture period of the first clock signal and the third capture period of the second clock signal is increased to update the second clock signal until the read data is different from the write data.

Since the hold time is the time that the data input must still be valid after the clock arrives, the hold time parameter is measured, and the timing of the write operation performed by the accessor needs to be adjusted, and the second clock signal is updated by increasing the delay of the first capture period of the first clock signal and the third capture period of the second clock signal.

The second clock signal is updated by increasing a delay between a first capture period of the first clock signal and a third capture period of the second clock signal, and the timing of the memory is violated if read data changes.

In step 804 of the above scheme, determining a timing parameter of the port to be tested according to the adjusted delay specifically includes:

step 1008 determines a holding time parameter of the port under test according to a delay between a first capture period of the first clock signal and a third capture period of the second clock signal.

Further, in step 1003 of the above scheme, the controlling the scan chain to update the port parameter corresponding to the port to be tested in the write configuration information in the first capture period and update the write enable signal in the write configuration information to an invalid signal specifically includes:

and controlling the scan chain to update the port parameter corresponding to the port to be tested in the write configuration information to be a non-value of original data in a first capturing period and update the write enable signal in the write configuration information to be an invalid signal.

For example, if the port to be tested is an input IN port, the corresponding parameter of the write enable CSN port is updated to 0, the input IN port is updated to the non-value of the corresponding parameter of the IN port IN the write configuration information, and the parameters corresponding to the other ports are maintained unchanged.

The timing parameter measurement method provided in the embodiment is specifically described by measuring the retention time parameter, and the retention time parameter corresponding to each write input port of the memory can be obtained.

Example nine

The embodiment also provides a measuring method of the time sequence parameter of the memory. In the present embodiment, the first clock signal includes a first shift period, a second shift period, a third shift period, a first capture period, a second capture period, and a fifth capture period; the second clock signal includes a third capture period, a fourth capture period, and a sixth capture period; the first capture period is between the first shift period and the third shift period, and the write operation timing of the memory is satisfied between the first capture period and the third capture period; the second capture period is after the second shift period, and the read operation timing of the memory is satisfied between the second capture period and the fourth capture period; the fifth capture period is between the third shift period and the second shift period.

The port to be tested is a write input port, and the time sequence parameter also comprises an establishing time parameter.

FIG. 11 is a flowchart illustrating a method for measuring timing parameters of a memory according to a ninth embodiment of the present invention. As shown in fig. 11, the method provides a first clock signal to a scan chain in step 801 in the above embodiment, and controls the scan chain to serially shift a test signal into scan flip-flops in the scan chain in a shift period of the first clock signal, specifically including:

step 1101, controlling the scan chain to shift a write configuration information in a first shift period, wherein the write configuration information includes port parameters corresponding to a plurality of write input ports one to one.

Step 1102, controlling the scan chain to shift another write configuration information in a third shift period, where the another write configuration information is consistent with the port parameters corresponding to the other write input ports except for updating the port parameters corresponding to the port to be tested in the write configuration information.

Step 1103, controlling the scan chain to shift read configuration information in a second shift period, where the read configuration information includes port parameters in one-to-one correspondence with the plurality of read input ports;

step 1104, controlling the memory to capture the write configuration information shifted by the scan chain in the first shift period in the third capture period, and executing a first write operation according to the captured write configuration information.

Step 1105, controlling the memory to capture the another write configuration information shifted by the scan chain in the third shift period in the sixth capture period, and executing a second write operation according to the captured another write configuration information.

In order to ensure that the time sequence parameter corresponding to the port to be measured obtained by measurement is more accurate, the values of other ports except the port to be measured can not be changed, and the method is realized by controlling the memory to execute two write operations.

Step 1106, controlling the memory to capture the read configuration information of the scan chain shifted in the second shift period in the fourth capture period, and executing the read operation according to the captured read configuration information.

In the above scheme, in step 803, updating the second clock signal by adjusting the delay between the capturing period of the first clock signal and the capturing period of the second clock signal when the memory performs a write operation or a read operation, until the execution timing of the memory is not satisfied, specifically including:

step 1107, before the memory performs the second write operation each time, the delay between the fifth capture period of the first clock signal and the sixth capture period of the second clock signal is decreased to update the second clock signal until the read data is different from the write data written by the second write operation.

Step 804 in the above scheme is to determine a timing parameter of the port to be tested according to the adjusted delay, and specifically includes:

step 1108, determining the setup time parameter of the port to be tested according to the delay between the fifth capture period of the first clock signal and the sixth capture period of the second clock signal.

Further, the first clock signal in the above embodiment further includes a fourth shift period, and after the second capture period of the first clock signal, the scan chain is controlled to serially shift the read data to the off-chip device in the fourth shift period, so that the off-chip device compares the read data with the write data.

The timing parameter measurement method provided in the embodiment is specifically described by measuring the setup time parameter, and the setup time parameter corresponding to each write input port of the memory can be obtained.

Example ten

The embodiment also provides a memory timing measurement device. The chip on which the memory is arranged is provided with at least one group of scanning trigger groups, each group of scanning trigger groups respectively corresponds to one port to be tested of the memory, and each scanning trigger group comprises at least one scanning trigger; at least one of the scan flip-flops is connected in series to form the scan trigger group, and at least one of the scan trigger groups is connected in series to form the scan chain.

Fig. 12 is a schematic structural diagram of a memory timing parameter measurement apparatus according to a tenth embodiment of the present invention. As shown in fig. 12, the apparatus 1200 for measuring the memory timing parameter includes:

a first control module 1201, configured to provide a first clock signal to the scan chain, and control the scan chain to serially shift a test signal into a scan flip-flop in the scan chain in a shift period of the first clock signal, where the test signal includes write configuration information and read configuration information;

the second control module 1202 is configured to provide a second clock signal to the memory, control the memory to capture the test signal in a capture period of the second clock signal, perform a write operation according to the configuration information, and perform a read operation according to the read configuration information.

An adjusting module 1203 is configured to update the second clock signal by adjusting a delay between a capturing period of the first clock signal and a capturing period of the second clock signal when the memory performs a write operation or a read operation until the execution timing of the memory is not satisfied.

A determining module 1204, configured to determine a timing parameter of the port to be tested according to the adjusted delay.

Further, in the above scheme, the first clock signal includes a first shift period, a second shift period, a first capture period, and a second capture period; the second clock signal includes a third capture period and a fourth capture period; the first capture period is between the first shift period and the second shift period, and the write operation timing of the memory is satisfied between the first capture period and the third capture period; the second capture period is after the second shift period, and the read operation timing of the memory is satisfied between the second capture period and the fourth capture period.

Furthermore, the port to be tested is an output port of the memory, and the time sequence parameter comprises an access time parameter; the first control module 1201 includes:

the first control submodule is used for controlling the scan chain to shift write configuration information in a first shift period, and the write configuration information comprises port parameters which are in one-to-one correspondence with at least one write input port; controlling the scan chain to shift reading configuration information in a second shift period, wherein the reading configuration information comprises port parameters in one-to-one correspondence with at least one reading input port;

the second control module 1202 includes:

the second control submodule is used for controlling the memory to capture the write configuration information shifted in by the scan chain in the first shift period in the third capture period and executing write operation according to the captured write configuration information; controlling the read configuration information which is captured by the memory in the fourth capture period and is shifted in by the scan chain in the second shift period, and executing read operation according to the captured read configuration information;

the adjustment module 1203 includes:

a first adjusting submodule, configured to increase a delay between a second capture period of the first clock signal and a fourth capture period of the second clock signal before the memory performs a read operation each time to update the second clock signal until read data is different from write data.

A determination module 1204, comprising:

and the first determining submodule is used for determining the access time parameter of the port to be tested according to the delay between the second capturing period of the first clock signal and the fourth capturing period of the second clock signal.

Optionally, the port to be tested is a write input port, and the timing parameter further includes a hold time parameter. The first control module 1201 further includes:

a third control sub-module, configured to control a scan trigger group corresponding to the write enable port to be triggered by a first clock edge, and control a scan trigger group corresponding to the write input port other than the write enable port to be triggered by a second clock edge, where the second clock edge and the first clock edge belong to a same clock cycle and the second clock edge is located before the first clock edge; controlling the scan chain to shift write configuration information in a first shift period, wherein the write configuration information comprises port parameters in one-to-one correspondence with at least one write input port; controlling the scan chain to update the port parameter corresponding to the port to be tested in the write configuration information in a first capturing period and updating the write enable signal in the write configuration information into an invalid signal; controlling the scan chain to shift reading configuration information in a second shift period, wherein the reading configuration information comprises port parameters in one-to-one correspondence with at least one reading input port;

the second control module 1202 further includes:

the fourth control submodule is used for controlling the memory to capture the write configuration information currently stored in the scan chain in the third capture period and executing write operation according to the captured write configuration information; and controlling the memory to capture the read configuration information stored in the scan chain in the second shift period in the fourth capture period, and executing a read operation according to the captured read configuration information.

The adjusting module 1203 further includes:

and a second adjusting submodule for increasing a delay between a first capture period of the first clock signal and a third capture period of the second clock signal before each write operation is performed on the memory to update the second clock signal until read data is different from write data.

The determining module 1204 further includes:

and the second determining submodule is used for determining the maintenance time parameter of the port to be tested according to the delay between the first capturing period of the first clock signal and the third capturing period of the second clock signal.

Preferably, the third control sub-module is further configured to control the scan chain to update the port parameter corresponding to the port to be tested in the write configuration information to a non-value of the original data in the first capture period, and update the write enable signal in the write configuration information to an invalid signal.

Optionally, in the above scheme, the first clock signal includes a first shift period, a second shift period, a third shift period, a first capture period, a second capture period, and a fifth capture period; the second clock signal includes a third capture period, a fourth capture period, and a sixth capture period; the first capture period is between the first shift period and the third shift period, and the write operation timing of the memory is satisfied between the first capture period and the third capture period; the second capture period is after the second shift period, and the read operation timing of the memory is satisfied between the second capture period and the fourth capture period; the fifth capture period is between the third shift period and the second shift period.

Further, the port to be tested is a write input port, and the timing parameter further includes an establishment time parameter.

The first control module 1201 further includes:

a fifth control submodule, configured to control the scan chain to shift write configuration information in the first shift period, where the write configuration information includes port parameters in one-to-one correspondence with the plurality of write input ports; controlling the scan chain to shift another write configuration information in a third shift period, wherein the other write configuration information and the port parameter corresponding to the port to be tested in the write configuration information are kept consistent except for updating the port parameter corresponding to the port to be tested; controlling the scan chain to shift reading configuration information in a second shift period, wherein the reading configuration information comprises port parameters in one-to-one correspondence with a plurality of reading input ports;

the second control module 1202 further includes:

a sixth control submodule, configured to control the memory to capture the write configuration information shifted by the scan chain in the first shift period in the third capture period, and execute a first write operation according to the captured write configuration information; controlling the memory to capture the other write configuration information shifted by the scan chain in the third shift period in the sixth capture period, and executing a second write operation according to the captured other write configuration information; and controlling the read configuration information of the scan chain shifted in the second shift period, captured by the memory in the fourth capture period, and executing a read operation according to the captured read configuration information.

The adjusting module 1203 further includes:

and the third adjusting submodule is used for reducing the delay between the fifth capture period of the first clock signal and the sixth capture period of the second clock signal before the memory performs the second write operation each time to update the second clock signal until the read data is different from the write data written by the second write operation.

The determining module 1204 further includes:

and the third determining submodule is used for determining the set-up time parameter of the port to be tested according to the delay between the fifth capture period of the first clock signal and the sixth capture period of the second clock signal.

Further, in the embodiment, the first clock signal further includes a fourth shift period, and after the second capture period of the first clock signal, the scan chain is controlled to serially shift the read data to the off-chip device in the fourth shift period, so that the off-chip device compares the read data with the write data.

The apparatus for measuring a memory timing parameter provided in this embodiment may be used to implement any of the schemes in the sixth to ninth embodiments, and the specific implementation process and beneficial effects thereof are similar to those in the embodiments described above, and are not described herein again.

EXAMPLE eleven

The embodiment also provides a device and a method for measuring the time sequence parameters of the memory. The present embodiment is explained by specific examples. Fig. 13 is a schematic connection diagram of a measuring apparatus for memory timing parameters and a memory according to an eleventh embodiment of the invention.

As shown in fig. 13, the measurement apparatus 1300 includes a scan chain 1301, a clock control module 1302, an input control module 1303, and a sustain control module 1304.

The clock control module 1302 is coupled to the scan chain 1301, the input control module 1303 and the memory 1305, and provides a first clock signal CLK1 to the scan chain 1301, a second clock signal CLK2 to the memory 1305, and a third clock signal CLK3 to the input control module 1303.

The memory 1305 includes a write enable WEN port, a chip select enable CSN port, an input data IN port, a write address WADDR port, a read enable REN port, a read address RADDR port, and an output data port OUT.

The scan chain 1301 includes a write enable trigger group WEN _ S1306, a chip select trigger group CSN _ S1307, an input data trigger group IN _ S1308, a write address port trigger group WADDR _ S1309, a read enable trigger group REN _ S1310, a read address trigger group RADDR _ S1311, and an output data trigger group OUT _ S1312. Correspondingly, the input control module 1303 includes trigger groups corresponding to the input ports of the memory 1305 in a one-to-one manner.

The write enable trigger group WEN _ S1306 of the scan chain 1301 is located at the top of each trigger group, so that when the retention time of the memory 1305 is measured, the falling edge of the write enable trigger group WEN _ S1306 triggers and captures a0 value in the input write configuration information, and the rising edge captures a non-value of the corresponding parameter of the port to be tested in the write configuration information and the remaining trigger groups capture the present value of the corresponding parameter.

The maintenance control module 1303 is configured to control the scan chain 1301, so that each trigger group of the scan chain 1301 captures a corresponding value of the write configuration information.

The clock control module 1302 includes a clock delay chain.

It should be noted that, in this embodiment, only a 1-port memory is used for explanation, and for a memory larger than 1 port, in the measurement apparatus, the scan chain further includes a corresponding port trigger group, and the input control module further includes a trigger group corresponding to a corresponding input port.

The following description will be made for the measurement of different timing parameters.

Measurement of access time:

FIG. 14 is a flowchart illustrating a method for measuring memory access time according to an eleventh embodiment of the present invention. As shown in fig. 14, the method specifically includes the following steps:

in step 1401, the clock delay chain is configured according to a first delay control signal input by a user, so that CLK2 is different from CLK3 by a high-speed clock period T.

In this configuration, the read and write timing of the memory is fully satisfied, i.e., there is no timing violation.

Step 1402, IN the scan shift mode, serially shift the write configuration information into the scan trigger group through the scan chain, so that CSN _ S is 0, WEN _ S is 1, WADDR _ S is the predetermined address a0, and IN _ S is the predetermined data D0.

Wherein the scan shift mode, i.e., the scan enable of the scan chain, is 1.

Step 1403, switching to the scan capture mode, and the memory completes the write operation according to the write configuration information in step 1402.

Wherein the scan capture mode, i.e., the scan enable of the scan chain, is 0. The memory needs a high-speed clock of 1 beat to perform the write operation.

In step 1404, the clock delay chain is configured according to a second delay control signal input by the user, so that the difference between CLK2 and CLK3 is T + n × T (n is the number of stages the clock delay chain increases, and is initially 0).

Step 1405, switching to the scan shift mode, and serially shifting the read configuration information into the scan trigger group through the scan chain, so that CSN _ S is 0, REN _ S is 1, and RADDR _ S is the predetermined address a 0.

And step 1406, switching to a scanning capture mode to finish the reading operation of the memory.

The memory performs a read operation requiring a high speed PLL clock of 3 beats.

Step 1407, switching to the scan shift mode, serially shifting OUT the data captured IN the OUT _ S trigger group to the off-chip device for monitoring, and determining whether the data read from the OUT port is the same as the predetermined data written into the IN port.

Whether the data read from the OUT port is the same as the predetermined data written from the IN port is judged, whether the read data is D0 is actually judged, if yes, the data are the same, and if not, the data are different, and the time sequence is violated.

Step 1408, if the data read from the OUT port is the same as the predetermined data written from the IN port of the present cycle, it indicates T_access+T_{setup_dff}<T-n × T, n — n +1, and steps 1401 to 1407 are repeatedly performed.

Wherein, T_{setup_dff}The setup requirement of the trigger set corresponding to the OUT port, that is, the OUT _ S trigger set, is known by the mature technology library.

FIG. 15 is a timing diagram of access time and clock according to an eleventh embodiment of the present invention. As shown in fig. 15, to reduce T_accessNeeds to continue to shift CLK2 to the right. CLK3 is unchanged and right-shifts CLK2, i.e., increases the delay between CLK2 and CLK 3. The delay between CLK2 and CLK3 may be increased by increasing n in step 1404, so as to adjust the delay step by step.

Step 1409, if the read data and the write data of the OUT port are different, this indicates that T is_access+T_{setup_dff}T-n T, from which T-n T-T is obtained_{setup_dff}<T_access<T-(n-1)*t-T_{setup_dff}(ii) a When the precision T of the clock delay chain is small, T-n x T-T_setup-dffIs T_access。

The access time measured by the embodiment is an access time parameter of the OUT port of the memory.

Measurement of set-up time:

fig. 16 is a flowchart of a memory setup time measurement method according to an eleventh embodiment of the present invention. As shown in fig. 16, the method specifically includes the following steps:

step 1601, the clock delay chain is configured according to a first delay control signal input by a user to make CLK2 different from CLK3 by T.

IN the scan shift mode, IN step 1602, the first write configuration information is serially shifted into the scan trigger group through the scan chain, so that CSN _ S is 0, WEN _ S is 1, WADDR _ S is the predetermined address a0, and IN _ S is the predetermined data D0.

Step 1603, switching to a scan capture mode, and completing the write operation by the memory according to the first write configuration information in step 1602.

The memory needs a high-speed clock of 1 beat to perform the write operation.

At step 1604, the clock delay chain is configured according to a second delay control signal input by the user, such that the difference between CLK2 and CLK3 is T-n × T (n is the number of stages of the clock delay chain, and is initially 0).

IN step 1605, IN the scan shift mode, the second write configuration information is serially shifted into the scan trigger group through the scan chain, so that CSN _ S is 0, WEN _ S is 1, WADDR _ S is the predetermined address a0, and IN _ S is the predetermined data D1.

And step 1606, switching to the scan capture mode, and completing the write operation by the memory according to the second write configuration information in step 1605.

In step 1607, the clock delay chain is configured according to the third delay control signal input by the user, so that the difference between CLK2 and CLK3 is T, and the read operation timing is guaranteed to be satisfied.

Step 1608, switching to scan shift mode, serially shifting the read configuration information into the scan trigger group through the scan chain, so that CSN _ S is 0, REN _ S is 1, and RADDR _ S is the predetermined address a 0.

Step 1609, switching to the scan capture mode, and completing the read operation of the memory.

Step 1610, switching to a scan shift mode, serially shifting OUT the data captured in the OUT _ S trigger group to an off-chip device for monitoring, and determining whether the data read from the OUT port is the same as the predetermined data written in the second write operation.

Here, it is determined whether the data read from the OUT port is identical to the predetermined data written by the second write operation, and it is actually determined whether the read data is D1, D1 is identical, and D0 is different.

Step 1611, if the data read from the OUT port is the same as the predetermined data written by the second write operation, it indicates that the second write operation timing is satisfied, i.e. T_{clk_to_q_dff}+T_setup<T-n T; n +1, and repeatedly performs steps 1602 to 1610.

Wherein, T_{clk_to_q_dff}The clk _ to _ q delay for the IN _ S trigger set is known from the mature process library.

IN the embodiment, the measured setup time is the setup time corresponding to the IN port of the memory, and since the timing parameter is the setup time of the IN port of the memory, IN one cycle of the measurement scheme, the measurement scheme includes 2 write operations and 1 read operation. The first write operation, that is, the write operation according to the first write configuration information, is to make the write address port and the write enable port have assigned values before the second write operation is performed, so as to ensure that the measured setup time of the IN terminal is more accurate.

Fig. 17 is a timing diagram of establishing a time-to-clock relationship according to an eleventh embodiment of the present invention. As shown in fig. 17, to reduce T_setupNeeds to continue to shift CLK2 to the left. CLK3 is unchanged, shifting CLK2 to the left reduces the delay between CLK2 and CLK 3. Which decreases the delay between CLK2 and CLK3 may be a step-wise adjustment by increasing the value of n in step 1604 above.

If the data read from the OUT port is changed from D1 to D0, step 1612, it indicates that the write operation timing is not satisfied, i.e. T_{clk_to_q_dff}+T_setup>T-n T, thereby obtaining T-n T-T_{clk_to_q_dff}<T_setup<T-(n-1)*t-T_{clk_to_q_dff}(ii) a When in useWhen the precision T of the clock delay chain is small, T-n x T-T_{clk_to_q_dff}Is T_setup。

Measurement of the holding time:

fig. 18 is a flowchart of a memory retention time measurement method according to an eleventh embodiment of the present invention. As shown in fig. 18, the method specifically includes the following steps:

step 1801, configure the sustain time parameter measurement control signal so that the IN _ S trigger group captures its own non-value, the WEN _ S trigger group captures its 0 value, and the other scan trigger groups capture their own values.

At step 1802, the clock delay chain is configured according to a first delay control signal input by a user, such that CLK2 differs from CLK3 by T + n × T (n is the number of stages the clock delay chain increases, and is initially 0).

Step 1803, IN the scan shift mode, the write configuration information is serially shifted into the scan trigger group through the scan chain, so that CSN _ S is 0, WEN _ S is 1, WADDR _ S is the predetermined address a0, and IN _ S is the predetermined data D0.

And 1804, switching to a scanning capture mode, and finishing the writing operation by the memory according to the writing configuration information.

This step requires a 2 beat high speed clock.

In the scanning capture mode, namely a first capture period, the input control module captures the first writing configuration information and transmits the first writing configuration information to the corresponding port of the memory in parallel; in the first capture period, the input data trigger group of the scan trigger group captures a non-value of the write data D0, the write enable trigger group captures a0 value of the write enable, and the other trigger groups capture original values of corresponding information and transmit the original values to the memory in parallel through the input control module. If the write operation of the memory does not generate hold timing violation, the memory writes data D0 to an address A0 at the rising edge of the first beat high-speed clock of CLK 2; if a hold timing violation occurs, the memory writes the NOT value of the data D0 to address A0.

Note that in the scan trigger set, the write enable trigger set captures that the 0 value of the write enable occurs at the negative edge of CLK1, thus ensuring that no hold timing violation occurs at the write enable.

At step 1805, the clock delay chain is configured according to the second delay control signal input by the user, so that the difference T between CLK2 and CLK3 is ensured, and the timing of the next read operation is satisfied.

Step 1806, switch to scan shift mode, serially shift the read configuration information into the scan trigger group through the scan chain, so that CSN _ S is 0, REN _ S is 1, and RADDR _ S is the predetermined address a 0.

The assignment of RADDR _ S in this step is the same as the configuration of WADDR _ S described above.

Step 1807, switching to the scan capture mode, and completing the read operation of the memory.

Step 1808, switching to the scan shift mode, serially shifting OUT the data captured IN the OUT _ S trigger group for monitoring, and determining whether the data read from the OUT port is the same as the predetermined data written IN the IN port.

Here, it is determined whether or not the data read from the OUT port is identical to the predetermined data written IN the IN port, and it is actually determined whether or not the read data is D0, and if it is D0, the data is identical, and if it is not D0, it indicates a difference.

Step 1809, if the data read from the OUT port is the same as the predetermined data written from the IN port, it indicates that the hold timing of the write operation is satisfied, i.e. T_{clk_to_q_dff}-n*t>T_hold(ii) a n +1, and steps 1802 to 1808 are repeatedly performed.

Wherein, T_{clk_to_q_dff}Clk _ to _ q delay, referred to as IN _ S trigger set, is from the mature process library.

The data read by the OUT port is the same as the predetermined data written by the IN port, i.e., the data read is D0.

FIG. 19 is a timing diagram of the hold time and the clock according to the eleventh embodiment of the present invention. As shown in fig. 19, to reduce T_holdNeeds to continue to shift CLK2 to the right. CLK3 is unchanged and right-shifts CLK2, i.e., increases the delay between CLK2 and CLK 3. It increases the delay between CLK2 and CLK3, which may be a step-by-step adjustment by increasing the value of n in step 1802 above.

Step 1810, if the data read by the OUT port changes from D0 to D0, it indicates that the hold timing of the write operation is not satisfied, i.e. T_{clk_to_q_dff}-n*t<T_holdThereby obtaining T_{clk_to_q_dff}-n*t<T_hold<T_{clk_to_q_dff}- (n-1) × t; when the precision T of the clock delay chain is small, T_{clk_to_q_dff}-n x T is T_hold。

The measured retention time of the present embodiment is the retention time of the IN port of the memory.

In this embodiment, the above embodiments are explained by using specific examples and different timing parameter measurement methods, and the beneficial effects are similar to those of the above embodiments and are not described herein again.

It should be noted that, although the solution provided in the embodiment of the present invention is to measure the timing parameters of the memory with a single port, the measurement method in the embodiment of the present invention can also measure the memory with two or more ports, and only needs to add the corresponding trigger group. The specific implementation process is similar to the above implementation process, and is not described herein again.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An apparatus for measuring timing parameters of a memory, comprising: a scan chain and a clock control module; wherein,

the scan chain comprises at least one group of scan trigger groups arranged on a chip where the memory is located, each group of scan trigger groups respectively corresponds to a port to be tested of the memory, and each scan trigger group comprises at least one scan trigger; at least one of the scan flip-flops is connected in series to form the scan trigger group, and at least one of the scan trigger groups is connected in series to form the scan chain; the scan chain is used for providing a test signal for the memory; the test signal comprises write configuration information and read configuration information and is used for indicating the memory to execute write operation according to the write configuration information and execute read operation according to the read configuration information;

2. The apparatus of claim 1, further comprising an input control module disposed between the scan chain and the memory;

the clock control module is further configured to provide a third clock signal to the input control module, where the third clock signal is a clock signal without a shift period compared to the first clock signal;

the input control module is used for capturing the currently stored data of the scan chain in the capturing period of the third clock signal, and providing the currently stored data of the input control module for the memory in the capturing period of the second clock signal.

3. The apparatus of claim 2, wherein the input control module comprises a set of control triggers in one-to-one correspondence with input ports of the memory; the control trigger group comprises at least one control trigger.

4. The apparatus according to any one of claims 1 to 3,

the scan chain comprises a first sub scan chain and a second sub scan chain, wherein the input end of the first sub scan chain is used as the input end of the scan chain, the output end of the first sub scan chain is connected with the input end of the second sub scan chain, and the output end of the second sub scan chain is used as the output end of the scan chain;

the first sub scan chain comprises at least one first scan trigger group, the first scan trigger group corresponds to a write enable port of the memory, and the first scan trigger groups are triggered by first clock edges;

the second sub scan chain comprises at least one second scan trigger group, the second scan trigger group corresponds to a port except the write enable port in the memory port, the second scan trigger groups are triggered by a second clock edge, the second clock edge and the first clock edge belong to the same clock cycle, and the second clock edge is positioned before the first clock edge;

the apparatus also includes a maintenance control module;

the maintaining control module is connected with the scan chain and used for sending a maintaining control signal to the scan chain so as to control the scan chain to update the data stored in the second scan trigger group according to the maintaining control signal in the capturing period of the first clock signal and update the write enable signal stored in the first scan trigger group to be invalid.

5. The apparatus of claim 4, wherein the maintenance control module comprises: a first control unit and a decoder; wherein,

the output end of the first control unit is connected with the input end of each first scanning trigger group and used for providing a writing enable signal with invalid writing enable for the first sub scanning chain;

the input end of the decoder is used for receiving information of a port to be detected, the decoder comprises output ends in one-to-one correspondence with second scanning trigger groups in the second sub scanning chain, each output end of the decoder is connected with the input end of each second scanning trigger group through an alternative selector, the output end of the decoder is connected with the control end of the alternative selector, the first input end of the alternative selector is connected with the output end of the second scanning trigger group corresponding to the alternative selector through a phase inverter, and the second input end of the alternative selector is directly connected with the output end of the second scanning trigger group corresponding to the alternative selector.

6. The apparatus of claim 4, wherein the control trigger groups corresponding to the write enable ports of the memory in the input control module are all triggered by a first clock edge;

and the control trigger groups corresponding to the ports of the memory except the write enable port in the input control module are all triggered by a second clock edge.

7. The apparatus of claim 1, wherein the scan chain comprises a third sub-scan chain comprising at least one third scan trigger group; the third scan trigger set corresponds to an output port of the memory;

the third scanning trigger group is used for capturing read data acquired by executing a read operation and shifting the read data to an off-chip device so that the off-chip device compares the read data with write data written by a write operation executed before the read operation is executed, and when the read data is different from the write data, the execution time sequence of the memory is not satisfied.

8. The apparatus of claim 1, wherein the clock control module comprises: the clock control unit on chip, the first clock delay chain, delay chain control unit;

the on-chip clock control unit is used for providing a first clock signal for the scan chain according to the type of the time sequence parameter to be tested of the port to be tested;

the on-chip clock control unit is further configured to provide a second clock signal for the memory through the first clock delay chain according to the type of the timing sequence parameter to be detected of the port to be detected;

a first input end of the first clock delay chain is used for receiving the first clock signal, a second input end of the first clock delay chain is connected with the delay chain control unit and used for receiving a clock delay control signal, and an output end of the first clock delay chain is used for outputting the second clock signal;

the delay chain control unit is configured to generate the clock delay control signal until the execution timing of the memory is not satisfied when the execution timing of the memory is satisfied, so that the first clock delay chain updates the second clock signal according to the clock delay control signal and generates an adjusted delay.

9. The apparatus of claim 8, wherein the clock control module further comprises: a second clock delay chain having the same delay chain structure as the first clock delay chain;

the output end of the second clock delay chain is connected with the first input end of the second clock delay chain through a phase inverter, the second input end of the second clock delay chain is connected with the delay chain control unit, and the period of a clock signal output by the output end of the second clock delay chain is twice of the adjusted delay.

10. A memory chip comprising the memory timing parameter measuring device according to any one of claims 1 to 9.

11. A measuring method of memory time sequence parameters is characterized in that at least one group of scanning trigger groups is arranged on a chip where a memory is arranged, each group of scanning trigger groups respectively corresponds to a port to be measured of the memory, and each scanning trigger group comprises at least one scanning trigger; at least one of the scan flip-flops is connected in series to form the scan trigger group, and at least one of the scan trigger groups is connected in series to form the scan chain; the method comprises the following steps:

12. The method of claim 11, wherein the first clock signal comprises a first shift period, a second shift period, a first acquisition period, and a second acquisition period; the second clock signal includes a third capture period and a fourth capture period; the first capture period is between the first shift period and the second shift period, and a write operation timing of the memory is satisfied between the first capture period and the third capture period; the second capture period is after the second shift period, and a read operation timing of the memory is satisfied between the second capture period and the fourth capture period.

13. The method of claim 12, wherein the port under test is an output port of the memory, and the timing parameter comprises an access time parameter;

the providing a first clock signal for the scan chain, controlling the scan chain to serially shift a test signal into a scan flip-flop in the scan chain during a shift period of the first clock signal, comprises:

controlling the scan chain to shift write configuration information in a first shift period, wherein the write configuration information comprises port parameters in one-to-one correspondence with at least one write input port;

controlling the scan chain to shift read configuration information in a second shift period, wherein the read configuration information comprises port parameters in one-to-one correspondence with at least one read input port;

the providing a second clock signal for the memory, controlling the memory to capture the test signal in a capture period of the second clock signal, executing a write operation according to the write configuration information, and executing a read operation according to the read configuration information includes:

controlling the memory to capture the write configuration information shifted in by the scan chain in the first shift period in the third capture period, and executing write operation according to the captured write configuration information;

controlling the read configuration information which is captured by the memory in the fourth capture period and is shifted in by the scan chain in the second shift period, and executing read operation according to the captured read configuration information;

the updating the second clock signal by adjusting a delay between a capture period of the first clock signal and a capture period of the second clock signal when the memory performs a write operation or a read operation until an execution timing of the memory is not satisfied, including:

before the memory performs a read operation each time, increasing a delay between a second capture period of the first clock signal and a fourth capture period of the second clock signal to update the second clock signal until read data is different from write data;

the determining the timing parameter of the port to be tested according to the adjusted delay includes:

and determining an access time parameter of the port to be tested according to the delay between the second capture period of the first clock signal and the fourth capture period of the second clock signal.

14. The method of claim 12, wherein the port under test is a write input port, and the timing parameters further include a hold time parameter;

the method further comprises the following steps:

controlling a scanning trigger group corresponding to a write enable port to be triggered by a first clock edge, and controlling a scanning trigger group corresponding to a write input port except the write enable port to be triggered by a second clock edge, wherein the second clock edge and the first clock edge belong to the same clock cycle and the second clock edge is positioned in front of the first clock edge;

the providing a first clock signal to the scan chain, controlling the scan chain to serially shift a test signal into a scan trigger group in the scan chain during a shift period of the first clock signal, comprises:

controlling the scan chain to update the port parameter corresponding to the port to be tested in the write configuration information in a first capture period and updating a write enable signal in the write configuration information into an invalid signal;

controlling the memory to capture the write configuration information currently stored in the scan chain in the third capture period, and executing write operation according to the captured write configuration information;

controlling the memory to capture the read configuration information stored in the scan chain in the second shift period in the fourth capture period, and executing a read operation according to the captured read configuration information;

before the memory performs a write operation each time, increasing a delay between a first capture period of the first clock signal and a third capture period of the second clock signal to update the second clock signal until read data is different from write data;

and determining a maintenance time parameter of the port to be tested according to the delay between the first capture period of the first clock signal and the third capture period of the second clock signal.

15. The method according to claim 14, wherein the controlling the scan chain to update the port parameter corresponding to the port to be tested in the write configuration information and update the write enable signal in the write configuration information to an invalid signal in the first capture period comprises:

and controlling the scan chain to update the port parameter corresponding to the port to be tested in the write configuration information to be a non-value of original data in a first capture period and update the write enable signal in the write configuration information to be an invalid signal.

16. The method of claim 11, wherein the first clock signal comprises a first shift period, a second shift period, a third shift period, a first acquisition period, a second acquisition period, and a fifth acquisition period; the second clock signal includes a third capture period, a fourth capture period, and a sixth capture period; the first capture period is between the first shift period and the third shift period, and a write operation timing of a memory is satisfied between the first capture period and the third capture period; the second capture period is after the second shift period, and the read operation timing of the memory is satisfied between the second capture period and the fourth capture period; the fifth capture period is located between the third shift period and the second shift period.

17. The method of claim 16, wherein the port under test is a write input port, and the timing parameters further include setup time parameters;

controlling the scan chain to shift write configuration information in a first shift period, wherein the write configuration information comprises port parameters which are in one-to-one correspondence with a plurality of write input ports;

controlling the scan chain to shift another write configuration information in a third shift period, wherein the another write configuration information is consistent with the port parameters corresponding to other write input ports except the port parameters corresponding to the port to be tested in the write configuration information;

controlling the scan chain to shift read configuration information in a second shift period, wherein the read configuration information comprises port parameters in one-to-one correspondence with a plurality of read input ports;

controlling the memory to capture the write configuration information shifted by the scan chain in the first shift period in the third capture period, and executing a first write operation according to the captured write configuration information;

controlling the memory to capture the other write configuration information shifted by the scan chain in the third shift period in the sixth capture period and to perform a second write operation according to the captured other write configuration information;

controlling the read configuration information of the scan chain, captured by the memory in the fourth capture period, shifted in the second shift period, and executing a read operation according to the captured read configuration information;

before the memory performs a second write operation each time, reducing a delay between a fifth capture period of the first clock signal and a sixth capture period of the second clock signal to update the second clock signal until read data and write data written by the second write operation are different;

and determining the establishing time parameter of the port to be tested according to the delay between the fifth capturing period of the first clock signal and the sixth capturing period of the second clock signal.

18. The method of any of claims 12-17, wherein the first clock signal further comprises a fourth shift period, the fourth shift period being subsequent to the second capture period of the first clock signal, the scan chain being controlled to serially shift the read data to an off-chip device during the fourth shift period to cause the off-chip device to compare the read data to the write data.

19. A measuring device for time sequence parameters of a memory is characterized in that at least one group of scanning trigger groups is arranged on a chip where the memory is located, each group of scanning trigger groups respectively corresponds to a port to be measured of the memory, and each scanning trigger group comprises at least one scanning trigger; at least one of the scan flip-flops is connected in series to form the scan trigger group, and at least one of the scan trigger groups is connected in series to form the scan chain; the measuring device comprises:

20. The apparatus of claim 19, wherein the first clock signal comprises a first shift period, a second shift period, a first acquisition period, and a second acquisition period; the second clock signal includes a third capture period and a fourth capture period; the first capture period is between the first shift period and the second shift period, and a write operation timing of the memory is satisfied between the first capture period and the third capture period; the second capture period is after the second shift period, and a read operation timing of the memory is satisfied between the second capture period and the fourth capture period.

21. The apparatus of claim 20, wherein the port under test is an output port of a memory, and the timing parameter comprises an access time parameter; the first control module includes:

the first control submodule is used for controlling the scan chain to shift write configuration information in a first shift period, and the write configuration information comprises port parameters which are in one-to-one correspondence with at least one write input port; controlling the scan chain to shift read configuration information in a second shift period, wherein the read configuration information comprises port parameters in one-to-one correspondence with at least one read input port;

the second control module includes:

the adjustment module includes:

a first adjusting submodule, configured to increase a delay between a second capture period of the first clock signal and a fourth capture period of the second clock signal before the memory performs a read operation each time to update the second clock signal until read data is different from write data;

the determining module includes:

22. The apparatus of claim 20, wherein the port under test is a write input port, and the timing parameters further comprise a hold time parameter;

the first control module further comprises:

a third control sub-module, configured to control a scan trigger group corresponding to a write enable port to be triggered by a first clock edge, and control a scan trigger group corresponding to a write input port other than the write enable port to be triggered by a second clock edge, where the second clock edge and the first clock edge belong to a same clock cycle and the second clock edge is located before the first clock edge; controlling the scan chain to shift write configuration information in a first shift period, wherein the write configuration information comprises port parameters in one-to-one correspondence with at least one write input port; controlling the scan chain to update the port parameter corresponding to the port to be tested in the write configuration information in a first capture period and updating a write enable signal in the write configuration information into an invalid signal; controlling the scan chain to shift read configuration information in a second shift period, wherein the read configuration information comprises port parameters in one-to-one correspondence with at least one read input port;

the second control module further comprises:

the fourth control submodule is used for controlling the memory to capture the write configuration information currently stored in the scan chain in the third capture period and executing write operation according to the captured write configuration information; controlling the memory to capture the read configuration information stored in the scan chain in the second shift period in the fourth capture period, and executing a read operation according to the captured read configuration information;

the adjusting module further comprises:

a second adjusting submodule, configured to increase a delay between a first capture period of the first clock signal and a third capture period of the second clock signal before the memory performs a write operation each time to update the second clock signal until read data is different from write data;

the determining module further comprises:

23. The apparatus of claim 22,

the third control sub-module is configured to control the scan chain to update the port parameter corresponding to the port to be tested in the write configuration information to a non-value of the original data in the first capture period and update the write enable signal in the write configuration information to an invalid signal.

24. The apparatus of claim 19, wherein the first clock signal comprises a first shift period, a second shift period, a third shift period, a first acquisition period, a second acquisition period, and a fifth acquisition period; the second clock signal includes a third capture period, a fourth capture period, and a sixth capture period; the first capture period is between the first shift period and the third shift period, and a write operation timing of a memory is satisfied between the first capture period and the third capture period; the second capture period is after the second shift period, and the read operation timing of the memory is satisfied between the second capture period and the fourth capture period; the fifth capture period is located between the third shift period and the second shift period.

25. The apparatus of claim 24, wherein the port under test is a write input port, and the timing parameters further comprise setup time parameters;

the first control module further comprises:

a fifth control submodule, configured to control the scan chain to shift write configuration information in a first shift period, where the write configuration information includes port parameters in one-to-one correspondence with multiple write input ports; controlling the scan chain to shift another write configuration information in a third shift period, wherein the another write configuration information is consistent with the port parameters corresponding to other write input ports except for updating the port parameters corresponding to the port to be tested in the write configuration information; controlling the scan chain to shift read configuration information in a second shift period, wherein the read configuration information comprises port parameters in one-to-one correspondence with a plurality of read input ports;

the second control module further comprises:

a sixth control submodule, configured to control the memory to capture the write configuration information shifted by the scan chain in the first shift period in the third capture period, and execute a first write operation according to the captured write configuration information; controlling the memory to capture the other write configuration information shifted by the scan chain in the third shift period in the sixth capture period and to perform a second write operation according to the captured other write configuration information; controlling the read configuration information of the scan chain, captured by the memory in the fourth capture period, shifted in the second shift period, and executing a read operation according to the captured read configuration information;

the adjusting module further comprises:

a third adjusting submodule, configured to reduce a delay between a fifth capture period of the first clock signal and a sixth capture period of the second clock signal before each second write operation is performed on the memory, so as to update the second clock signal until read data is different from write data written by the second write operation;

the determining module further comprises:

and the third determining submodule is used for determining the establishment time parameter of the port to be tested according to the delay between the fifth capturing period of the first clock signal and the sixth capturing period of the second clock signal.

26. The apparatus of any of claims 20-25, wherein the first clock signal further comprises a fourth shift period, subsequent to the second capture period of the first clock signal, to control the scan chain to serially shift the read data to an off-chip device in the fourth shift period to cause the off-chip device to compare the read data to the write data.