CN106991022B

CN106991022B - Chip analysis method based on scan chain

Info

Publication number: CN106991022B
Application number: CN201710132264.6A
Authority: CN
Inventors: 赵胜平
Original assignee: Ramaxel Technology Shenzhen Co Ltd
Current assignee: Ramaxel Technology Shenzhen Co Ltd
Priority date: 2017-03-07
Filing date: 2017-03-07
Publication date: 2020-12-18
Anticipated expiration: 2037-03-07
Also published as: CN106991022A

Abstract

The invention discloses a chip analysis method based on a scan chain, which is characterized in that a common register needing to be stored in a CPU is replaced by a register with scan input, when the CPU is abnormal, a serial scan trigger instruction is output through a JTAG (joint test action group) to start the data storage operation of the scan chain, the data series with the scan input register is output to a debugging host through a JTAG port, a debugger analyzes the data received by each register with scan input by the debugging host, and after the analysis is finished, the reset operation is carried out on the CPU by controlling a JTAG output control reset signal to control the CPU to recover the normal work. The method of the scan chain mechanism can realize that the state of the main register of the chip can be read out quickly and conveniently when the CPU is abnormal, and the abnormal CPU can be analyzed quickly and positioned by matching with a JTAG tool, so that the development efficiency can be greatly improved.

Description

Chip analysis method based on scan chain

Technical Field

The invention relates to the field of information electronic chip design, in particular to a chip analysis method based on a scan chain.

Background

In the development process of embedded products, software design and debugging are an important link in the development. Any software needs to be debugged for many times before being fixed, and in order to improve the design efficiency, many chip design companies synchronously design debugging tools of the software. Basically, all kinds of debugging tools are similar to those of debugging tools which directly communicate with a CPU and control the execution of programs through a JTAG (an international standard test protocol which is mainly used for chip internal test) port. For example, single step debugging, one premise of such debugging is that the CPU itself is working normally, and if the CPU itself has a problem or an abnormality, the state of various types of software or the CPU is lost, and the problem cannot be located. When the condition occurs, the current state of the CPU needs to be accurately acquired, and the reason of the abnormality or the error of the software or the CPU can be further analyzed. Existing JTAG tools do not fulfill this need well for existing chip designs.

Disclosure of Invention

Aiming at the defects, the invention aims to quickly locate the internal problems of the chip when the CPU is abnormal, save debugging time and eliminate the problems of manufacturing and time sequence.

In order to achieve the above purpose, the invention provides a chip analysis method based on scan chain, which is characterized in that a common register needing to be stored in a CPU is replaced by a scan input register, when the CPU is abnormal, a serial scan trigger instruction is output through JTAG, the data storage operation of the scan chain is started, the data serial with the scan input register is output to a debugging host through a JTAG port, a debugger analyzes the data received by the debugging host and provided with the scan input register, and after the analysis is finished, the reset operation is carried out on the CPU by controlling JTAG output control reset signal, and the CPU is controlled to recover the normal work.

The chip analysis method based on the scan chain is characterized in that a data selector is additionally arranged in front of a data input port of a common register of the scan input register, and the data selector comprises a data input port, a scan input port and a scan enable control port; the band scan input register further includes a clock input port and a scan output port.

The chip analysis method based on the scan chain is characterized in that the scan input registers are connected in series, the scan output port of the previous scan input register is connected with the scan input port of the next scan input register, and the clock input ports of all the scan input registers are connected together; all scan enable control ports with scan input registers are connected together.

The invention can realize the quick and convenient reading of the state of the main register of the chip when the CPU is abnormal by a method of a scan chain mechanism, and can realize the quick analysis and problem positioning of the abnormal CPU by matching with a JTAG tool, thereby greatly improving the development efficiency.

Drawings

FIG. 1 is a schematic diagram of a tape scan input register;

FIG. 2 is a schematic diagram of scan chain connections in a CPU;

FIG. 3 is a scan chain based chip analysis state transition diagram.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

FIG. 1 is a schematic diagram of a tape scan input register; the Data selector MUX is additionally arranged In front of a Data input port of the common register FF and comprises a Data input port Data, a Scan input port Scan In and a Scan Enable control port Scan Enable; the band Scan input register further includes a clock input port Clk, a data output port Q, and a Scan output port Scan Out.

FIG. 2 is a schematic diagram of scan chain connections in a CPU; the CPU state-saving method comprises 7

registers

1, 2, 3, 4, 5, 6 and 7 with scanning input, wherein a common register needing to save state in the CPU is replaced by the register with scanning input, the registers with scanning input are connected in series, a scanning output port of the previous register with scanning input is connected with a scanning input port of the next register with scanning input, and clock input ports of all registers with scanning input are connected together; all scan enable control ports with scan input registers are connected together.

Fig. 3 is a scan chain based chip analysis state transition diagram, comprising 8 states: an IDLE state IDLE, a CPU direct trigger waiting state WAIT _ SIGNAL, a clock cycle trigger waiting state WAIT _ CNT, a SERIAL data scanning state SCAN _ SAVE, a SERIAL data output state SERIAL _ OUT, a data analysis state COMPARE, a chip RESET state ASSERT _ SESET and a RELEASE control SIGNAL state RELEASE _ RESET; the specific state is switched according to the following steps:

the IDLE state IDLE is a state that a background CPU waits for a serial port to input an instruction, and the CPU simultaneously sets two trigger modes, namely a chip signal trigger mode and a fixed clock period trigger mode;

when the CPU receives the serial port command, the CPU starts a chip signal triggering mode according to a fixed clock cycle triggering command, enters a clock cycle triggering waiting state WAIT _ CNT and enters a serial data scanning state after waiting for a fixed clock cycle;

when the serial port instruction received by the CPU is a CPU direct trigger instruction, starting a fixed clock period trigger mode, entering a CPU direct trigger waiting state WAIT _ SIGNAL, and automatically triggering by the CPU according to a preset condition to enter a serial data scanning state;

the serial data scanning state SCAN _ SAVE realizes the acquisition of the clock control right of the CPU, realizes the control of the lengths of a clock and a scanning chain after the clock control right of the CPU is acquired, and controls the serial scanning of data with a scanning input register;

the SERIAL data output state SERIAL _ OUT serially outputs the data with the scanning input register to the debugging host;

the data analysis state COMPARE is used for displaying the data difference of each scanning input register to a debugger in a bit map mode;

after the analysis of the ASSERT _ RESET data in the chip RESET state is finished, the RESET signal is controlled to be output by controlling JTAG to carry out RESET operation on the CPU;

the RELEASE control signal state RELEASE _ RESET RELEASEs the clock control right of the CPU, and the CPU re-enters the idle state after normal operation.

While the invention has been described with reference to a particular embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A chip analysis method based on scan chain is characterized in that a common register needing to be stored in a CPU is replaced by a register with scan input, when the CPU is abnormal, a serial scan trigger instruction is output through JTAG to start the data storage operation of the scan chain, the data with the scan input register is output to a debugging host through a JTAG port, a debugger analyzes the data with the scan input register received by the debugging host, and after the analysis is finished, the reset operation is carried out on the CPU by controlling a JTAG output control reset signal to control the CPU to restore the normal work; the data selector is additionally arranged in front of a data input port of the common register and comprises a data input port, a scanning input port and a scanning enabling control port; the input register with scanning also comprises a clock input port and a scanning output port; the input registers with scanning are connected in series, the scanning output port of the previous input register with scanning is connected with the scanning input port of the next input register with scanning, and the clock input ports of all the input registers with scanning are connected together; all the scan enable control ports with scan input registers are connected together; comprising 8 states: the method comprises the following steps that (1) an idle state, a CPU direct trigger waiting state, a clock cycle trigger waiting state, a serial data scanning state, a serial data output state, a data analysis state, a chip reset state and a control signal release state are adopted; the specific state is switched according to the following steps:

the method comprises the following steps that an idle state background CPU waits for a serial port input instruction state, and the CPU simultaneously sets two trigger modes, namely a chip signal trigger mode and a fixed clock period trigger mode;

when the CPU receives the serial port command, the CPU starts a chip signal triggering mode according to the fixed clock cycle triggering command, enters a clock cycle triggering waiting state, and enters a serial data scanning state after waiting for the fixed clock cycle;

when the serial port instruction received by the CPU is a CPU direct trigger instruction, starting a fixed clock period trigger mode, entering a CPU direct trigger waiting state, and automatically triggering by the CPU according to a preset condition to enter a serial data scanning state;

the serial data scanning state realizes the acquisition of the clock control right of the CPU, realizes the control of the lengths of the clock and the scan chain after the clock control right of the CPU is acquired, and controls the serial scanning of the data with the scan input register; the serial data output state serially outputs the data with the scanning input register to the debugging host;

the data analysis state shows the data difference of each scanning input register to a debugger in a mode of a bit map;

after the chip reset state data is analyzed, the reset signal is controlled to carry out reset operation on the CPU by controlling JTAG output;

the control signal is released to release the clock control right of the CPU, and the CPU enters an idle state again after working normally.