CN111211776A - Phase-locked loop circuit - Google Patents
Phase-locked loop circuit Download PDFInfo
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
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Abstract
The invention provides a phase-locked loop circuit, which charges or discharges a loop filter according to up pulses or dn pulses through a self-calibration charge pump and adjusts control voltage output by the loop filter; the self-calibration charge pump has the advantages that currents pumped in or out by the self-calibration charge pump according to the UP pulse or the DN pulse are the same, the current mismatch problem of the traditional charge pump is improved by the self-calibration charge pump, the UP current and the DN current of the charge pump are matched, and therefore the problem of output jitter increase caused by static phase difference and current mismatch when the analog phase-locked loop is locked is solved.
Description
Technical Field
The application relates to the technical field of electronic circuits, in particular to a phase-locked loop circuit.
Background
In the prior art, in order to enable the phase-locked loop to have a large adjustable range of output frequency (10-28 GHz) and small phase noise (jitter is less than 1 ps), sensitivity of the output frequency of a voltage-controlled oscillator to a control voltage Vctrl needs to be improved, but if voltage noise on the control voltage Vctrl is large, large phase noise and jitter occur in an output clock of the phase-locked loop; in order to reduce noise, the sensitivity of the output frequency of the vco to the control voltage Vctrl must be reduced, which is contrary to the requirement of a large output frequency range. Secondly, when the voltage of the control voltage Vctrl is close to the power supply or the ground, the charge and discharge currents of the charge pump in the analog phase-locked loop to the loop filter are severely mismatched, so that the performance of the phase-locked loop is reduced.
Disclosure of Invention
In view of the above, the present application provides a phase-locked loop circuit to solve the problem that the charging and discharging currents of the charge pump to the loop filter in the conventional phase-locked loop are not matched seriously.
The technical scheme adopted by the invention is as follows:
the present invention provides a phase-locked loop circuit, including: the system comprises a frequency phase comparator, a self-calibration charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider; the frequency phase comparator, the self-calibration charge pump electric connection, the loop filter and the voltage-controlled oscillator are sequentially connected; the voltage-controlled oscillator is also connected with the frequency phase comparator through the frequency divider;
the frequency divider is used for dividing the frequency of the clock signal output by the voltage-controlled oscillator to generate a feedback clock and transmitting the feedback clock to the frequency phase comparator;
the frequency phase comparator is used for comparing the feedback clock with a reference clock and outputting an up pulse or a dn pulse to the self-calibration charge pump;
the self-calibration charge pump pumps current to the loop filter according to the up pulse, and is further used for controlling the pump-out current of the loop filter according to the dn pulse, wherein the pump-out current is matched with the pump-in current;
the loop filter is used for adjusting the control voltage output to the voltage-controlled oscillator according to the pumping current or the pumping current so that the voltage-controlled oscillator outputs a clock signal which is synchronous with the phase of the reference clock according to the control voltage.
Further, the self-calibration charge pump comprises a self-calibration module and a charge pump module, and the self-calibration module is electrically connected with the charge pump module;
the charge pump module is used for generating a pump-in current according to the up pulse to charge the loop filter so as to increase the control voltage; the charge pump module is also used for generating a pump-out current according to the dn pulse to discharge the loop filter so as to reduce the control voltage;
the self-calibration module is used for adjusting and controlling the charge pump module so as to enable the pump-in current to be matched with the pump-out current.
Further, the charge pump includes: the first PMOS tube, the first NMOS tube, the first switch group and the second switch group;
the first switch group and the second switch group are connected in parallel between the first PMOS tube and the first NMOS tube;
the first switch group comprises a second PMOS tube and a second NMOS tube; the second PMOS tube is connected with the second NMOS tube in series, wherein the second PMOS tube is connected with the first PMOS tube; the second NMOS tube is connected with the first NMOS tube;
the second switch group comprises a third PMOS tube and a third NMOS tube; the third PMOS tube is connected with the third NMOS tube in series; the third PMOS tube is connected with the first PMOS tube; the third NMOS tube is connected with the first NMOS tube;
the first switch group and the second switch group are used for being alternatively conducted according to the up pulse or the dn pulse so as to generate the pumping-in current or the pumping-out current.
Further, the gate of the first PMOS transistor is used for accessing a preset direct current signal Vbp, so that the pumping current is generated when the second switch group is turned on.
Further, the self-calibration module comprises an amplifier and a capacitor Cd;
the inverting end of the amplifier is connected between the third PMOS tube and the third NMOS tube, and the non-inverting end of the amplifier is connected between the second PMOS tube and the second NMOS tube;
a first end of the capacitor Cd is connected with the in-phase end of the amplifier, and a second end of the capacitor Cd is grounded;
the output end of the amplifier is connected with the grid electrode of the first NMOS tube, so that the pump-out current matched with the pump-in current is generated when the first switch group is conducted.
Further, when the reference clock is advanced in phase, the frequency phase comparator outputs the up pulse, and the self-calibration charge pump controls the loop filter to charge according to the up pulse.
Further, when the reference clock is lagging in phase, the frequency phase comparator outputs the dn pulse; the self-calibration charge pump controls the loop filter pump to discharge according to the dn pulse.
Further, the voltage-controlled oscillator comprises a cross-coupled MOS tube and an LC resonant circuit;
the LC resonance circuit is connected with the cross-coupling MOS tube and comprises an inductor LVCOA first capacitor C1 and a second capacitor C2;
the LC resonance circuit comprises an inductor LVCOThe first capacitor bank C1 and the second capacitor C2 are connected in parallel, wherein the first capacitor bank C1 includes a plurality of digital switched capacitors connected in parallel, and the second capacitor C2 is an analog regulating capacitor;
the output frequency of the voltage-controlled oscillator and the inductance LVCOThe first capacitor bank C1 and the second capacitor C2 satisfy the following formula:
wherein, the fLCVCORepresenting the output frequency of said voltage controlled oscillator, said LVCOFor the inductor, the C1 is the first capacitor bank, and the C2 is the second capacitor.
Further, the second capacitor C2 is used to realize fine adjustment of the output frequency of the voltage-controlled oscillator;
the first capacitor bank C1 is used to implement coarse tuning of the output frequency of the vco.
Further, a low-voltage threshold and a high-voltage threshold are preset in the phase-locked loop circuit;
when the control voltage is smaller than the low-voltage threshold, increasing the capacitance value of the first capacitor bank C1 to realize phase-locked loop locking;
when the control voltage is greater than or equal to the low-voltage threshold and less than the high-voltage threshold, keeping the capacitance value of the first capacitor bank C1 unchanged, and adjusting the capacitance value of the second capacitor C2 to realize phase-locked loop locking;
when the control voltage is greater than or equal to the high-voltage threshold and less than the power supply voltage, the capacitance value of the first capacitor bank C1 is reduced to realize phase-locked loop locking.
Compared with the prior art, the phase-locked loop circuit provided by the application has the following beneficial effects:
according to the phase-locked loop circuit provided by the invention, the self-calibration charge pump charges or discharges the loop filter according to the up pulse or the dn pulse so as to adjust the control voltage output by the loop filter; and the voltage-controlled oscillator outputs a clock signal which is in phase synchronization with the reference clock according to the control voltage output by the loop filter. The self-calibration charge pump is utilized to improve the current mismatch problem of the traditional charge pump, and the matching of the UP current and the DN current of the charge pump is realized, so that the problem of output jitter increase caused by static phase difference and current mismatch when the analog phase-locked loop is locked is solved. Meanwhile, the phase-locked loop circuit provided by the invention adopts the analog and digital double-regulation voltage-controlled oscillator, so that the requirement of low phase noise of an output clock can be met while the large-range adjustable output frequency is realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 shows a schematic diagram of a prior art phase-locked loop.
Fig. 2 shows another prior art phase locked loop schematic.
Fig. 3 shows a schematic diagram of a phase-locked loop circuit provided by the present invention.
Fig. 4 shows a schematic diagram of a self-calibrating charge pump provided by the present invention.
Fig. 5 shows a schematic diagram of a voltage controlled oscillator provided by the present invention.
Fig. 6 shows a schematic diagram of the division of the control voltage region provided by the present invention.
Fig. 7 shows a schematic diagram of a finite state machine provided by the present invention.
Icon: p1-first PMOS tube; p2-second PMOS tube; p3-third PMOS tube; n1-first NMOS tube; n2-second NMOS tube; n3-third NMOS transistor.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should also be noted that relational terms such as first and second, and the like, may be used solely herein to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
Some embodiments of the invention are described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
Phase-locked loops are the means for generating clock signals in many digital chips. The input reference clock of the phase locked loop is usually a clock signal with low phase noise, usually generated by a crystal oscillator, and has a relatively low frequency, but the frequency of the phase locked loop output clock is relatively high. The optical fiber communication physical layer chip generally needs to generate a clock frequency of 10-28 GHz, and the output clock jitter is required to be less than 1 ps.
Two typical phase-locked loop schemes are available in the conventional phase-locked loop scheme, one is an analog phase-locked loop, as shown in fig. 1, a phase frequency comparator (PFD) is used to compare a phase difference between a reference clock and an output clock divided by N times, a comparison result is used to control a charge pump to charge and discharge a loop filter, a control voltage Vctrl is generated, and a voltage-controlled oscillator (VCO)) outputs an N-times frequency clock signal locked with the phase of the reference clock under the action of the control voltage Vctrl.
Another common Digital phase-locked loop is a Digital phase-locked loop, as shown in fig. 2, compared to an analog phase-locked loop, a Digital filter and a Time To Digital Converter (TDC) are used to replace a charge pump and a loop filter in the analog phase-locked loop, a Digital signal Dctrl generated by the Digital filter is used to adjust an output frequency of the Digital controlled oscillator, and simultaneously, an output of the Digital controlled oscillator also provides a clock signal for the TDC.
Because a high-speed signal transmitting end needs to output a phase-locked loop with a large adjustable frequency range (10-28 GHz) and small phase noise (jitter below 1 ps), in order to enable the adjustable frequency range of the phase-locked loop to be large, the sensitivity of the output frequency of a voltage-controlled oscillator to a control voltage Vctrl needs to be improved in the simulated phase-locked loop, but if the voltage noise on the control voltage Vctrl is large, the phase-locked loop output clock has large phase noise and jitter; in order to reduce noise, the sensitivity of the output frequency of the voltage-controlled oscillator to the control voltage Vctrl must be reduced, so that the requirement of a large output frequency range is contradicted, and in addition, when the voltage of the control voltage Vctrl is close to a power supply or ground, the charge and discharge currents of a charge pump in the analog phase-locked loop to a loop filter are severely mismatched, so that the performance of the phase-locked loop is reduced. Although the digital phase-locked loop is not affected by the above-mentioned analog noise, its TDC is a time measurement circuit, and a quantization error occurs, thereby generating a deviation in the output clock frequency of the phase-locked loop and affecting the jitter of the output clock.
In order to improve the above problem, the present application provides a new pll circuit, please refer to fig. 3, where fig. 3 shows a schematic diagram of a circuit provided in an embodiment of the present application.
The phase-locked loop circuit provided by the embodiment of the application comprises: a frequency phase comparator, a self-calibration charge pump, a loop filter, a voltage-controlled oscillator, a buffer and a frequency divider.
The frequency phase comparator, the self-calibration charge pump electric connection, the loop filter and the voltage-controlled oscillator are connected in sequence. The voltage-controlled oscillator is also connected with the frequency phase comparator through a buffer and a frequency divider.
The frequency divider is used for dividing a clock signal (VCO clock) output by the voltage-controlled oscillator to generate a feedback clock and transmitting the feedback clock to the frequency phase comparator; the frequency phase comparator is used for comparing the feedback clock with the reference clock and outputting up pulses or dn pulses to the self-calibration charge pump; the self-calibration charge pump charges or discharges the loop filter according to the up pulse or the dn pulse so as to adjust the control voltage output by the loop filter; wherein the charge and discharge electric quantity are the same; the voltage-controlled oscillator outputs a clock signal phase-synchronized with the reference clock according to the control voltage output by the loop filter.
The frequency phase comparator first compares the phases of the reference clock and the divided-by-N VCO clock, and as a result outputs three states, the first being UP, the second being DN, and the third being idle. The frequency phase comparator outputs up pulses when the phase of the reference clock is advanced, outputs dn pulses when the phase of the reference clock is delayed, and outputs an idle state when the phases of the reference clock and the frequency phase comparator are the same.
The self-calibrating charge pump controls the loop filter to charge according to the up pulse or to discharge according to the dn pulse. When the phase of the reference clock is advanced and the up pulse is output by the frequency phase comparator, the self-calibration charge pump current is sent to the loop filter to charge the loop filter, and the voltage of the control voltage Vctrl is increased; when the reference clock is lagging in phase, the frequency phase comparator outputs dn pulses; the self-calibration charge pump controls the loop filter to pump current to discharge according to the dn pulse, and the voltage of the control voltage Vctrl is reduced.
In general, the charge pump pumps in the same current according to the up pulses and out the same current according to the dn pulses, which reduces the static phase error. However, if the control voltage Vctrl rises close to the supply Vdd or falls close to ground, the current pumped in by the charge pump according to the up pulses and pumped out according to the dn pulses can be severely mismatched. The pump-in current is much smaller than the pump-out current when the control voltage Vctrl is high, and much larger than the pump-out current when the control voltage Vctrl is low. Therefore, if the control voltage Vctrl is just too high or too low when the phase-locked loop is locked, the charge pump may have current mismatch, which may deteriorate the ability of the phase-locked loop to suppress phase noise and reduce the quality of the output clock signal.
For this reason, the present embodiment employs a self-calibration charge pump, and referring to fig. 4, the self-calibration charge pump includes a self-calibration module and a charge pump module, and the self-calibration module is electrically connected to the charge pump module.
The charge pump module is used for generating an UP current (namely a pumping current) according to the UP pulse so as to charge the loop filter; the charge pump module is also used for generating DN current (namely pumping out current) according to the DN pulse so as to discharge the loop filter; the self-calibration module is used for adjusting and controlling the charge pump module so as to enable the UP current to be matched with the DN current.
In one possible implementation, the charge pump module consists of six field effect transistors, P-type metal oxide field effect transistors (PMOS) P1-P3 and N-type metal oxide field effect transistors (NMOS) N1-N3. For example, the charge pump includes: a first PMOS transistor P1, a first NMOS transistor N1, a first switch group and a second switch group; the first switch group and the second switch group are connected in parallel between the first PMOS transistor P1 and the first NMOS transistor N1; the first switch group comprises a second PMOS tube P2 and a second NMOS tube N2; a second PMOS transistor P2 is connected in series with a second NMOS transistor N2, wherein the second PMOS transistor P2 is connected to the first PMOS transistor P1; the second NMOS transistor N2 is connected with the first NMOS transistor N1; the second switch group comprises a third PMOS tube P3 and a third NMOS tube N3; the third PMOS pipe P3 is connected with the third NMOS pipe N3 in series; the third PMOS pipe P3 is connected with the first PMOS pipe P1; the third NMOS transistor N3 is connected to the first NMOS transistor N1.
The gate of the first PMOS transistor P1 is used for receiving a preset dc signal Vbp, so that an UP current is generated when the second switch set is turned on. The gate of the first NMOS transistor N1 is used to switch in Vbn.
The connection point of the third PMOS transistor P3 and the third NMOS transistor N3 in series is set as point E, and the connection point of the second PMOS transistor P2 and the second NMOS transistor N2 is set as point F. The output of the charge pump is point E, the magnitudes of the UP and DN currents of the charge pump are determined by the gate voltages Vbp and Vbn of the first PMOS transistor P1 and the first NMOS transistor N1, respectively, where Vbp is an external preset dc voltage, and Vbn is generated by the self-calibration module, so that the DN current automatically matches the UP current.
The first switch group and the second switch group are respectively controlled by UP pulses and DN pulses generated by the frequency phase comparator and inverse signals ub and db pulses of the UP pulses and the DN pulses, and the first switch group and the second switch group are alternately conducted according to the UP pulses or the DN pulses to generate UP current or DN current. At the point E, the subsequent loop filter is charged and discharged through the third PMOS transistor P3 and the third NMOS transistor N3, and finally Vctrl (VCO control voltage) is generated at the point E. The second PMOS transistor P2 and the third PMOS transistor P3, the second NMOS transistor N2 and the third NMOS transistor N3 are symmetrical circuits, that is, the first switch group and the second switch group are symmetrical circuits, so that the current at point F is the complementary current at point E, that is, when point E is UP pump out current, point F is DN pump in current; when point E is DN pump-in current, point F is UP pump-out current; when point E is idle, neither pump-in nor pump-out current is present, and point F is when pump-in and pump-out current occurs simultaneously.
The self-calibration module comprises an amplifier and a capacitor Cd; the inverting terminal of the amplifier is connected between the third PMOS transistor P3 and the third NMOS transistor N3, namely, the point E, and the non-inverting terminal of the amplifier is connected between the second PMOS transistor P2 and the second NMOS transistor N2; i.e., point F. The first end of the capacitor Cd is connected with the in-phase end of the amplifier, and the second end of the capacitor Cd is grounded; the output end of the amplifier is connected with the grid electrode of the first NMOS tube N1, so that DN current matched with UP current is generated when the first switch is conducted.
The capacitor Cd is used as a redundant capacitor, the amplifier is used as an error amplifier, if the UP current and DN current generated by the charge pump module are not matched, the F point current can continuously accumulate error charges on the redundant capacitor Cd, and finally the voltage of the redundant capacitor Cd is Vdd or ground; if the UP current is matched with the DN current, no charge accumulation occurs on the redundant capacitor Cd, and the voltage of the redundant capacitor Cd is constant at a certain direct current voltage.
Based on the above seriously, the present embodiment employs an amplifier to sense the difference between the control voltage Vctrl and the voltage of the redundant capacitor Cd, and amplify and feed the difference back to the gate of the first NMOS transistor N1, so as to change the DN current, and eliminate the difference between the control voltage Vctrl and the voltage of the redundant capacitor Cd. When the voltage of the redundant capacitor Cd is the same as the control voltage Vctrl, the voltage of the redundant capacitor Cd is neither Vdd nor ground, so that the DN current is equal to the UP current.
The relationship between the output frequency of the voltage-controlled oscillator VCO and the control voltage Vctrl satisfies the following equation:
fVCO＝KVCO*Vctrl；
in the formula, KVCOVctrl is the control voltage output by the loop filter to the VCO for adjusting the gain of the VCO.
For an application scenario with a phase-locked loop with a large adjustable frequency range, K needs to be adjustedVCOThe design is a large value, so that a large range of adjustable frequency can still be output when the variation range of the control voltage Vctrl is small.
For application scenarios requiring low clock jitter applications, K needs to be setVCODesigned to be small in value, thereby reducing the influence of noise on the control voltage Vctrl on the phase noise of the output clock.
And for high-speed signal transmitting terminal, lockThe phase loop is required to provide both a large adjustable range frequency output and to keep the phase noise of the output clock low, resulting in KVCOThe value of (a) is relatively difficult to design.
In order to solve the above problem, in the embodiment of the present application, a voltage controlled oscillator using an analog fine tuning and a digital coarse tuning is adopted, and referring to fig. 5, the voltage controlled oscillator includes a cross-coupled MOS transistor and an LC resonant circuit. The LC resonance circuit is connected with the cross-coupling MOS tube and comprises an inductor LVCOA first capacitor C1 and a second capacitor C2; the LC resonance circuit comprises an inductor LVCOThe first capacitor C1 and the second capacitor C2 are connected in parallel, wherein the first capacitor C1 includes a plurality of digital switched capacitors connected in parallel, the capacitance value of the digital switched capacitors is controlled by the input digital signal, and the second capacitor C2 is an analog adjusting capacitor, the capacitance value of which changes with the input control voltage Vctrl.
Output frequency and inductance L of voltage controlled oscillatorVCOThe first capacitor group C1 and the second capacitor group C2 satisfy the following formula:
wherein f isLCVCOIndicating the output frequency, L, of the voltage-controlled oscillatorVCOThe inductor is C1, the first capacitor bank, and the second capacitor bank is C2.
The second capacitor C2 is used for fine adjustment of the output frequency of the voltage-controlled oscillator; the first switch C1 is used to implement coarse tuning of the output frequency of the vco. In this embodiment, the second capacitor C2 is an analog fine tuning capacitor, and has a small tuning range but high precision when the control voltage Vctrl changes. The first capacitor bank C1 is a digital coarse tuning capacitor with a wide tuning range but a low resolution.
When the phase of the phase-locked loop circuit is locked, the capacitance value of the first capacitor bank C1 is not changed, only the control voltage Vctrl finely changes the output phase of the voltage-controlled oscillator through the second capacitor C2, namely, the fine adjustment is simulated, and at the moment, K isVCOThe value is small, and clock output with low phase noise is realized.
When the output frequency of the vco needs to be changed, the pll adjusts the first capacitor bank C1, so as to realize a wider frequency adjustment range, that is, digital coarse adjustment, wherein the digital control signal of the first capacitor bank C1 is determined by the magnitude of the control voltage Vctrl.
In this embodiment, the phase-locked loop circuit is preset with a low voltage threshold and a high voltage threshold; the low voltage threshold is Vdd 3/8, the high voltage threshold is Vdd 5/8, and Vdd refers to the power supply voltage. When Vctrl is lower than the low voltage threshold or higher than the voltage threshold, it is determined that the analog fine tuning second capacitor C2 is not enough to achieve phase-locked loop locking, and the coarse tuning capacitor C1 is needed.
In one possible implementation, the voltage region of the control voltage Vctrl is divided into three region ranges, as shown in fig. 6.
Region S1: when the control voltage is smaller than the low-voltage threshold, the capacitance value of the first capacitor bank C1 is increased to realize phase-locked loop locking;
region S2: when the control voltage is greater than or equal to the low-voltage threshold and less than the high-voltage threshold, the capacitance value of the first capacitor bank C1 is kept unchanged, and the phase-locked loop is locked by adjusting the capacitance value of the second capacitor C2;
region S3: when the control voltage is greater than or equal to the high voltage threshold and less than the dc voltage Vdd, the capacitance of the first capacitor C1 is decreased to achieve phase-locked loop locking.
The phase-locked loop circuit compares the control voltage Vctrl with the voltage of a low-voltage threshold and the voltage of a high-voltage threshold by using a threshold judgment module, and then sends the result to a finite-state machine. As shown in fig. 7, when the voltage range of the control voltage Vctrl is in the region S1, the capacitance value of the first capacitor bank C1 needs to be increased; when the voltage range S2 of the voltage Vctrl is controlled, the first capacitor group C1 does not need to be changed, and the locking of the phase-locked loop can be realized by simulating and finely adjusting the capacitance value of the second capacitor C2; when the voltage range of the control voltage Vctrl is in the region S3, the capacitance value of the first capacitor bank C1 is large, and C1 needs to be reduced.
It should be noted that each adjustment described above requires a delay module to prevent the problem of instability of the phase-locked loop. The clock of the finite state machine is provided by a signal of the VCO clock after being divided by N, and through adjustment of the finite state machine on the first capacitor bank C1, finally when the phase-locked loop is locked, the voltage range of the control unit Vctrl will be in S2, which is in a range between the low voltage threshold and the high voltage threshold, so that the influence of too high or too low of the control voltage Vctrl on the mismatch of the charge pump current can also be reduced.
In summary, in the phase-locked loop circuit provided by the present invention, the self-calibration charge pump charges or discharges the loop filter according to the up pulse or the dn pulse to adjust the control voltage output by the loop filter; the voltage-controlled oscillator outputs a clock signal phase-synchronized with the reference clock according to the control voltage output by the loop filter. The self-calibration charge pump is utilized to improve the current mismatch problem of the traditional charge pump, and the matching of the UP current and the DN current of the charge pump is realized, so that the problem of output jitter increase caused by static phase difference and current mismatch when the analog phase-locked loop is locked is solved. Meanwhile, the phase-locked loop circuit provided by the invention adopts the analog and digital double-regulation voltage-controlled oscillator, so that the requirement of low phase noise of an output clock can be met while the large-range adjustable output frequency is realized. In addition, the application of the finite-state machine ensures that the control voltage of the voltage-controlled oscillator does not exceed the limit of the charge pump when the phase-locked loop works stably, thereby further reducing the influence of the current mismatch of the charge pump. Meanwhile, the scheme does not need to use a time measurement module TDC, so that the clock jitter problem caused by TDC error can not occur.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A phase-locked loop circuit, comprising:
the system comprises a frequency phase comparator, a self-calibration charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider;
the frequency phase comparator, the self-calibration charge pump electric connection, the loop filter and the voltage-controlled oscillator are sequentially connected;
the voltage-controlled oscillator is also connected with the frequency phase comparator through the frequency divider;
the frequency divider is used for dividing the frequency of the clock signal output by the voltage-controlled oscillator to generate a feedback clock and transmitting the feedback clock to the frequency phase comparator;
the frequency phase comparator is used for comparing the feedback clock with a reference clock and outputting an up pulse or a dn pulse to the self-calibration charge pump;
the self-calibration charge pump pumps current to the loop filter according to the up pulse, and is further used for controlling the pump-out current of the loop filter according to the dn pulse, wherein the pump-out current is matched with the pump-in current;
the loop filter is used for adjusting the control voltage output to the voltage-controlled oscillator according to the pumping current or the pumping current so that the voltage-controlled oscillator outputs a clock signal which is synchronous with the phase of the reference clock according to the control voltage.
2. The phase-locked loop circuit of claim 1, wherein the self-calibrating charge pump comprises a self-calibrating module and a charge pump module, the self-calibrating module being electrically connected to the charge pump module;
the charge pump module is used for generating a pump-in current according to the up pulse to charge the loop filter so as to increase the control voltage; the charge pump module is also used for generating a pump-out current according to the dn pulse to discharge the loop filter so as to reduce the control voltage;
the self-calibration module is used for adjusting and controlling the charge pump module so as to enable the pump-in current to be matched with the pump-out current.
3. The phase-locked loop circuit of claim 2, wherein the charge pump comprises: the first PMOS tube, the first NMOS tube, the first switch group and the second switch group;
the first switch group and the second switch group are connected in parallel between the first PMOS tube and the first NMOS tube;
the first switch group comprises a second PMOS tube and a second NMOS tube; the second PMOS tube is connected with the second NMOS tube in series, wherein the second PMOS tube is connected with the first PMOS tube; the second NMOS tube is connected with the first NMOS tube;
the second switch group comprises a third PMOS tube and a third NMOS tube; the third PMOS tube is connected with the third NMOS tube in series; the third PMOS tube is connected with the first PMOS tube; the third NMOS tube is connected with the first NMOS tube;
the first switch group and the second switch group are used for being alternatively conducted according to the up pulse or the dn pulse so as to generate the pumping-in current or the pumping-out current.
4. The phase-locked loop circuit of claim 3, wherein a gate of the first PMOS transistor is configured to receive a predetermined DC signal Vbp, so as to generate the pump-in current when the second switch set is turned on.
5. The phase-locked loop circuit of claim 4, wherein the self-calibration module comprises an amplifier and a capacitor Cd;
the inverting end of the amplifier is connected between the third PMOS tube and the third NMOS tube, and the non-inverting end of the amplifier is connected between the second PMOS tube and the second NMOS tube;
a first end of the capacitor Cd is connected with the in-phase end of the amplifier, and a second end of the capacitor Cd is grounded;
the output end of the amplifier is connected with the grid electrode of the first NMOS tube, so that the pump-out current matched with the pump-in current is generated when the first switch group is conducted.
6. The phase-locked loop circuit of claim 1, wherein the frequency phase comparator outputs the up pulse when the reference clock is phase advanced, the self-calibrating charge pump controlling the loop filter to charge based on the up pulse.
7. The phase-locked loop circuit of claim 6, wherein the frequency phase comparator outputs the dn pulse when the reference clock is phase-lagging; the self-calibration charge pump controls the loop filter pump to discharge according to the dn pulse.
8. The phase-locked loop circuit of claim 1, wherein the voltage-controlled oscillator comprises cross-coupled MOS transistors and an LC resonant circuit;
the LC resonance circuit is connected with the cross-coupling MOS tube and comprises an inductor LVCOA first capacitor C1 and a second capacitor C2;
the LC resonance circuit comprises an inductor LVCOThe first capacitor bank C1 and the second capacitor C2 are connected in parallel, wherein the first capacitor bank C1 includes a plurality of digital switched capacitors connected in parallel, and the second capacitor C2 is an analog regulating capacitor;
the output frequency of the voltage-controlled oscillator and the inductance LVCOThe first capacitor bank C1 and the second capacitor C2 satisfy the following formula:
wherein, the fLCVCORepresenting the output frequency of said voltage controlled oscillator, said LVCOFor the inductor, the C1 is the first capacitor bank, and the C2 is the second capacitor.
9. The phase-locked loop circuit of claim 8, wherein the second capacitor C2 is used to achieve fine tuning of the output frequency of the voltage-controlled oscillator;
the first capacitor bank C1 is used to implement coarse tuning of the output frequency of the vco.
10. The pll circuit of claim 9 wherein the pll circuit is preset with a low voltage threshold and a high voltage threshold;
when the control voltage is smaller than the low-voltage threshold, increasing the capacitance value of the first capacitor bank C1 to realize phase-locked loop locking;
when the control voltage is greater than or equal to the low-voltage threshold and less than the high-voltage threshold, keeping the capacitance value of the first capacitor bank C1 unchanged, and adjusting the capacitance value of the second capacitor C2 to realize phase-locked loop locking;
when the control voltage is greater than or equal to the high-voltage threshold and less than the power supply voltage, the capacitance value of the first capacitor bank C1 is reduced to realize phase-locked loop locking.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113452366A (en) * | 2021-07-22 | 2021-09-28 | 海能达通信股份有限公司 | PLL circuit and electronic equipment |
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| CN1481076A (en) * | 2002-07-17 | 2004-03-10 | 威盛电子股份有限公司 | Circuit of phase locked loop of charge pump |
| CN101483434A (en) * | 2008-01-11 | 2009-07-15 | 上海锐协微电子科技有限公司 | Voltage control oscillator with low tuning gain variance |
| CN102545600A (en) * | 2010-12-13 | 2012-07-04 | 立锜科技股份有限公司 | Power supply circuit capable of adaptively adjusting input and power supply method |
| JP2014204533A (en) * | 2013-04-03 | 2014-10-27 | 学校法人福岡大学 | Voltage adjusting device and motor driver having the same |
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|---|---|---|---|---|
| CN1481076A (en) * | 2002-07-17 | 2004-03-10 | 威盛电子股份有限公司 | Circuit of phase locked loop of charge pump |
| CN101483434A (en) * | 2008-01-11 | 2009-07-15 | 上海锐协微电子科技有限公司 | Voltage control oscillator with low tuning gain variance |
| CN102545600A (en) * | 2010-12-13 | 2012-07-04 | 立锜科技股份有限公司 | Power supply circuit capable of adaptively adjusting input and power supply method |
| JP2014204533A (en) * | 2013-04-03 | 2014-10-27 | 学校法人福岡大学 | Voltage adjusting device and motor driver having the same |
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| CN113452366A (en) * | 2021-07-22 | 2021-09-28 | 海能达通信股份有限公司 | PLL circuit and electronic equipment |
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