CN113541681B - Automatic current calibration charge pump circuit applied to dual-path phase-locked loop - Google Patents
Automatic current calibration charge pump circuit applied to dual-path phase-locked loop Download PDFInfo
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
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- H03L7/08—Details of the phase-locked loop
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- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The invention discloses an automatic current calibration charge pump circuit applied to a dual-path phase-locked loop, which comprises a phase frequency detector, a first charge pump module, a second charge pump module, a first loop filter module, a second loop filter module, a first calibration logic module, a second calibration logic module, a voltage-controlled oscillator, a frequency divider and a detection module, wherein the first charge pump module, the first loop filter module and the first calibration logic module form an integral path, the second charge pump module, the second loop filter module and the second calibration logic module are connected to form a proportional path, and the voltage-controlled oscillator is tuned and controlled by two control paths of the proportional path and the integral path. The circuit greatly improves the matching degree of the up-down current of the charge pump, reduces the ripple on the voltage controlled oscillator control voltage after the system is stabilized, and greatly inhibits the reference stray of the phase-locked loop to enable the phase-locked loop to achieve better performance.
Description
Technical Field
The invention belongs to the technical field of digital-analog hybrid integrated circuits, and particularly relates to an automatic current calibration charge pump circuit applied to a dual-path phase-locked loop.
Background
A PLL (Phase Locked Loop) is a negative feedback control system that uses a voltage generated by Phase synchronization to tune a voltage controlled oscillator to generate a target frequency, and uses an externally input reference signal to control the frequency and Phase of an internal oscillation signal of a Loop, so as to realize automatic tracking of an output signal frequency to an input signal frequency, and is generally used in a closed-Loop tracking circuit. The Phase-Locked Loop is a method for stabilizing frequency in radio transmission, and mainly includes a VCO (Voltage Controlled Oscillator) and a PLLIC (Phase Locked Loop Integrated Circuit), where the VCO provides a signal, one part of which is used as output, and the other part of which is compared with a local Oscillator signal generated by the PLL IC through frequency division, and in order to keep frequency constant, the Phase difference is required to be unchanged, and if there is a change in the Phase difference, the Voltage at the Voltage output end of the PLL IC changes to control the VCO until the Phase difference is recovered, so as to achieve the purpose of Phase locking.
Based on the contradiction between the phase noise and the area of the traditional single-path PLL, a proportional-integral double-path phase-locked loop is provided. Referring to fig. 1, fig. 1 is a schematic diagram of a conventional two-type dual-loop PLL, in which a filtering control path of a conventional PLL is divided into an upper control path and a lower control path, and a loop filter in one path is composed of a proportional resistor and a ripple capacitor, and is called a proportional path; the loop filter in the other path is only composed of one integrating capacitor and is called an integrating path. The charge and discharge of the loop filter in each path are respectively from an independent charge pump, the input signals of the two paths are from the same phase frequency detector, and the output tuning voltage controls the same voltage-controlled oscillator together.
The two-type double-loop phase-locked loop has obvious advantages in the aspects of reducing phase noise and saving area. In particular, since the two paths are independently opened, the integration path may rely on independent capacitance C I To achieve lower phase noise and C I The size of the loop filter does not need to be overlarge, and the area is saved to a certain extent, so that the loop filter can be integrated into a phase-locked loop chip, the efficiency is improved, and the manufacturing cost is reduced. And the path separation ensures that the integral path mainly bears the task of frequency calibration, and the proportional path does not need to bear, so that the proportional path can be provided with smaller voltage/frequency gain, and simultaneously, a larger charge pump current is arranged to inhibit in-band phase noise caused by the proportional path。
However, the mismatch that must exist due to the charge pump will usually deteriorate the spurious performance of the circuit, while the two charge pumps in the two-type dual-loop phase-locked loop will have the mismatch at the same time, which is more difficult to handle than the mismatch of the charge pumps in the single path, so that the reference spurious is further deteriorated. Therefore, the adoption of the structure can cause the deterioration of the reference stray caused by the mismatch of the charge pump and reduce the performance of the phase-locked loop.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides an automatic current calibration charge pump circuit applied to a dual-path phase-locked loop. The technical problem to be solved by the invention is realized by the following technical scheme:
the invention provides an automatic current calibration charge pump circuit applied to a dual-path phase-locked loop, which comprises a phase frequency detector, a first charge pump module, a second charge pump module, a first loop filter module, a second loop filter module, a first calibration logic module, a second calibration logic module, a voltage-controlled oscillator, a frequency divider and a detection module, wherein,
the first charge pump module, the first loop filter module and the first calibration logic module form an integral path, the second charge pump module, the second loop filter module and the second calibration logic module are connected to form a proportional path, and the voltage-controlled oscillator is tuned and controlled by two control paths of the proportional path and the integral path;
the phase frequency detector is used for generating a charging pulse and a discharging pulse according to a phase difference between a reference clock signal and an output signal from the detection module, controlling the first charge pump module to charge and discharge the first loop filter module and controlling the second charge pump module to charge and discharge the second loop filter module;
the first loop filter module is used for filtering the charge pump current input by the first charge pump module to generate a first filtering voltage and outputting the first filtering voltage to the voltage-controlled oscillator;
the second loop filter module is used for filtering the charge pump current input by the second charge pump module to generate a second filtering voltage and outputting the second filtering voltage to the voltage-controlled oscillator;
the first calibration logic module is configured to obtain a mismatch condition of the first charge pump module and generate a calibration logic signal according to the mismatch condition, so as to control the first charge pump module to adjust a charge pump current;
the second calibration logic module is configured to obtain a mismatch condition of the second charge pump module and generate a calibration logic signal according to the mismatch condition to control the second charge pump module to adjust a charge pump current;
the voltage-controlled oscillator is used for generating an output clock signal with variable frequency according to the first filtering voltage and the second filtering voltage;
the frequency divider is used for dividing the frequency of the output clock signal from the voltage-controlled oscillator by a preset frequency division value to obtain a feedback signal;
the detection module is used for judging whether the frequency divider enters a locking state or not according to the feedback signal from the frequency divider, and generating an output signal to be sent to the phase frequency detector.
In one embodiment of the present invention, the detection module comprises a lock detector, a signal switching unit and an adjustable dead-time prevention delay unit, wherein,
the input end of the lock detector is connected with the frequency divider and used for generating a calibration enable signal according to the feedback signal from the frequency divider;
the input end of the signal switching unit is respectively connected with the lock detector, the frequency divider and the reference signal input end, and is used for switching an output signal into a reference signal or a feedback signal from the frequency divider according to the calibration enabling signal and sending the reference signal or the feedback signal to the phase frequency detector;
the input end of the adjustable dead zone preventing delay unit is connected with the locking detector, and the output end of the adjustable dead zone preventing delay unit is connected with the phase frequency detector and used for adjusting the reset delay time sent to the phase frequency detector according to the calibration enabling signal.
In one embodiment of the invention, the first charge pump module comprises a charge pump unit and a current calibration array unit connected to the charge pump unit, wherein,
the current calibration array unit is connected with the first calibration logic module and used for obtaining a mismatch current calibration code from the first calibration logic module in a calibration mode and carrying out current calibration on the charge pump unit by using the mismatch current calibration code so as to eliminate current mismatch in the charge pump unit.
In one embodiment of the present invention, the current calibration array unit includes a pull-up current calibration array and a pull-down current calibration array, wherein,
the pull-up current calibration array comprises n first sub-units connected in series, and each first sub-unit is provided with a complementary switch tube M A And M B And a current source tube M C The calibration current of the n-bit first subunit is gradually increased by multiplying by two;
the pull-down current calibration array comprises n second subunits connected in series, and the second subunit of each bit is provided with a complementary switch tube M D And M E And a current source tube M F And the calibration current of the n-bit second subunit is incremented by a multiplication of two proportions from time to time.
In one embodiment of the invention, said first loop filter module comprises a first capacitor C I1 A second capacitor C I2 A third capacitor C I A first switch S 1 And a second switch S 2 Wherein the first capacitor C I1 Connected between the ground terminal and the output terminal of the first charge pump module, the first switch S 1 And the second capacitor C I2 The first charge pump module is connected between a ground terminal and the output terminal of the first charge pump module in series; the first switch S 1 The second switch S 2 And said third capacitance C I The first charge pump module is connected in series between a ground terminal and an output terminal of the first charge pump module.
In one embodiment of the invention, the second loop filterThe module comprises a fourth capacitor C P1 A fifth capacitor C P2 A sixth capacitor C P A first resistor R P And a third switch S 3 And a fourth switch S 4 And a fifth switch S 5 Wherein the fourth capacitor C P1 Connected between the ground terminal and the output terminal of the second charge pump module, the third switch S 3 And the first resistor R P A common mode voltage V connected in series with the output end of the second charge pump module CM Of said sixth capacitance C P Is connected to the ground terminal, and the other end is connected to the third switch S 3 And the first resistor R P To (c) to (d); the fourth switch S 4 Connected at a common-mode voltage V CM And the output end of the second charge pump module, the fifth switch S 5 Connected between the input of the first calibration logic and the common-mode voltage V CM Between, the fifth capacitance C P2 Connected between the input terminal of the first calibration logic block and ground.
In one embodiment of the present invention, the first calibration logic block comprises a first comparator COM1, a first register unit and a first calibration logic unit, wherein,
a positive input end of the first comparator COM1 is connected to the output end of the first charge pump module, and a negative input end of the first comparator COM1 is connected to the first switch S 1 And the second switch S 2 The output end of the first register unit is connected with the first register unit, and the first comparator COM1 is used for comparing voltage values representing mismatch conditions to output mismatch comparison results;
the first register unit is connected between the first comparator COM1 and the first calibration logic unit, and is used for transferring the mismatch comparison result to the first calibration logic unit;
the first calibration logic unit is connected to the first charge pump module, and is configured to generate a calibration logic signal according to the mismatch comparison result, so as to control the first charge pump module to perform current compensation.
In one embodiment of the invention, the second calibration logic module comprises a second comparator COM2, a second register unit and a second calibration logic unit, wherein,
the positive input end of the second comparator COM2 is connected to the output end of the second charge pump module, and the negative input end of the second comparator COM2 is connected to the fifth switch S 5 And said fifth capacitance C P2 The output end of the first register unit is connected with the first register unit; the second register unit is connected between the second comparator COM2 and the second calibration logic unit, and an output end of the second calibration logic unit is connected with the second charge pump module.
Compared with the prior art, the invention has the beneficial effects that:
1. the automatic current calibration charge pump circuit applied to the dual-path phase-locked loop greatly improves the matching degree of the pull-up current and the pull-down current of the charge pump, reduces the ripple on the control voltage of the voltage-controlled oscillator after the system is stabilized, greatly inhibits the reference stray of the phase-locked loop and enables the phase-locked loop to achieve better performance.
2. This dynamic current calibration charge pump circuit makes the dual path phase-locked loop can realize being less than 5% charge pump mismatch, thereby obtain the stability of structure and reduce stray, simultaneously through the delay time of increase phase frequency detector and reduce load capacitance, make the mismatch current can be discerned in single reference cycle, can discern the size of rising current and decline electric current difference in single reference cycle, the compensation adopts successive approximation control logic simultaneously, the calibration time of circuit has been reduced, make the calibration performance more superior.
The present invention will be described in further detail with reference to the drawings and examples.
Drawings
FIG. 1 is a diagram of a two-type conventional dual-loop PLL;
FIG. 2 is a block diagram of an automatic current calibration charge pump circuit applied to a dual-path phase-locked loop according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an automatic current calibration charge pump circuit applied to a dual-path phase-locked loop according to an embodiment of the present invention;
fig. 4 is a circuit diagram of a charge pump module according to an embodiment of the present invention;
FIG. 5 is a circuit state diagram of the automatic current calibration charge pump circuit provided by the embodiment of the invention during calibration;
FIG. 6 is a flowchart illustrating the calibration of an automatic current calibration charge pump circuit applied to a dual-path phase-locked loop according to an embodiment of the present invention;
fig. 7 is a calibration timing diagram of an automatic current calibration charge pump circuit applied to a dual-path phase-locked loop according to an embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention for achieving the predetermined objects, the following description will be made in detail with reference to the accompanying drawings and the detailed description of the present invention.
The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. While the present invention has been described in connection with the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or device that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising one of 8230, and" comprising 8230does not exclude the presence of additional like elements in an article or device comprising the element.
Referring to fig. 2, fig. 2 is a block diagram of an automatic current calibration charge pump circuit applied to a dual-path phase-locked loop according to an embodiment of the present invention. The automatic current calibration charge pump circuit comprises a phase frequency detector 101, a first charge pump module 102, a second charge pump module 103, a first loop filter module 104, a second loop filter module 105, a first calibration logic module 106, a second calibration logic module 107, a voltage-controlled oscillator 108, a frequency divider 109 and a detection module 110, wherein the first charge pump module 102, the first loop filter module 104 and the first calibration logic module 106 form an integral path, the second charge pump module 103, the second loop filter module 105 and the second calibration logic module 107 are connected to form a proportional path, and the voltage-controlled oscillator 108 is jointly tuned and controlled by two control paths, namely the proportional path and the integral path.
The phase frequency detector 101 is configured to generate a charging pulse and a discharging pulse according to a phase difference between an input reference clock signal and an output signal of the detection module 110, control the first charge pump module 102 to charge and discharge the first loop filter module 104, and control the second charge pump module 103 to charge and discharge the second loop filter module 105; the first loop filter module 104 is configured to filter the charge pump current input by the first charge pump module 102 to generate a first filtered voltage, and output the first filtered voltage to the vco 108; a second loop filter module 105, configured to filter the charge pump current input by the second charge pump module 103 to generate a second filtered voltage, and output the second filtered voltage to the voltage controlled oscillator 108; the first calibration logic module 106 is configured to obtain a mismatch condition of the first charge pump module 102 and generate a calibration logic signal according to the mismatch condition to control the first charge pump module 102 to adjust a charge pump current; a second calibration logic module 107, configured to obtain a mismatch condition of the second charge pump module 103 and generate a calibration logic signal according to the mismatch condition, so as to control the second charge pump module 103 to adjust a charge pump current; a voltage controlled oscillator 108 for generating an output clock signal having a variable frequency from the first filtered voltage and the second filtered voltage; the frequency divider 109 is configured to divide the frequency of the output clock signal from the voltage-controlled oscillator 108 by a predetermined frequency division value to obtain a feedback signal; the detection module 110 is configured to determine whether to enter a locked state according to a feedback signal from the frequency divider 109, and generate an output signal to be sent to the phase frequency detector 101.
Further, referring to fig. 3, fig. 3 is a schematic structural diagram of an automatic current calibration charge pump circuit applied to a dual-path phase-locked loop according to an embodiment of the present invention. The detection module 110 of this embodiment includes a lock detector 1101, a signal switching unit 1102, and an adjustable dead-time delay prevention unit 1103, where an input terminal of the lock detector 1101 is connected to the frequency divider 109, and is configured to generate a calibration enable signal according to a feedback signal from the frequency divider 109; the input end of the signal switching unit 1102 is connected to the lock detector 1101, the frequency divider 109 and the reference signal input end, respectively, and is configured to determine whether to enter a charge pump calibration state according to the calibration enable signal, switch the output signal of the signal switching unit 1102 into a reference signal or a feedback signal from the frequency divider 109, and send the reference signal or the feedback signal to the phase frequency detector 101; the input end of the adjustable dead zone time delay unit 1103 is connected to the lock detector 1101, and the output end is connected to the phase frequency detector 101, so as to adjust the reset delay time sent to the phase frequency detector 101 according to the calibration enable signal.
Referring to fig. 4, fig. 4 is a circuit structure diagram of a charge pump module according to an embodiment of the invention. The first charge pump module 102 and the second charge pump module 103 of this embodiment have the same structure, and include a charge pump unit 1021 and a current calibration array unit 1022 connected to the charge pump unit 1021, where the current calibration array unit 1022 is connected to the first calibration logic module 106, and is configured to obtain a mismatch current calibration code from the first calibration logic module 106 in a calibration mode, and perform current calibration on the charge pump unit 1021 by using the mismatch current calibration code to eliminate current mismatch in the charge pump unit 1021.
As shown in fig. 4, the charge pump module of this embodiment is a charge pump with programmable binary compensation current sources, wherein the left side is the existing charge pump structure, and the right side is the current calibration array unit modified and added in this embodiment, that is, the programmable binary compensation current sources, wherein SW 1 And SWB 1 Are a pair of opposite signals.
Specifically, the working principle of the charge pump module is as follows:
MOS transistor M 1 、M 2 、M 3 、M 19 、M 16 、M 17 、M 18 Forming a mirror current source, and providing static bias current for the charge pump by a leftmost band-gap reference source; using source-side controlled charge pump architecture, M 5 、M 6 、M 14 、M 15 The charge pump charge-discharge control tube has a gate terminal for receiving output signals UP, UPB, DN and DNB generated by a previous stage phase frequency detector to control whether the charge pump is charged or discharged, wherein UP and UPB are opposite signals, and DN and DNB are opposite signals. The drain ends of the control tubes are respectively connected with a group of current calibration arrays.
Specifically, a current copying branch circuit is adopted for the pull-up current and the pull-down current, the charge and discharge currents of the charge pump are mirrored in the same current, the consistency of the charge and discharge currents is guaranteed to the maximum extent, and the current mismatch of the charge pump is reduced. MOS transistor M 8 、M 9 、M 11 、M 12 The non-ideal charge effect of the switching tube in the switching process is reduced to influence the output node.
Further, in order to eliminate the spurious component caused by the mismatch of the charge pump current, a current calibration array unit 1022 is disposed in the charge pump module 102 of the present embodiment, and the current calibration array unit 1022 includes a pull-up current calibration array and a pull-down current calibration array. The pull-up current calibration array comprises n bit first subunits connected in series, and each bit first subunit is provided with a complementary switch tube M A And M B And a current source tube M C The calibration current of the n-bit first subunit is gradually increased by multiplying two proportions; similarly, the pull-down current calibration array comprises n-bit second sub-units connected in series, and the second sub-unit of each bit is provided with a complementary switch tube M D And M E And a current source tube M F And the calibration current of the n-bit second subunit is gradually increased by multiplying by two.
When the loop is locked, the loop of the phase-locked loop is switched to a calibration mode, and when mismatch is detected in the charge pump, the first calibration logic module 106 encodes mismatch current and controls the pull-up current calibration array and the pull-down current calibration array to perform current calibration on the charge pump, so that the current mismatch of the charge pump in the locked loop is eliminated.
Specifically, the first calibration logic 106 outputs SW if the pull-up current needs to be calibrated 2 <n:1>Are all low, and their corresponding opposite signals SWB 2 <n:1>Are all high, so that M in each second subunit D Are all turned off, and M E Will be conducted to result in M F Is pulled down to GND, M F All are turned off. At this time, the pull-up current calibration array selects a part of bits to access according to the mismatch value, and if the first bit needs to be accessed, the first calibration logic module 106 outputs SW 1 <1>At high level, corresponding to the opposite signal SWB 1 <1>Is low, so that M A Off, M B Conducting, bias voltage V B1 Will be transmitted to M C Of the grid electrode, M C Will conduct and provide a nominal current. The other cases are similar.
The second charge pump module 103 has the same structure as the first charge pump module 102, and is controlled by the second calibration logic module 107, and the process is similar to that of the first charge pump module 102, which is not repeated herein.
Further, the first loop filter module 104 of the present embodiment includes a first capacitor C I1 A second capacitor C I2 A third capacitor C I A first switch S 1 And a second switch S 2 Wherein the first capacitor C I1 A first switch S connected between the ground terminal and the output terminal of the first charge pump module 102 1 And a second capacitor C I2 Connected in series between the ground terminal and the output terminal of the first charge pump module 102; first switch S 1 A second switch S 2 And a third capacitance C I Connected in series between ground and the output of the first charge pump module 102.
Further, the second loop filter module includes a fourth circuitContainer C P1 A fifth capacitor C P2 A sixth capacitor C P A first resistor R P And a third switch S 3 And a fourth switch S 4 And a fifth switch S 5 Wherein the fourth capacitance C P1 Connected between the ground terminal and the output terminal of the second charge pump module 103, and a third switch S 3 And a first resistor R P Is connected in series with the output end of the second charge pump module 103 and the common mode voltage V CM Between, a sixth capacitance C P One end of the first switch is connected to the ground end, and the other end is connected to the third switch S 3 And a first resistor R P To (c) to (d); fourth switch S 4 Connected at a common-mode voltage V CM And the output terminal of the second charge pump module 103, a fifth switch S 5 A fifth capacitor C connected between the input of the first calibration logic 106 and the common mode voltage VCM P2 Connected between the input of the first calibration logic block 106 and ground.
It should be noted that the combination of the first loop filter block 104 and the second loop filter block 105 of the present embodiment is a second-order filter in nature, but in other embodiments, the case where the first loop filter block 104 and the second loop filter block 105 constitute a third-order filter is also applicable.
The first calibration logic 106 includes a first comparator COM1, a first register unit and a first calibration logic unit, wherein a positive input terminal of the first comparator COM1 is connected to an output terminal of the first charge pump module 102, and a negative input terminal of the first comparator COM1 is connected to the first switch S 1 And a second switch S 2 The output end of the first register unit is connected with the output end of the first comparator COM1, and the first comparator COM1 is used for comparing voltage values representing mismatch conditions to output mismatch comparison results; the first register unit is connected between the first comparator COM1 and the first calibration logic unit, and is used for transmitting the mismatch comparison result to the first calibration logic unit; the first calibration logic unit is connected to the first charge pump module 102, and configured to generate a calibration logic signal according to the mismatch comparison result, so as to control the first charge pump module 102 to perform current compensation.
Further, the second calibration logic module 107 comprises a second comparator COM2 and a second deposit receiptA first calibration logic unit, wherein the positive input terminal of the first comparator COM2 is connected to the output terminal of the first charge pump module 103, and the negative input terminal is connected to the fifth switch S 5 And a fifth capacitance C P2 The output end of the first register unit is connected with the first register unit; the second register unit is connected between the second comparator COM2 and the second calibration logic unit, and the output terminal of the second calibration logic unit is connected to the second charge pump module 103.
Referring to fig. 5 and fig. 6, fig. 5 is a circuit state diagram of the automatic current calibration charge pump circuit according to the embodiment of the present invention during calibration; fig. 6 is a flowchart illustrating calibration of an automatic current calibration charge pump circuit applied to a dual-path phase-locked loop according to an embodiment of the present invention. The working principle of the automatic current calibration charge pump circuit of the embodiment is as follows:
the first step is as follows: when the charge pump reaches the locked state, the calibration logic modules (the first calibration logic module 106 and the second calibration logic module 107) enter an initial preparation phase.
The second step is that: switch S 1 、S 2 And S 3 And the circuit is completely disconnected, so that a main loop is disconnected, wherein the main loop refers to a closed loop formed by the phase frequency detector, the charge pump, the loop filter, the voltage controlled oscillator, the frequency divider and the phase frequency detector. Due to the capacitance C I1 And C I2 Much less than C I And C is I1 Capacity value equal to C I2 So that when the switch is opened, the capacitor C I1 And C I2 The charge on is equal. Meanwhile, the adjustable dead zone prevention delay unit 1103 adjusts the reset delay time of the phase frequency detector 101 from 200ps to 2ns, and the input end of the signal switching unit 1102, which is originally connected with the feedback signal of the frequency divider 109, is connected to the reference signal instead, so that both input ends of the phase frequency detector 101 are connected to the reference signal, and it is ensured that the conduction time of the pull-up current and the pull-down current of the first charge pump module 102 and the second charge pump module 103 are the same. The control voltage VC of the voltage-controlled oscillator 108 is constant in the short time, the voltage V on the proportional path is constant by the integral path and the proportional path P Is still close to the common mode voltage V CM . That is, the vco 108 is still in an almost locked state, which ensures that only the vco output is available during calibrationA slight change.
The third step: the calibration is started, and in the first reference clock period, the conduction time of the charge pump charge-discharge current is ensured to be the same, and then the capacitor C is supplied I1 Charging, then the capacitor C I1 And a capacitor C I2 The difference in the upper voltages reflects the mismatch of the charge pump currents. The positive and negative input ends of the first comparator COM1 are connected with V I1 And V I2 And the output is connected with the successive approximation control logic for controlling the 5bit compensation charge pump. To V I1 And V I2 Comparing, if the first comparator COM1 outputs 1, indicating I UP >I DN Hold of I UP Unchanged, for I DN Compensation is carried out; conversely, if the first comparator COM1 output is 0, it represents that I UP <I DN Hold of I DN Unchanged, for I UP And (6) compensating. After the compensation operation is completed, the capacitor C I1 And C I2 And C I The connection will be resumed until the next reference period.
The fourth step: the same comparison operation will be performed when the next reference period arrives. If the current comparison result is assumed to be 1, the first comparison result is 1,I DN The MSB (most significant bit) compensation current of (1) will be turned off and the next highest bit compensation current turned on, thereby reducing current mismatch. If the current comparison result is assumed to be 0, the first comparison result is 1,I DN The MSB (most significant bit) compensation current is still turned on and then the next higher bit compensation current is turned on, thereby reducing current mismatch. The above operation is then repeated until the LSB (least significant bit) current compensation is completed.
Since the calibration schemes are similar in both paths, the integration path is taken as an example for further explanation. Referring to fig. 7, fig. 7 is a calibration timing diagram of an automatic current calibration charge pump circuit applied to a dual-path phase-locked loop according to an embodiment of the present invention. After the first cycle, the unmatched current will be charged to C I1 And is then reacted with C I2 Are compared. If the output of the first comparator COM1 is 1, I is represented UP >I DN Then I UP Not to be compensated, SW 1 <n:1>All are 0, and SW 2 <n:1>Firstly, the highest position is 1, if the compensation current is too large, the highest position is 0, the next highest position is 1, and the like, until the mismatch is smaller than the rated value of the compensation current of the lowest position after calibration, the calibration is completed. I.C. A UP The situation that needs to be compensated is the opposite.
It should be noted that the calibration process of the proportional path is the same as that of the integral path, and the mismatch current is first charged to C P1 Above, then compare C P1 And C P2 And calibration is performed sequentially, which will not be described herein.
The automatic current calibration charge pump circuit applied to the dual-path phase-locked loop enables the matching degree of the pull-up current and the pull-down current of the charge pump to be greatly improved, the ripple size on the voltage-controlled oscillator control voltage after the system is stabilized is reduced, and the reference stray of the phase-locked loop is greatly inhibited, so that the phase-locked loop achieves better performance. The dynamic current calibration charge pump circuit enables the double-path phase-locked loop to achieve less than 5% of charge pump mismatch, so that structural stability is obtained, stray is reduced, delay time of the phase frequency detector is prolonged, load capacitance is reduced, mismatch current can be identified in a single reference period, the difference value between rising current and falling current can be identified in the single reference period, successive approximation control logic is adopted for compensation, calibration time of the circuit is shortened, and calibration performance is superior.
The foregoing is a further detailed description of the invention in connection with specific preferred embodiments and it is not intended to limit the invention to the specific embodiments described. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (6)
1. An automatic current calibration charge pump circuit applied to a dual-path phase-locked loop is characterized by comprising a phase frequency detector (101), a first charge pump module (102), a second charge pump module (103), a first loop filter module (104), a second loop filter module (105), a first calibration logic module (106), a second calibration logic module (107), a voltage-controlled oscillator (108), a frequency divider (109) and a detection module (110),
the first charge pump module (102), the first loop filter module (104) and the first calibration logic module (106) form an integral path, the second charge pump module (103), the second loop filter module (105) and the second calibration logic module (107) are connected to form a proportional path, and the voltage-controlled oscillator (108) is tuned and controlled by two control paths of the proportional path and the integral path;
the phase frequency detector (101) is used for generating a charging pulse and a discharging pulse according to a phase difference between a reference clock signal and an output signal from the detection module (110), controlling the first charge pump module (102) to charge and discharge the first loop filter module (104) and controlling the second charge pump module (103) to charge and discharge the second loop filter module (105);
the first loop filter module (104) is configured to filter the charge pump current input by the first charge pump module (102) to generate a first filtered voltage, and output the first filtered voltage to the voltage controlled oscillator (108);
the second loop filter module (105) is configured to filter the charge pump current input by the second charge pump module (103) to generate a second filtered voltage, and output the second filtered voltage to the voltage controlled oscillator (108);
the first calibration logic module (106) is configured to obtain a mismatch condition of the first charge pump module (102) and generate a calibration logic signal according to the mismatch condition to control the first charge pump module (102) to adjust a charge pump current;
the second calibration logic module (107) is configured to acquire a mismatch condition of the second charge pump module (103) and generate a calibration logic signal according to the mismatch condition to control the second charge pump module (103) to adjust the charge pump current;
the voltage controlled oscillator (108) for generating an output clock signal having a variable frequency from the first filtered voltage and the second filtered voltage;
the frequency divider (109) is used for dividing the frequency of the output clock signal from the voltage-controlled oscillator (108) by a preset frequency division value to obtain a feedback signal;
the detection module (110) is used for judging whether a locking state is entered or not according to a feedback signal from the frequency divider (109) and generating an output signal to be sent to the phase frequency detector (101), wherein,
the first calibration logic block (106) comprises a first comparator COM1, a first register unit and a first calibration logic unit, wherein,
a positive input end of the first comparator COM1 is connected to an output end of the first charge pump module (102), a negative input end of the first comparator COM1 is connected to the first loop filter module, an output end of the first comparator COM1 is connected to the first register unit, and the first comparator COM1 is configured to compare a voltage value representing a mismatch condition to output a mismatch comparison result;
the first register unit is connected between the first comparator COM1 and the first calibration logic unit, and is used for transmitting the mismatch comparison result to the first calibration logic unit;
the first calibration logic unit is connected with the first charge pump module (102) and used for generating a calibration logic signal according to the mismatch comparison result so as to control the first charge pump module (102) to perform current compensation;
the second calibration logic module (107) comprises a second comparator COM2, a second register unit and a second calibration logic unit, wherein,
the positive input end of the second comparator COM2 is connected to the output end of the second charge pump module (103), the negative input end of the second comparator COM2 is connected to the second loop filter module, and the output end of the second comparator COM2 is connected to the second register unit; the second register unit is connected between the second comparator COM2 and the second calibration logic unit, and the output end of the second calibration logic unit is connected with the second charge pump module (103).
2. The automatic current calibration charge pump circuit applied to a dual path phase locked loop of claim 1, wherein the detection module (110) comprises a lock detector (1101), a signal switching unit (1102), and an adjustable anti-dead-time delay unit (1103), wherein,
an input end of the lock detector (1101) is connected with the frequency divider (109) and is used for generating a calibration enabling signal according to the feedback signal from the frequency divider (109);
the input end of the signal switching unit (1102) is respectively connected with the lock detector (1101), the frequency divider (109) and a reference signal input end, and is used for switching an output signal into a reference signal or a feedback signal from the frequency divider (109) according to the calibration enable signal and sending the reference signal or the feedback signal to the phase frequency detector (101);
the input end of the adjustable dead zone time delay unit (1103) is connected with the locking detector (1101), and the output end of the adjustable dead zone time delay unit is connected with the phase frequency detector (101) and used for adjusting the reset delay time sent to the phase frequency detector (101) according to the calibration enabling signal.
3. The automatic current calibration charge pump circuit for a dual path phase locked loop according to claim 1, wherein the first charge pump block (102) comprises a charge pump unit (1021) and a current calibration array unit (1022) connected to the charge pump unit (1021), wherein,
the current calibration array unit (1022) is connected to the first calibration logic module (106) and configured to obtain a mismatch current calibration code from the first calibration logic module (106) in a calibration mode, and perform current calibration on the charge pump unit (1021) using the mismatch current calibration code to eliminate current mismatch in the charge pump unit (1021).
4. The automatic current calibration charge pump circuit applied to a dual-path phase-locked loop of claim 3, wherein the current calibration array unit (1022) comprises a pull-up current calibration array and a pull-down current calibration array, wherein,
the pull-up current calibration array comprises n-bit first subunits connected in series, each of which is provided with a plurality of N-bit first subunitsThe first subunits are all provided with complementary switch tubes M A And M B And a current source tube M C The calibration current of the n-bit first subunit is gradually increased by multiplying by two;
the pull-down current calibration array comprises n second subunits connected in series, and the second subunit of each bit is provided with a complementary switch tube M D And M E And a current source tube M F And the calibration current of the n-bit second subunit is incremented by a multiplication of two proportions from time to time.
5. The automatic current calibration charge pump circuit for a dual path phase locked loop of claim 1 wherein said first loop filter block (104) comprises a first capacitor C I1 A second capacitor C I2 A third capacitor C I A first switch S 1 And a second switch S 2 Wherein the first capacitor C I1 Connected between ground and the output of the first charge pump module (102), the first switch S 1 And the second capacitor C I2 Is connected in series between a ground terminal and an output terminal of the first charge pump module (102); the first switch S 1 The second switch S 2 And said third capacitance C I Is connected in series between ground and the output of the first charge pump module (102).
6. The automatic current calibration charge pump circuit for a dual path phase locked loop of claim 1, wherein the second loop filter module comprises a fourth capacitor C P1 A fifth capacitor C P2 And a sixth capacitor C P A first resistor R P And a third switch S 3 And a fourth switch S 4 And a fifth switch S 5 Wherein the fourth capacitance C P1 Connected between a ground terminal and an output terminal of the second charge pump module (103), the third switch S 3 And the first resistor R P Is connected in series with the output end of the second charge pump module (103) and the common-mode voltage V CM Between, the sixth capacitance C P Is connected to ground at one endOne end of the other end is connected to the third switch S 3 And the first resistor R P To (c) to (d); the fourth switch S 4 Connected at a common-mode voltage V CM And the output end of the second charge pump module (103), the fifth switch S 5 Connected between the input of the first calibration logic block (106) and the common-mode voltage V CM Of said fifth capacitance C P2 Is connected between the input of the first calibration logic block (106) and ground.
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