WO2023124558A1

WO2023124558A1 - Phase-locked loop circuit, control method, charge pump, and chip

Info

Publication number: WO2023124558A1
Application number: PCT/CN2022/130899
Authority: WO
Inventors: 蔡炎; 刘帅锋
Original assignee: 合肥市芯海电子科技有限公司
Priority date: 2021-12-31
Filing date: 2022-11-09
Publication date: 2023-07-06
Also published as: CN114301451A

Abstract

The present application provides a phase-locked loop circuit, a control method, a charge pump, and a chip. The phase-locked loop circuit comprises: a phase frequency detector configured to receive a reference clock signal and an output signal of a frequency divider, and generate a charging/discharging control signal; a charge pump module configured to determine charging or discharging, determine the current magnitude of a charge pump proportional unit and a charge pump integral unit, and generate corresponding charging current or discharging current according to the determined charging or discharging and the current magnitude of the charge pump proportional unit and the charge pump integral unit; a loop filter configured to filter the charging current or discharging current to obtain a control voltage signal; a voltage-controlled oscillator configured to generate a phase-locked loop output signal having a preset frequency; and the frequency divider configured to perform frequency division on the phase-locked loop output signal, and input the signal subjected to frequency division to the phase frequency detector as the output signal. The phase-locked loop circuit provided by the present application can greatly reduce stray in the phase-locked loop.

Description

Phase-locked loop circuit, control method, charge pump and chip

This application claims the priority of the Chinese patent application with the application number 202111674334.3 and the application title "Phase-locked loop circuit, control method, charge pump and chip" filed with the China Patent Office on December 31, 2021, the entire content of which is incorporated by reference incorporated in this application.

technical field

The present application relates to the technical field of phase-locked loops, in particular to a phase-locked loop circuit, a control method, a charge pump and a chip.

Background technique

A phase-locked loop is a circuit that synchronizes the phase and frequency of an output frequency-divided signal generated by a voltage-controlled oscillator with an input reference signal. In the synchronous state, the phase difference between the output signal of the oscillator and the input reference signal is 0 or a fixed constant. If the phase difference between the two changes, there is a feedback control mechanism in the phase-locked loop to adjust the output of the oscillator so that the phase difference decreases and finally reaches the locked state. In this circuit, the phase of the output signal is actually locked to the phase of the input reference signal, which is why the circuit is called a phase-locked loop. The spurs in the existing phase-locked loop circuit are relatively high, and the high spurs will seriously affect the use effect of the phase-locked loop.

Contents of the invention

Based on this, the application provides a phase-locked loop circuit, including a phase-frequency detector, a charge pump module, a loop filter, a voltage-controlled oscillator and a frequency divider, and the charge pump module includes a charge pump proportional unit and a charge pump module. pump integral unit;

The frequency and phase detector is configured to receive a reference clock signal and an output signal of the frequency divider, and generate a charge and discharge control signal according to the reference clock signal and the output signal of the frequency divider;

The charge pump module is used to receive the charge and discharge control signal, determine charging or discharging according to the charge and discharge control signal, and is also used to determine the charge pump proportional unit and charge according to the size of the capacitor in the loop filter. The current magnitude of the pump integration unit, and according to the determined charge or discharge and the current magnitude of the charge pump proportional unit and the charge pump integration unit, generate a corresponding charging current or discharge current;

The loop filter is used to filter the charging current or discharging current to obtain a control voltage signal;

The voltage-controlled oscillator is used to generate a phase-locked loop output signal of a preset frequency according to the control voltage signal;

The frequency divider is used to divide the frequency of the output signal of the phase-locked loop, and use the frequency-divided signal as an output signal to input to the frequency and phase detector.

Optionally, the charge pump module further includes a dynamic unit matching module, and the dynamic unit matching module is used to determine the current size of the charge pump proportional unit and the charge pump integral unit according to the size of the capacitor in the loop filter .

Optionally, both the charge pump proportional unit and the charge pump integral unit include several current mirror units;

The dynamic unit matching module is also used to determine the conduction number of the current mirror units in the charge pump proportional unit and the charge pump integral unit according to the current size of the charge pump proportional unit and the charge pump integral unit, and according to The conduction numbers of the current mirror units in the charge pump proportional unit and the charge pump integral unit respectively conduct conduction to the current mirror units in the charge pump proportional unit and the charge pump integral unit.

Optionally, the charge pump proportional unit is used to generate a corresponding charge current or discharge current according to the determined charge or discharge, and the number of conduction current mirror units in the charge pump proportional unit; the charge pump integral unit , for generating a corresponding charging current or discharging current according to the determined charging or discharging, and the number of conducting current mirror units in the charge pump integration unit.

Optionally, the charge pump proportional unit includes a first charging unit and a first discharging unit, the first charging unit includes a first P-type field effect transistor, and the first discharging unit includes a first N-type field effect transistor ; The gate of the first P-type field effect transistor is used to receive the first bias voltage, the source of the first P-type field effect transistor is connected to the power supply, and the drain of the first P-type field effect transistor is connected to the power supply. The dynamic unit matching module; the gate of the first N-type field effect transistor is used to receive the second bias voltage, the source of the first N-type field effect transistor is grounded, and the first N-type field effect transistor The drain of the tube is connected to the dynamic unit matching module.

Optionally, the charge pump integration unit includes a second charging unit and a second discharging unit, the second charging unit includes a second P-type field effect transistor, and the second discharging unit includes a second N-type field effect transistor ; The gate of the second P-type field effect transistor is used to receive the first bias voltage, the source of the second P-type field effect transistor is connected to the power supply, and the drain of the second P-type field effect transistor is connected to the The dynamic unit matching module; the gate of the second N-type field effect transistor is used to receive the second bias voltage, the source of the second N-type field effect transistor is grounded, and the second N-type field effect transistor The drain is connected to the dynamic cell matching module.

Optionally, the first charging unit, the first discharging unit, the second charging unit and the second discharging unit respectively include several current mirror units; the dynamic unit matching module includes a first dynamic unit a matcher and a second dynamic unit matcher;

The first dynamic unit matcher is used for determining the conduction number of the current mirror units in the first charging unit and the second charging unit according to the size of the capacitor in the loop filter, and according to the first charging The conduction number of the current mirror unit in the unit and the second charging unit is respectively conducting the current mirror unit in the first charging unit and the second charging unit;

The second dynamic unit matcher is used to determine the conduction number of the current mirror units in the first discharge unit and the second discharge unit according to the size of the capacitor in the loop filter, and according to the first discharge The number of conduction current mirror units in the cell and the second discharge unit respectively conducts conduction to the current mirror units in the first discharge unit and the second discharge unit.

Optionally, performing conduction on the current mirror units in the first charging unit and the second charging unit respectively, specifically includes conducting random conduction on the current mirror units in the first charging unit and the second charging unit respectively; Turning on the current mirror units in the first discharge unit and the second discharge unit respectively includes, respectively conducting random conduction on the current mirror units in the first discharge unit and the second discharge unit.

Optionally, the charge pump module further includes a first switch, a second switch, a third switch, and a fourth switch; one end of the first switch is connected to the first dynamic unit matcher, and one end of the first switch The other end is connected to one end of the second switch and the voltage-controlled oscillator, the other end of the second switch is connected to the second dynamic unit matcher, one end of the third switch is connected to the first dynamic unit matcher, and the second end is connected to the second dynamic unit matcher. The other end of the three switches is connected to one end of the fourth switch and the voltage-controlled oscillator, and the other end of the fourth switch is connected to the second dynamic unit matcher.

Optionally, the loop filter includes an integrating capacitor Ci, a proportional capacitor Cp, a resistor Rp and a buffer BUF, one end of the proportional capacitor Cp is connected to the other end of the first switch, and the other end of the proportional capacitor Cp One end and one end of the integrating capacitor Ci are grounded, the other end of the integrating capacitor is connected to the other end of the third switch and the input end of the buffer, the output end of the buffer is connected to one end of the resistor Rp, the The other end of the resistor Rp is connected to one end of the proportional capacitor Cp.

The present application also provides a phase-locked loop control method, comprising the following steps:

Obtaining a reference clock signal and a frequency division signal, and generating a charge and discharge control signal according to a phase difference between the reference clock signal and the frequency division signal;

Determine the charge or discharge according to the charge and discharge control signal, determine the current size of the charge pump proportional unit and the charge pump integral unit according to the size of the capacitor in the loop filter, and determine the charge or discharge according to the determined charge or discharge and the charge pump The current magnitude of the integration unit and the charge pump integration unit generates the corresponding charging current or discharging current;

filtering the charging current or discharging current to obtain a control voltage signal;

generating a phase-locked loop output signal of a preset frequency according to the control voltage signal;

Perform frequency division on the phase-locked loop output signal to obtain the frequency-divided signal.

The present application also provides a charge pump. The charge pump includes a charge pump proportional unit and a charge pump integral unit. , is also used to determine the current magnitude of the charge pump proportional unit and the charge pump integral unit, and generate the corresponding charging current or discharge current according to the determined charging or discharging and the current magnitude of the charge pump proportional unit and the charge pump integrating unit.

The present application also provides a chip, including the phase-locked loop circuit or the charge pump described in any of the above-mentioned technical solutions.

The beneficial effect of the present application is that the charge and discharge control signal is generated by the frequency and phase detector according to the reference clock signal and the output signal of the frequency divider, and the charge and discharge control signal is received by the charge pump module, and determined according to the charge and discharge control signal. Charging or discharging, according to the size of the capacitor in the loop filter, determine the current size of the charge pump proportional unit and the charge pump integral unit, and according to the determined charge or discharge and the current of the charge pump proportional unit and the charge pump integral unit The magnitude of the current generates the corresponding charging current or discharging current; through the loop filter, the charging current or discharging current is filtered to obtain the control voltage signal; through the voltage-controlled oscillator, the phase-locked loop output signal of the preset frequency is generated; through The frequency divider divides the frequency of the phase-locked loop output signal, and the frequency-divided signal is used as an output signal, and is input to the frequency and phase detector; while realizing the phase-locked loop function, the charge pump is optimized. The current mismatch greatly reduces the spurs in the phase-locked loop.

Description of drawings

Fig. 1 is the circuit block diagram of the phase-locked loop circuit of the first embodiment of the present application;

Fig. 2 is the circuit principle diagram of the phase-locked loop circuit of the first embodiment of the present application;

FIG. 3 is a functional block diagram of the charge pump module of the first embodiment of the present application;

4 is a schematic circuit diagram of the charge pump module of the first embodiment of the present application;

FIG. 5 is a schematic flowchart of a phase-locked loop control method according to a second embodiment of the present application.

Detailed ways

In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Preferred embodiments of the application are shown in the accompanying drawings. However, the present application can be embodied in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the application more thorough and comprehensive.

It should be noted that when an element is referred to as being “fixed” to another element, it can be directly on the other element or there can also be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or intervening elements may also be present.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of the application are only for the purpose of describing specific embodiments, and are not intended to limit the application.

FIG. 1 is a circuit block diagram of a phase-locked loop circuit according to the first embodiment of the present application. It should be noted that the circuit of the present application is not limited to the schematic circuit diagram shown in FIG. 1 if substantially the same result is obtained. As shown in Figure 1, the phase-locked loop circuit includes a frequency and phase detector PFD, a charge pump module CP, a loop filter LPF, a voltage-controlled oscillator VCO and a frequency divider DIV, and the charge pump module CP includes a charge pump Proportional unit CPP and charge pump integral unit CPI;

The phase frequency detector PFD is used to receive a reference clock signal and the output signal of the frequency divider DIV, and generate a charge and discharge control signal according to the reference clock signal and the output signal of the frequency divider DIV;

The charge pump module CP is used to receive the charge and discharge control signal, determine charge or discharge according to the charge and discharge control signal, and determine the charge pump proportional unit according to the size of the capacitor in the loop filter LPF CPP and the current magnitude of the charge pump integration unit CPI, and generate a corresponding charging current or discharge current according to the determined charging or discharging and the current magnitude of the charge pump integration unit CPP and the charge pump integration unit CPI;

The loop filter LPF is used to filter the charging current or discharging current to obtain a control voltage signal;

The voltage-controlled oscillator VCO is used to generate a phase-locked loop output signal of a preset frequency according to the control voltage signal;

The frequency divider DIV is used to divide the frequency of the phase-locked loop output signal, and use the frequency-divided signal as an output signal to input to the frequency and phase detector PFD.

It should be noted that, in the embodiment of the present application, the frequency and phase detector is used to generate the charge and discharge control signal according to the phase difference between the reference clock signal and the output signal of the frequency divider, and the dynamic unit matching module is used according to the capacitance in the loop filter. The size of the charge pump proportional unit and the conduction number of the current mirror unit in the charge pump integral unit are determined, and according to the conduction number of the current mirror unit in the charge pump proportional unit and the charge pump integral unit, respectively adjust the charge pump proportional unit And the current mirror unit in the integration unit of the charge pump is turned on, and the charging current or discharging current is filtered by the loop filter to obtain the control voltage signal, and the phase-locked loop of the preset frequency is generated by the voltage-controlled oscillator according to the control voltage signal Output signal; while realizing the function of the phase-locked loop, the current mismatch in the charge pump is optimized, which greatly reduces the spurs in the phase-locked loop.

As an implementation, the phase-locked loop circuit includes a phase-frequency detector PFD, a charge pump module CP, a loop filter LPF, a voltage-controlled oscillator VCO, and a frequency divider DIV; the phase-frequency detector is used to detect an input reference clock The phase difference between clkin and the feedback clock clkdiv after frequency division, output control signals UP and DN, the control signal UP controls the charging of the charge pump proportional unit CPP and the charge pump integral unit CPI, and the control signal DN controls the charge pump proportional unit CPP and charge The pump integral unit CPI discharges; the output currents of the charge pump proportional unit CPP and the charge pump integral unit CPI are Icpp and Icpi respectively, and Icpp and Icpi get the control voltage Vc of the voltage-controlled oscillator VCO after passing through the loop filter LPF, and Vc will The output clock frequency of the voltage-controlled oscillator VCO is adjusted, and the current returns to the frequency and phase detector PFD after being divided by the frequency divider DIV, thus forming a feedback loop.

In some embodiments, the loop filter includes an integrating capacitor Ci, a proportional capacitor Cp, a resistor Rp, and a buffer BUF, one end of the proportional capacitor Cp is connected to the other end of the first switch, and the proportional capacitor Cp The other end of the integration capacitor Ci and one end of the integration capacitor Ci are grounded, the other end of the integration capacitor is connected to the other end of the third switch and the input end of the buffer, and the output end of the buffer is connected to one end of the resistor Rp, The other end of the resistor Rp is connected to one end of the proportional capacitor Cp.

As an embodiment, the circuit schematic diagram of the phase-locked loop circuit is as shown in Figure 2, where clkin is the input reference clock, clkdiv is the feedback clock after frequency division, and the loop filter LPF includes an integrating capacitor Ci , proportional capacitor Cp, resistor Rp and buffer BUF, where the transfer function of LPF is

The loop gain of the PLL circuit is approximately

The zero point of the loop gain is

The second pole of the loop gain is

The loop phase margin PM of the phase-locked loop circuit is

Among them, K _vco is the gain of the voltage controlled oscillator, N is the frequency division coefficient, Icp is the unit current, which is equal to the current size of the charge pump integral unit CPI, B is the current of the charge pump proportional unit CPP and the charge pump integral unit CPI The ratio of current magnitude. It can be seen from the above formula that the phase margin is related to the ratio of B*Ci and Cp. If PM=60°, only B*Ci is 13 times of Cp, which means that setting the current coefficient B can reduce the capacitance The size requirement of Ci realizes the integration of LPF on-chip with small area and low cost.

In addition, since the capacitance per unit area of MOM capacitors and MIM capacitors becomes smaller under the advanced size technology, the realization of large capacitance on the chip usually needs to rely on MOS capacitors, so reducing the capacitance Ci can effectively reduce the leakage caused by the gate terminal of the MOS transistor. The phase-locked loop loop is periodically perturbed, thereby suppressing spurs.

As an implementation, the loop unity gain bandwidth of the phase-locked loop circuit is

natural frequency

damping factor

For a phase-locked loop circuit, consider that the input reference comes from a high-precision crystal oscillator, and its phase noise performance is very good. At this time, the loop bandwidth design should be as close as possible to 1/20 of the input reference, so that the phase noise suppression effect of the ring oscillator VCO most.

In some embodiments, the charge pump module further includes a dynamic unit matching module, and the dynamic unit matching module is used to determine the ratio of the charge pump proportional unit and the charge pump integral unit according to the size of the capacitor in the loop filter. Current size.

As an implementation manner, a functional block diagram of the charge pump module is shown in FIG. 3 . The charge pump module in FIG. 3 includes a charge pump proportional unit 301 , a charge pump integral unit 302 and a dynamic unit matching module 303 .

In some embodiments, the charge pump proportional unit and the charge pump integral unit both include several current mirror units;

As an implementation, according to the conduction number of the current mirror units in the charge pump proportional unit and the charge pump integral unit, the current mirror units in the charge pump proportional unit and the charge pump integral unit are respectively randomly turned on ; It can not only eliminate the mismatch between the charge pump proportional unit and the charge pump integral unit, its own charging current and discharge current, but also eliminate the mismatch of the current ratio between the charge pump integral unit and the charge pump proportional unit.

As an implementation manner, a schematic circuit diagram of the charge pump module is shown in FIG. 4 . The two circuits of the charge pump proportional unit CPP and the charge pump integral unit CPI in Figure 2 are combined in Figure 4 for matching and logic control.

In some embodiments, the charge pump proportional unit is used to generate a corresponding charge current or discharge current according to the determined charge or discharge, and the number of current mirror units in the charge pump proportional unit; The integrating unit is configured to generate a corresponding charging current or discharging current according to the determined charging or discharging, and the number of conducting current mirror units in the charge pump integrating unit.

As an implementation, the charge pump module includes P-type field effect transistors PM1~PMK and N-type field effect transistors, wherein K=B+1, B is the current of the charge pump proportional unit CPP and the current of the charge pump integral unit CPI ratio of size. It should be noted that K can also be an integer multiple of B+1. At this time, the ratio of the conduction number of the current mirror unit in the charge pump proportional unit to the conduction number of the current mirror unit in the charge pump integration unit is B .

In some embodiments, the charge pump proportional unit includes a first charging unit and a first discharging unit, the first charging unit includes a first P-type field effect transistor, and the first discharging unit includes a first N-type field effect transistor. Effect tube; the gate of the first P-type field effect tube is used to receive the first bias voltage, the source of the first P-type field effect tube is connected to the power supply, and the drain of the first P-type field effect tube Pole connected to the dynamic unit matching module; the gate of the first N-type field effect transistor is used to receive the second bias voltage, the source of the first N-type field effect transistor is grounded, and the first N-type field effect transistor The drain of the field effect transistor is connected to the dynamic unit matching module.

As an implementation manner, the charge pump proportional unit includes a first charging unit and a first discharging unit, the current mirror unit in the first charging unit includes a first P-type field effect transistor, and the first discharging unit includes The first N-type field effect transistor; the gate of the first P-type field effect transistor is connected to the P-type bias voltage, the source of the first P-type field effect transistor is connected to the power supply, and the first P-type field effect transistor The drain of the tube is connected to the dynamic unit matching module; the gate of the first N-type field effect transistor is connected to the N-type bias voltage, the source of the first N-type field effect transistor is grounded, and the first P The drain of the type field effect transistor is connected to the dynamic unit matching module.

As an example, the gate terminals of the P-type field effect transistors PM1 to PMK are all connected to the P-type bias voltage V _biasp , the source terminals are all connected to the power supply voltage VDD, and the drain terminals are connected to the corresponding interface of the dynamic unit matching module; the N field effect transistors The gate terminals of NM1-NMK are all connected to the bias voltage V _biasn of the current mirror, the source terminals are all grounded, and the drain terminals are connected to the corresponding interface of the dynamic unit matching module.

In some embodiments, the charge pump integration unit includes a second charging unit and a second discharging unit, the second charging unit includes a second P-type field effect transistor, and the second discharging unit includes a second N-type field effect transistor. effect tube; the gate of the second P-type field effect tube is used to receive the first bias voltage, the source of the second P-type field effect tube is connected to the power supply, and the drain of the second P-type field effect tube connected to the dynamic unit matching module; the gate of the second N-type field effect transistor is used to receive the second bias voltage, the source of the second N-type field effect transistor is grounded, and the second N-type field effect transistor The drain of the effect transistor is connected to the dynamic unit matching module.

As an implementation manner, the charge pump integration unit includes a second charging unit and a second discharging unit, the current mirror unit in the second charging unit includes a second P-type field effect transistor, and the second discharging unit includes The second N-type field effect transistor; the gate of the second P-type field effect transistor is connected to the P-type bias voltage, the source of the second P-type field effect transistor is connected to the power supply, and the second P-type field effect transistor is connected to the power supply. The drain of the second N-type field effect transistor is connected to the dynamic unit matching module; the gate of the second N-type field effect transistor is connected to the N-type bias voltage, the source of the second N-type field effect transistor is grounded, and the second P-type field effect transistor The drain of the field effect transistor is connected to the dynamic unit matching module.

In some embodiments, the first charging unit, the first discharging unit, the second charging unit and the second discharging unit respectively include several current mirror units; the dynamic unit matching module includes a first a dynamic unit matcher and a second dynamic unit matcher;

As an example, a number of current mirror units in the first charging unit, the first discharging unit, the second charging unit and the second discharging unit respectively form a current mirror, and each current mirror unit is a current An output branch of the mirror.

In some embodiments, turning on the current mirror units in the first charging unit and the second charging unit respectively includes, respectively conducting random conduction on the current mirror units in the first charging unit and the second charging unit Turning on; respectively turning on the current mirror units in the first discharge unit and the second discharge unit, specifically including randomly turning on the current mirror units in the first discharge unit and the second discharge unit respectively.

As an implementation, the first dynamic unit matcher (DEM logic1) receives the current from the P field effect transistors PM1~PMK, and the input clock clkin controls the internal logic of the first dynamic unit matcher to make random selections to generate two currents, the magnitude of which is are B*Icp and Icp, flowing in from the first switch SW1 and the third switch SW3 respectively, and the first switch SW1 and the third switch SW3 are controlled by the output signal UP of the phase frequency detector PFD; the second dynamic unit matcher receives the signal from the N The current of field effect transistors NM1 ~ NMK, the input clock clkin controls the internal logic of the second dynamic unit matcher to make random selection, and generates two currents with the magnitude of B*Icp and Icp, which flow out from the lower ends of the second switch SW2 and the fourth SW4 respectively , the switch is controlled by the output signal DN of the frequency and phase detector PFD; the other end of the first switch SW1 is connected to one end of the second switch SW2 to obtain an output Icpp to the loop filter LPF, and the other end of the third switch SW3 is connected to one end of SW4, The output Icpi is obtained and given to the loop filter LPF.

As an example, the P-type field effect transistors have the same size, and the corresponding output currents are the same, that is, I _P1 =I _P2 =...=I _PK , and the same N-type field effect transistors have the same size, and the corresponding output currents are the same, That is, I _N1 =I _N2 =...=I _NK , and they are all the same as the unit current.

In some embodiments, the charge pump module further includes a first switch SW1, a second switch SW2, a third switch SW3, and a fourth switch SW4; one end of the first switch SW1 is connected to the first dynamic unit matcher , the other end of the first switch SW1 is connected to one end of the second switch SW2 and the voltage-controlled oscillator, the other end of the second switch SW2 is connected to the second dynamic unit matcher, and one end of the third switch SW3 is connected to the The first dynamic unit matcher, the other end of the third switch SW3 is connected to one end of the fourth switch SW4 and the voltage-controlled oscillator, and the other end of the fourth switch SW4 is connected to the second dynamic unit matcher .

The phase-locked loop circuit provided by the embodiment of the present application uses a dual-path structure, sets the output current of the charge pump proportional unit CPP and the charge pump integral unit CPI to a certain ratio, and realizes the two-way current to voltage-controlled oscillation through the loop filter LPF Converter VCO input voltage, the loop of this phase-locked loop circuit can realize the equivalent reduction of the capacitor size in the loop filter LPF by setting the current ratio of the charge pump proportional unit CPP and the charge pump integral unit CPI; based on the dual path The structure, using dynamic unit matching, can not only eliminate the mismatch between the charge pump proportional unit CPP and the charge pump integral unit CPI, its own charging current _Iup and discharge current _Idn , but also eliminate the charge pump integral unit CPI and the charge pump proportional Mismatches in current ratios between cell CPPs effectively suppress spurs.

A schematic flow chart of the phase-locked loop control method of the second embodiment of the present application, as shown in Figure 5, the phase-locked loop control method includes the following steps:

S501. Acquire a reference clock signal and a frequency division signal, and generate a charge and discharge control signal according to the reference clock signal and the frequency division signal;

S502. Determine charging or discharging according to the charging and discharging control signal, determine the current magnitude of the charge pump proportional unit and the charge pump integrating unit according to the size of the capacitor in the loop filter, and determine the charging or discharging according to the determined charging or discharging and the The current magnitude of the charge pump integration unit and the charge pump integration unit generates a corresponding charging current or discharging current;

S503. Filter the charging current or discharging current to obtain a control voltage signal;

S504, generating a phase-locked loop output signal with a preset frequency according to the control voltage signal;

S505. Divide the frequency of the phase-locked loop output signal to obtain the frequency-divided signal.

The third embodiment of the present application provides a charge pump, the charge pump includes a charge pump proportional unit and a charge pump integral unit, the charge pump is used to receive the charge and discharge control signal, and according to the charge and discharge control signal Determine the charge or discharge, and also determine the current of the charge pump proportional unit and the charge pump integral unit, and generate the corresponding charging current according to the determined charge or discharge and the current of the charge pump proportional unit and the charge pump integral unit or discharge current. Wherein, when the charge pump is applied to the phase-locked loop circuit, determine the current size of the charge pump proportional unit and the charge pump integral unit, specifically, according to the size of the capacitor in the loop filter, determine the charge pump proportional unit and the charge pump The current magnitude of the integrating unit.

As an implementation, the above-mentioned charge pump also includes a dynamic unit matching module, and the dynamic unit matching module is used to determine the current size of the charge pump proportional unit and the charge pump integral unit according to the size of the capacitor in the loop filter .

As an implementation manner, the charge pump proportional unit and the charge pump integral unit both include several current mirror units;

As an implementation, the above-mentioned charge pump proportional unit is used to generate a corresponding charge current or discharge current according to the determined charge or discharge, and the conduction number of the current mirror unit in the charge pump proportional unit; the charge pump integral The unit is used to generate a corresponding charging current or discharging current according to the determined charging or discharging, and the number of conducting current mirror units in the charge pump integration unit.

As an implementation, the charge pump proportional unit includes a first charging unit and a first discharging unit, the first charging unit includes a first P-type field effect transistor, and the first discharging unit includes a first N-type field effect transistor. Tube; the gate of the first P-type field effect transistor is used to receive the first bias voltage, the source of the first P-type field effect transistor is connected to the power supply, and the drain of the first P-type field effect transistor connected to the dynamic unit matching module; the gate of the first N-type field effect transistor is used to receive the second bias voltage, the source of the first N-type field effect transistor is grounded, and the first N-type field effect transistor The drain of the effect transistor is connected to the dynamic unit matching module.

As an implementation, the charge pump integration unit includes a second charging unit and a second discharging unit, the second charging unit includes a second P-type field effect transistor, and the second discharging unit includes a second N-type field effect transistor. tube; the gate of the second P-type field effect transistor is used to receive the first bias voltage, the source of the second P-type field effect transistor is connected to the power supply, and the drain of the second P-type field effect transistor is connected to The dynamic unit matching module; the gate of the second N-type field effect transistor is used to receive the second bias voltage, the source of the second N-type field effect transistor is grounded, and the second N-type field effect transistor The drain of the tube is connected to the dynamic unit matching module.

As an implementation manner, the first charging unit, the first discharging unit, the second charging unit and the second discharging unit respectively include several current mirror units; the dynamic unit matching module includes a first a dynamic unit matcher and a second dynamic unit matcher;

As an implementation manner, conducting the current mirror units in the first charging unit and the second charging unit respectively, specifically includes conducting random conduction on the current mirror units in the first charging unit and the second charging unit respectively. Turning on; respectively turning on the current mirror units in the first discharge unit and the second discharge unit, specifically including randomly turning on the current mirror units in the first discharge unit and the second discharge unit respectively.

The charge pump provided in the embodiment of the present application determines the charge or discharge according to the charge and discharge control signal, determines the current magnitude of the charge pump proportional unit and the charge pump integral unit, and determines the charge or discharge according to the determined charge or discharge and the charge pump proportional unit and the charge pump The current magnitude of the integral unit generates the corresponding charging current or discharging current, which can not only eliminate the mismatch between the charge pump proportional unit and the charge pump integral unit, its own charging current and discharge current, but also eliminate the charge pump integral unit and the charge pump Mismatch of current ratio between proportional units, thus effectively suppressing spurs.

The fourth embodiment of the present application provides a chip, including the phase-locked loop circuit or the charge pump described in any of the above-mentioned embodiments.

The technical features of the above embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be It is considered to be within the range described in this specification.

The above examples only express the preferred implementation of the present application, and the descriptions are more specific and detailed, but should not be construed as limiting the scope of the patent. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be determined by the appended claims.

Claims

A phase-locked loop circuit, characterized in that it includes a frequency and phase detector, a charge pump module, a loop filter, a voltage-controlled oscillator and a frequency divider, and the charge pump module includes a charge pump proportional unit and a charge pump integral unit;

The frequency and phase detector is configured to receive a reference clock signal and an output signal of the frequency divider, and generate a charge and discharge control signal according to the reference clock signal and the output signal of the frequency divider;

The charge pump module is used to receive the charge and discharge control signal, determine charging or discharging according to the charge and discharge control signal, and is also used to determine the charge pump proportional unit and charge according to the size of the capacitor in the loop filter. The current magnitude of the pump integration unit, and according to the determined charge or discharge and the current magnitude of the charge pump proportional unit and the charge pump integration unit, generate a corresponding charging current or discharge current;

The loop filter is used to filter the charging current or discharging current to obtain a control voltage signal;

The voltage-controlled oscillator is used to generate a phase-locked loop output signal of a preset frequency according to the control voltage signal;

The frequency divider is used to divide the frequency of the output signal of the phase-locked loop, and use the frequency-divided signal as an output signal to input to the frequency and phase detector.
The phase-locked loop circuit according to claim 1, wherein the charge pump module further includes a dynamic unit matching module, and the dynamic unit matching module is used to determine, according to the size of the capacitor in the loop filter, The current magnitude of the charge pump proportional unit and the charge pump integral unit.
The phase-locked loop circuit according to claim 2, wherein the charge pump proportional unit and the charge pump integral unit each include a plurality of current mirror units;

The dynamic unit matching module is also used to determine the conduction number of the current mirror units in the charge pump proportional unit and the charge pump integral unit according to the current size of the charge pump proportional unit and the charge pump integral unit, and according to The conduction numbers of the current mirror units in the charge pump proportional unit and the charge pump integral unit respectively conduct conduction to the current mirror units in the charge pump proportional unit and the charge pump integral unit.
The phase-locked loop circuit according to claim 3, wherein the charge pump proportional unit is used to generate corresponding Charging current or discharging current; the charge pump integration unit is used to generate a corresponding charging current or discharge current according to the determined charging or discharging and the number of conduction current mirror units in the charge pump integration unit.
The phase-locked loop circuit according to claim 2, wherein the charge pump proportional unit includes a first charging unit and a first discharging unit, the first charging unit includes a first P-type field effect transistor, the The first discharge unit includes a first N-type field effect transistor; the gate of the first P-type field effect transistor is used to receive the first bias voltage, and the source of the first P-type field effect transistor is connected to a power supply, so The drain of the first P-type field effect transistor is connected to the dynamic unit matching module; the gate of the first N-type field effect transistor is used to receive the second bias voltage, and the gate of the first N-type field effect transistor The source is grounded, and the drain of the first N-type field effect transistor is connected to the dynamic unit matching module.
The phase-locked loop circuit according to claim 2 or 5, wherein the charge pump integration unit includes a second charging unit and a second discharging unit, and the second charging unit includes a second P-type field effect transistor, The second discharge unit includes a second N-type field effect transistor; the gate of the second P-type field effect transistor is used to receive the first bias voltage, and the source of the second P-type field effect transistor is connected to a power supply, The drain of the second P-type field effect transistor is connected to the dynamic unit matching module; the gate of the second N-type field effect transistor is used to receive a second bias voltage, and the second N-type field effect transistor The source of the second N-type field effect transistor is connected to the dynamic unit matching module.
The phase-locked loop circuit according to claim 6, wherein the first charging unit, the first discharging unit, the second charging unit and the second discharging unit respectively include several current mirror units ; The dynamic unit matching module includes a first dynamic unit matcher and a second dynamic unit matcher;

The first dynamic unit matcher is used for determining the conduction number of the current mirror units in the first charging unit and the second charging unit according to the size of the capacitor in the loop filter, and according to the first charging The conduction number of the current mirror unit in the unit and the second charging unit is respectively conducting the current mirror unit in the first charging unit and the second charging unit;

The second dynamic unit matcher is used to determine the conduction number of the current mirror units in the first discharge unit and the second discharge unit according to the size of the capacitor in the loop filter, and according to the first discharge The number of conduction current mirror units in the cell and the second discharge unit respectively conducts conduction to the current mirror units in the first discharge unit and the second discharge unit.
The phase-locked loop circuit according to claim 7, wherein the current mirror units in the first charging unit and the second charging unit are respectively turned on, specifically comprising, respectively connecting the first charging unit and the second charging unit The current mirror unit in the second charging unit is randomly turned on; the current mirror unit in the first discharge unit and the second discharge unit are respectively turned on, specifically including, respectively, in the first discharge unit and the second discharge unit. The current mirror cells conduct random conduction.
The phase-locked loop circuit according to claim 7, wherein the charge pump module further comprises a first switch, a second switch, a third switch and a fourth switch; one end of the first switch is connected to the first A dynamic unit matcher, the other end of the first switch is connected to one end of the second switch and the voltage-controlled oscillator, the other end of the second switch is connected to the second dynamic unit matcher, and one end of the third switch is connected to In the first dynamic unit matcher, the other end of the third switch is connected to one end of the fourth switch and the voltage-controlled oscillator, and the other end of the fourth switch is connected to the second dynamic unit matcher.
The phase-locked loop circuit according to claim 8, wherein the loop filter comprises an integrating capacitor Ci, a proportional capacitor Cp, a resistor Rp and a buffer BUF, and one end of the proportional capacitor Cp is connected to the first The other end of the switch, the other end of the proportional capacitor Cp and one end of the integrating capacitor Ci are grounded, the other end of the integrating capacitor is connected to the other end of the third switch and the input end of the buffer, and the buffer The output terminal of the resistor Rp is connected to one end of the resistor Rp, and the other end of the resistor Rp is connected to one end of the proportional capacitor Cp.
A phase-locked loop control method is characterized in that, comprising the following steps:

Obtaining a reference clock signal and a frequency division signal, and generating a charge and discharge control signal according to the reference clock signal and the frequency division signal;

Determine the charge or discharge according to the charge and discharge control signal, determine the current size of the charge pump proportional unit and the charge pump integral unit according to the size of the capacitor in the loop filter, and determine the charge or discharge according to the determined charge or discharge and the charge pump The current magnitude of the integration unit and the charge pump integration unit generates the corresponding charging current or discharging current;

filtering the charging current or discharging current to obtain a control voltage signal;

generating a phase-locked loop output signal of a preset frequency according to the control voltage signal;

Perform frequency division on the phase-locked loop output signal to obtain the frequency-divided signal.
A charge pump, characterized in that the charge pump includes a charge pump proportional unit and a charge pump integral unit, the charge pump is used to receive the charge and discharge control signal, and determine charging or discharging according to the charge and discharge control signal , is also used to determine the current magnitude of the charge pump proportional unit and the charge pump integral unit, and generate the corresponding charging current or discharge current according to the determined charging or discharging and the current magnitude of the charge pump proportional unit and the charge pump integrating unit.
A chip, characterized by comprising the phase-locked loop circuit according to any one of claims 1-10 or the charge pump according to claim 12.