CN117254801A - Phase-locked loop circuit - Google Patents

Phase-locked loop circuit Download PDF

Info

Publication number
CN117254801A
CN117254801A CN202311269793.2A CN202311269793A CN117254801A CN 117254801 A CN117254801 A CN 117254801A CN 202311269793 A CN202311269793 A CN 202311269793A CN 117254801 A CN117254801 A CN 117254801A
Authority
CN
China
Prior art keywords
phase
node
locked loop
charge pump
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311269793.2A
Other languages
Chinese (zh)
Inventor
相俊辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xinyaohui Technology Co ltd
Original Assignee
Xinyaohui Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xinyaohui Technology Co ltd filed Critical Xinyaohui Technology Co ltd
Priority to CN202311269793.2A priority Critical patent/CN117254801A/en
Publication of CN117254801A publication Critical patent/CN117254801A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C

Abstract

The technical scheme provides a phase-locked loop circuit, which comprises a phase frequency detector, a phase frequency detector and a phase feedback controller, wherein the phase frequency detector is used for receiving an input frequency signal and a feedback frequency signal and generating a control signal based on phase comparison of the input frequency signal and the feedback frequency signal; the first charge pump and the second charge pump are respectively connected with the phase frequency detector and are used for receiving the control signal and adjusting the phase of the feedback frequency signal based on the control signal; a filter circuit; a first capacitor and an operational amplifier; a first MOS tube; a second MOS tube; the current control oscillator is used for receiving the output current of the first MOS tube and outputting a frequency signal; the feedback circuit is used for receiving the frequency signal output by the current control oscillator and outputting the feedback frequency signal; and the mode switching switch is arranged between the second node and the reference voltage node. The phase-locked loop circuit of the technical scheme has better performance.

Description

Phase-locked loop circuit
Technical Field
The present application relates to the field of electronics, and in particular, to a phase locked loop circuit.
Background
With the continuous increase of data transmission rate, the serial communication technology applied to remote data transmission, such as Serializer and Deserializer (Serdes), is expanding the application field, and has the body and the shadow of Serdes from wide area networks using optical communication to computer board level interfaces using electric communication. The SerDes is mainly divided into a transmitting end (TX) and a receiving end (RX), and the TX is divided into a plurality of lines, so that in order to realize that each line can work at different frequencies, an independent phase-locked loop (PLL, phase Locked Loop) needs to be placed in each line, which puts higher requirements on the area power consumption of the PLL.
However, the current PLL circuit has performance problems such as narrow output frequency range, slow response, and large noise.
Disclosure of Invention
The technical problem to be solved by the application is to improve the performance of the phase-locked loop circuit.
The present application provides a phase-locked loop circuit, which includes: a phase frequency detector for receiving an input frequency signal and a feedback frequency signal and generating a control signal based on a phase comparison of the input frequency signal and the feedback frequency signal; the first charge pump and the second charge pump are respectively connected with the phase frequency detector and are used for receiving the control signal and adjusting the phase of the feedback frequency signal based on the control signal, wherein the output ends of the first charge pump and the second charge pump are respectively connected to a first node and a second node; a filter circuit connected to the second node for converting an output current of the second charge pump into a voltage signal; a first capacitor and an operational amplifier, the first capacitor disposed between the first node and a first potential; the first input end of the operational amplifier is connected with the output node of the filter circuit, the second input end of the operational amplifier is connected with the reference voltage node, and the output end of the operational amplifier is connected with the first node; the source electrode of the first MOS tube is connected with the first potential, the grid electrode of the first MOS tube is connected with the first node, and the drain electrode of the first MOS tube is used for outputting current; the grid electrode of the second MOS tube is connected with the second node, the drain electrode of the second MOS tube is connected with the drain electrode of the first MOS tube, and the source electrode of the second MOS tube is connected with a second potential; the input end of the current control oscillator is connected with the drain electrode of the first MOS tube and is used for receiving the output current of the first MOS tube and outputting a frequency signal; the feedback circuit is used for receiving the frequency signal output by the current control oscillator and outputting the feedback frequency signal; and the mode switching switch is arranged between the second node and the reference voltage node.
In some embodiments of the present application, the control unit is further configured to output a mode switching signal, and the mode switching signal is configured to control the operating states of the first charge pump and the mode switching switch.
In some embodiments of the present application, the mode switching signal controls the first charge pump to be deactivated when the mode switching switch is turned off.
In some embodiments of the present application, the filter circuit includes: a second capacitor disposed between the second node and the second potential; the two ends of the resistor are respectively connected with the second node and the output node of the filter circuit; and a third capacitor provided between the output node of the filter circuit and the second potential.
In some embodiments of the present application, the first charge pump and the second charge pump respectively include a first current source, a first switch, a second switch and a second current source connected in series, the first current source and the second current source are further respectively connected with a first potential and a second potential, and output ends of the first charge pump and the second charge pump are respectively disposed between the corresponding first switch and the second switch, wherein the control signal is used for controlling the on and off of the first switch and the second switch.
In some embodiments of the present application, the control signals include an up control signal for controlling the first switch and a down control signal for controlling the second switch.
In some embodiments of the present application, the transconductance of the first MOS transistor is greater than the transconductance of the second MOS transistor.
In some embodiments of the present application, the phase-locked loop circuit further includes a third MOS transistor, a drain electrode of the third MOS transistor is connected to a bias current source, a gate electrode of the third MOS transistor is connected to the mode switch, and a source electrode of the third MOS transistor is connected to the second potential, wherein the bias current source is further connected to the second input end of the operational amplifier.
In some embodiments of the present application, the feedback circuit includes a frequency divider that connects an output of the current controlled oscillator and an input of the phase frequency detector.
In some embodiments of the present application, the first potential is an operating potential and the second potential is a ground potential.
According to the phase-locked loop circuit, the working states of the first charge pump and the mode change-over switch can be controlled to be switched between the second type mode and the third type mode, when the tracking function is realized in the second type mode, the resistor, the third capacitor and the operational amplifier do not work, and the integrating circuit only performs once integration, so that the response speed is high, and meanwhile, the wide output frequency range can be ensured by improving the gain factor of the integrating circuit.
When the phase-locked loop circuit is in three modes, the first charge pump stops working, the resistor, the third capacitor and the operational amplifier enter the loop, and the integrated circuit and the proportional circuit have independent gain factors, so that the performance of the phase-locked loop circuit can be ensured by reducing the gain factors of the proportional circuit and improving the current and the resistor of the proportional circuit.
When the phase-locked loop circuit is switched from the second mode to the third mode, the direct current voltages at the key nodes are equal, and the phase errors of the input frequency signal and the feedback frequency signal are very small, so that the phase-locked loop circuit can be switched to the third mode rapidly without being locked again.
Drawings
The following figures describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals refer to like structure throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of the present application, other embodiments may equally well accomplish the intent of the invention in this application. It should be understood that the drawings are not to scale. Wherein:
FIG. 1 is a schematic diagram of a phase locked loop circuit;
FIG. 2 is a schematic diagram of another phase locked loop circuit;
fig. 3 is a schematic diagram of a phase-locked loop circuit according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a first charge pump and a second charge pump according to an embodiment of the present application;
fig. 5 is a schematic diagram of a phase-locked loop circuit according to an embodiment of the present application in a second mode;
fig. 6 is a schematic structural diagram of a pll circuit according to an embodiment of the present application in three types of modes.
Detailed Description
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the description of the embodiments will be briefly described below. It is apparent that the drawings in the following description are only some examples or embodiments of the present application, and it is obvious to those skilled in the art that the present application may be applied to other similar situations according to the drawings without inventive effort. Unless otherwise apparent from the context of the language or otherwise specified, the same reference numerals or the same reference numerals in the figures denote the same elements throughout the specification.
The terminology used in the present application is for the purpose of describing particular example embodiments only and is not intended to be limiting. For example, the terms first, second, third and the like as used herein may be used herein to describe various elements unless otherwise indicated by the context, but these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. The terms "comprises," "comprising," "includes," and/or "including," when used in this specification, are taken to specify the presence of stated integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. When different elements are described in the specification as being associated with each other, the relationship may be direct or indirect. For example, "a and B connected" may be a direct connection between a and B, or an indirect connection between a and B via other elements.
These and other features, as well as the operation and function of the related elements of structure, as well as the combination of parts and economies of manufacture, disclosed herein may be significantly improved upon in view of the following description. All of which form a part of the disclosure of the present specification, refer to the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only and are not intended as a definition of the limits of the disclosure.
Fig. 1 shows a phase-locked loop circuit in which a capacitor C int Capacitance C slow Resistance R slow Transconductance is g mv2i The MOS tube of (2) is used as an element on an integrating path, and the resistor R prop Transconductance is g mint The MOS transistor of (C) is used as a component on the proportional path. Due to the capacitance C slow And resistance R slow The existence of an ultra-low pole exists on the integral circuit, thus ensuring that the proportional circuit is not affected, and g mv2i G is g mint A high output frequency range can be ensured. The gain factor (Kvco) on the proportional path is smaller, and the Deterministic Jitter (DJ) of the phase-locked loop can be further reduced while the in-band high Random Jitter (RJ) performance is realized. However, due to the resistance R of the integrating branch slow The resistance of (c) is large, resulting in a degradation of the output noise, and the response of the overall phase locked loop is also slowed down due to the presence of the ultra-low pole.
FIG. 2 shows another phase-locked loop circuit, based on FIG. 1, with a larger resistance R slow Alternate to a span g mslow Smaller operational amplifierThe amplifier can thus solve the negative effects of the ultra-low pole in fig. 1. The loop gain of the phase-locked loop can be replaced by an integrating circuit at extremely low frequency, the overall falling speed of-40 dBc/10 times of frequency is achieved, meanwhile, the output resistance of the operational amplifier is very large, and can be approximated to infinity, which means that the third pole is approximated to be 0 frequency, and the integration is equivalent to the integration again. And the noise caused by the operational amplifier affects the resistance R slow Smaller in terms of size. But this also results in a slower overall response since in response one integration at the loop filter is followed by another integration at the third pole.
Based on this, the embodiment of the application provides a phase-locked loop circuit, which can enable the phase-locked loop circuit to switch between a second-class mode and a third-class mode, when the phase-locked loop circuit is in the second-class mode, the phase-locked loop circuit can realize a tracking function, and the integrating circuit only performs once integration at the moment, so that the response speed is higher, and when Kvco of the integrating circuit is larger, a wide output frequency range can be ensured; when the phase-locked loop circuit is in three types of modes, the locking function can be realized, at the moment, the operational amplifier enters the loop, compared with the RC oscillating circuit, the operational amplifier can reduce the noise influence, and meanwhile, the proportional loop can be provided with smaller Kvco, so that the current and the resistance of the proportional loop are improved, and the performance of the phase-locked loop circuit is ensured.
Referring to fig. 3, the phase-locked loop circuit of the embodiment of the present application includes a phase frequency detector PFD, a first charge pump CPINT, a second charge pump CP, a filter circuit, a first capacitor C1, an operational amplifier, a first MOS transistor M1, a second MOS transistor M2, a current-controlled oscillator (hereinafter referred to as CCO, current Controlled Oscillator), a feedback circuit, and a mode switch S T . The first capacitor C1 and the first MOS transistor M1 are used as elements on an integrating path, and the resistor R and the second MOS transistor M2 are used as elements on a proportional path.
The phase frequency detector PFD is arranged to compare the phases of the input frequency signal refclk and the feedback frequency signal div and to generate a control signal based on the phase comparison of the input frequency signal refclk and the feedback frequency signal div. As an example, the control signals of the embodiment of the present application include an up control signal up that is high (replaced with 1 below) and a down control signal dn that is low (replaced with 0 below) when the input frequency signal refclk leads the feedback frequency signal div; when the input frequency signal refclk lags the feedback frequency signal div, the up control signal up is 0 and the down control signal dn is 1. When the input frequency signal refclk and the feedback frequency signal div are in phase, the up control signal up and the down control signal dn are both 0.
The first charge pump CPINT and the second charge pump CP are respectively connected to the phase frequency detector PFD, and are configured to receive the control signal and adjust the phase of the feedback frequency signal div based on the control signal. The output terminals of the first charge pump CPINT and the second charge pump CP are connected to a first node a and a second node b, respectively. In some embodiments, the control signal adjusts the phase of the feedback frequency signal div by controlling the first and second charge pumps CPINT and CP input or output currents.
Referring to fig. 4, in some embodiments, the first and second charge pumps CPINT and CP may each include a first current source I connected in series s1 A first switch S1, a second switch S2 and a second current source I s2 The first current source I s1 Also connected to the first potential, the second current source I s2 The second potential is also connected, and a corresponding output terminal iout is arranged between the first switch S1 and the second switch S2. Wherein the first current source I s1 And the second current source I s2 For providing an operating current of said first charge pump CPINT and said second charge pump CP. The on and off of the first switch S1 and the second switch S2 are controlled by the control signal. In the embodiment of the present application, the first switch S1 is controlled by the up control signal up, and the second switch S2 is controlled by the down control signal dn. As an example, when the input frequency signal refclk leads the feedback frequency signal div, the up control signal up is 1, the up directionThe lower control signal dn is 0, the first switch S1 is turned on, the second switch S2 is turned off, and the first charge pump CPINT and the second charge pump CP output currents; when the input frequency signal refclk lags the feedback frequency signal div, the up control signal up is 0, the down control signal dn is 1, at this time, the first switch S1 is turned off, the second switch S2 is turned on, and the first charge pump CPINT and the second charge pump CP input currents.
In this embodiment of the present application, the working state of the first charge pump CPINT affects the working mode of the phase-locked loop circuit, and when the first charge pump CPINT works normally, the phase-locked loop circuit is in the second mode; when the first charge pump CPINT stops working, the phase-locked loop circuit is in three types of modes. Of course, the working mode of the phase-locked loop circuit is also the same as the mode switch S T Related content is switched on and off in the following mode T The description is given here. The operation state of the first charge pump CPINT may be controlled by a mode switching signal typeii, which may be output by a control section. The control section may be implemented by a conventional digital circuit.
The filter circuit is connected to the second node b and is configured to convert an output current of the second charge pump CP into a voltage signal. The filter circuit may include a second capacitor C2, a resistor R, and a third capacitor C3, where the second capacitor C2 is disposed between the second node b and a second potential, and two ends of the resistor R are respectively connected to the second node b and an output node C of the filter circuit; the third capacitor C3 is arranged between the output node C of the filter circuit and the second potential. The second potential is lower than the first potential, for example ground potential.
The first capacitance C1 is provided between the first node a and a first potential. The first potential may be an operating potential VDD. The first input end of the operational amplifier is connected with the output node c of the filter circuit, the second input end of the operational amplifier is connected with the reference voltage node d, and the output end of the operational amplifier is connected with the first node a. In some embodiments, the reference voltage nodeThe point d can generate a reference voltage through a third MOS tube M3 and a bias current source ibias, wherein the drain electrode of the third MOS tube M3 is connected with the bias current source ibias, and the grid electrode is connected with the mode switching switch S T The source is connected to the second potential, wherein the bias current source ibias is also connected to the second input of the operational amplifier. In this embodiment, the first capacitor C1 and the operational amplifier may be regarded as one low frequency pole.
The source electrode of the first MOS tube M1 is connected with the first potential, the grid electrode is connected with the first node a, and the drain end is used for outputting current. In this embodiment of the present application, a MOS tube with a larger transconductance may be used as the first MOS tube M1, so that the integrating circuit has a larger Kvco, and further, a high output frequency range of the phase-locked loop is ensured. The grid electrode of the second MOS tube M2 is connected with the second node b, the drain electrode of the second MOS tube M2 is connected with the drain electrode of the first MOS tube M1, the source electrode of the second MOS tube M2 is connected with the second potential, and the second MOS tube M2 can extract part of current output by the first MOS tube M1 so as to adjust the current input into the CCO. In this embodiment of the present application, an MOS transistor with a smaller transconductance is used as the second MOS transistor M2, so as to provide a smaller Kvco on the proportional path, so that the performance of the phase-locked loop circuit can be ensured by improving the current and the resistance of the proportional path. In this embodiment of the present application, the transconductance of the second MOS transistor M2 should be smaller than the transconductance of the first MOS transistor M1, and the specific transconductance of the first MOS transistor M1 and the specific transconductance of the second MOS transistor M2 depend on the actual situation, which is not limited herein. As an example, the first MOS transistor M1 is a PMOS transistor, and the second MOS transistor M2 is an NMOS transistor.
The input end of the CCO is connected with the drain electrode of the first MOS transistor M1, and is configured to receive the output current of the first MOS transistor M1 and output a frequency signal. The feedback circuit is used for receiving the frequency signal output by the CCO and outputting the feedback frequency signal div. In this embodiment of the present application, the feedback circuit includes a frequency divider Fbdiv/N, where the frequency divider Fbdiv/N is connected to the output end of the CCO and the input end of the phase frequency detector PDF. The frequency divider Fbdiv/N receives the frequency division signal Fbdiv, performs frequency division processing on the frequency output by the CCO, and outputs the feedback frequency signal div.
The mode change-over switch S T Is arranged between the second node b and the reference voltage node d. In the embodiment of the present application, the first charge pump CPINT and the mode switch S may be controlled T The phase-locked loop circuit is switched between different modes. Wherein the first charge pump CPINT is controlled to work normally and the mode switch S is controlled to switch T The phase-locked loop circuit is conducted and can be in a second-class mode; by controlling the first charge pump CPINT to stop working and making the mode switch S T And the phase-locked loop circuit can be in three types of modes after being turned off. In the embodiment of the present application, the first charge pump CPINT and the mode switch S are simultaneously controlled by a mode switching signal typeii T Is not in the operating state. In some embodiments, the mode switch S T Also controlled by a reset signal reset, while the operating states of the first charge pump CPINT and the second charge pump CP are controlled by the inverse of the reset signal reset.
The working principle of the phase-locked loop circuit in the embodiment of the present application is further described below.
Referring to fig. 5, when the input frequency signal refclk and the feedback frequency signal div are out of phase, the first charge pump CPINT is controlled to be in a normal operation state by the mode switching signal typeii while the mode switching switch S is controlled T And the resistor R, the third capacitor C3 and the operational amplifier are conducted, and the phase-locked loop circuit is set in the second-class mode to realize the tracking function of the phase-locked loop circuit. In the second mode, the current output by the first charge pump CPINT may be small, so that the overall area of the pll circuit may be adjusted by controlling the area of the first charge pump CPINT. Meanwhile, because the current output by the first charge pump CPINT directly charges and discharges the first capacitor C1, and only one integration exists, compared with the phase-locked loop circuit shown in fig. 1 and 2, the response speed can be greatly improved, and meanwhile, because the Kvco of the integration branch is larger, the width can be ensuredIs provided for the output frequency range of (a).
Referring to fig. 6, the first charge pump CPINT is controlled to be in a stopped state by a mode switching signal typeii, while the mode switching switch S is controlled T And the phase-locked loop circuit is set in three types of modes when the resistor R, the third capacitor C3 and the operational amplifier start to work. In this mode, the first capacitance C1 exists as a third pole. When the phase-locked loop circuit is switched from the second mode to the third mode, the direct-current voltages of the second mode and the third mode at the key nodes are equal, and the phase errors of the input frequency signal refclk and the feedback frequency signal div are particularly small, which means that the phase-locked loop circuit can be quickly switched to the third mode without being locked again. In addition, in the three modes, the first MOS transistor M1 provides the integrated circuit Kvco, and the second MOS transistor M2 provides the proportional circuit Kvco, so that the integrated circuit Kvco and the proportional circuit Kvco are separated, and the loop bandwidth w is related to the proportional circuit Kvco, which has the following formula:
wherein I is CP Kvco is a gain factor of a proportional path, R is a resistor, N is a frequency division ratio, C2 is a second capacitor, and C3 is a third capacitor.
When Kvco of the proportional path is smaller, according to the formula of the loop bandwidth w, the performance of the phase-locked loop circuit can be improved by increasing the charge-discharge current and the resistor R of the second charge pump CP.
Those skilled in the art will appreciate after reading this application that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the present application.

Claims (10)

1. A phase locked loop circuit comprising:
a phase frequency detector for receiving an input frequency signal and a feedback frequency signal and generating a control signal based on a phase comparison of the input frequency signal and the feedback frequency signal;
the first charge pump and the second charge pump are respectively connected with the phase frequency detector and are used for receiving the control signal and adjusting the phase of the feedback frequency signal based on the control signal, wherein the output ends of the first charge pump and the second charge pump are respectively connected to a first node and a second node;
a filter circuit connected to the second node for converting an output current of the second charge pump into a voltage signal;
a first capacitor and an operational amplifier, the first capacitor disposed between the first node and a first potential; the first input end of the operational amplifier is connected with the output node of the filter circuit, the second input end of the operational amplifier is connected with the reference voltage node, and the output end of the operational amplifier is connected with the first node;
the source electrode of the first MOS tube is connected with the first potential, the grid electrode of the first MOS tube is connected with the first node, and the drain electrode of the first MOS tube is used for outputting current;
the grid electrode of the second MOS tube is connected with the second node, the drain electrode of the second MOS tube is connected with the drain electrode of the first MOS tube, and the source electrode of the second MOS tube is connected with a second potential;
the input end of the current control oscillator is connected with the drain electrode of the first MOS tube and is used for receiving the output current of the first MOS tube and outputting a frequency signal;
the feedback circuit is used for receiving the frequency signal output by the current control oscillator and outputting the feedback frequency signal;
and the mode switching switch is arranged between the second node and the reference voltage node.
2. The phase-locked loop circuit of claim 1, further comprising a control section for outputting a mode switching signal, and the mode switching signal is for controlling an operation state of the first charge pump and the mode switching switch.
3. The phase-locked loop circuit of claim 2, wherein the mode switch signal controls the first charge pump to be deactivated when the mode switch is turned off.
4. The phase-locked loop circuit of claim 1, wherein the filter circuit comprises:
a second capacitor disposed between the second node and the second potential;
the two ends of the resistor are respectively connected with the second node and the output node of the filter circuit;
and a third capacitor provided between the output node of the filter circuit and the second potential.
5. The phase-locked loop circuit of claim 1, wherein the first charge pump and the second charge pump each comprise a first current source, a first switch, a second switch, and a second current source connected in series, the first current source and the second current source further respectively connect a first potential and a second potential, and output terminals of the first charge pump and the second charge pump are respectively disposed between the corresponding first switch and the second switch, wherein the control signal is configured to control on and off of the first switch and the second switch.
6. The phase-locked loop circuit of claim 5, wherein the control signals comprise an up control signal for controlling the first switch and a down control signal for controlling the second switch.
7. The phase-locked loop circuit of claim 1, wherein the transconductance of the first MOS transistor is greater than the transconductance of the second MOS transistor.
8. The phase-locked loop circuit of claim 1, further comprising a third MOS transistor having a drain connected to a bias current source, a gate connected to the mode switch, and a source connected to the second potential, wherein the bias current source is further connected to the second input of the operational amplifier.
9. The phase locked loop circuit of claim 1, wherein the feedback circuit comprises a frequency divider coupled to an output of the current controlled oscillator and an input of the phase frequency detector.
10. The phase-locked loop circuit of claim 1, wherein the first potential is an operating potential and the second potential is a ground potential.
CN202311269793.2A 2023-09-27 2023-09-27 Phase-locked loop circuit Pending CN117254801A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311269793.2A CN117254801A (en) 2023-09-27 2023-09-27 Phase-locked loop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311269793.2A CN117254801A (en) 2023-09-27 2023-09-27 Phase-locked loop circuit

Publications (1)

Publication Number Publication Date
CN117254801A true CN117254801A (en) 2023-12-19

Family

ID=89136560

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311269793.2A Pending CN117254801A (en) 2023-09-27 2023-09-27 Phase-locked loop circuit

Country Status (1)

Country Link
CN (1) CN117254801A (en)

Similar Documents

Publication Publication Date Title
KR100358118B1 (en) Phase locked loop having high-speed locking
US7330058B2 (en) Clock and data recovery circuit and method thereof
US6580329B2 (en) PLL bandwidth switching
US6771114B2 (en) Charge pump current compensating circuit
US7602253B2 (en) Adaptive bandwidth phase locked loop with feedforward divider
US6873214B2 (en) Use of configurable capacitors to tune a self biased phase locked loop
US6693496B1 (en) Method and system for low power, low jitter, wide range, self-adaptive multi-frequency phase locked loop
US7145400B2 (en) Phase locked loop with a switch capacitor resistor in the loop filter
US20080191783A1 (en) Symmetric charge pump replica bias detector
US7386085B2 (en) Method and apparatus for high speed signal recovery
CN110572150A (en) Clock generation circuit and clock generation method
US7498886B2 (en) Clock distribution system and method thereof
WO2000060740A1 (en) Differential charge pump with common mode feedback
US7511580B2 (en) Charge pump circuit with dynamic current biasing for phase locked loop
US20100207673A1 (en) Asymmetric charge pump and phase locked loops having the same
WO2023124558A1 (en) Phase-locked loop circuit, control method, charge pump, and chip
US8248123B2 (en) Loop filter
US9391626B2 (en) Capacitive load PLL with calibration loop
CN117254801A (en) Phase-locked loop circuit
CN111211776B (en) Phase-locked loop circuit
US20090289674A1 (en) Phase-locked loop
US5929678A (en) Frequency synthesis circuit having a charge pump
US6993106B1 (en) Fast acquisition phase locked loop using a current DAC
US7880550B2 (en) Voltage translation using feedback to adjust output voltage range
US7388440B1 (en) Circuit and method to speed up PLL lock-time and prohibit frequency runaway

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination