CN107248862A - A kind of fractional frequency division reduction frequency jitter circuit and method - Google Patents
A kind of fractional frequency division reduction frequency jitter circuit and method Download PDFInfo
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- CN107248862A CN107248862A CN201710433104.5A CN201710433104A CN107248862A CN 107248862 A CN107248862 A CN 107248862A CN 201710433104 A CN201710433104 A CN 201710433104A CN 107248862 A CN107248862 A CN 107248862A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
Abstract
The invention discloses a kind of fractional frequency division reduction frequency jitter circuit and method, the circuit includes PFD, CP, LPF, VCO, three rank Σ Δs, programmable frequency divider, DIV, PFD, CP, LPF, VCO are sequentially connected, programmable frequency divider is connected between VCO and PFD, three rank Σ Δs are connected to programmable frequency divider, and VCO and programmable frequency divider are connected to DIV；Fvco output frequency is after three rank Σ Δs, programmable frequency divider frequency dividing, it is input to PFD, it is compared with the PFD reference clocks inputted, the frequency and any difference of phase of PFD two input clocks, corresponding voltage signal will be converted to by CP, then after LPF filters high-frequency noise, input VCO regulations Fvco output frequency and phase, until PFD two input clocks frequency and phase close to untill identical, at this moment Fvco can export desired frequency and phase.
Description
Technical field
The invention belongs to technical field of integrated circuits, more particularly to a kind of phaselocked loop fractional frequency division algorithm, to reduce output
Frequency jitter.
Background technology
Ultrasonic atomization technique carries out energy amplification using the oscillator signal from main circuit board by large power triode, passes
Ultrasonic chip is passed, electric energy is converted into ultrasonic energy by ultrasonic quarter wave plate 14, and ultrasonic energy at normal temperatures can be water-soluble pesticide
Thing is atomized into 1um to 5um small droplet, using water as medium, using ultrasound orientation pressure by water-soluble decoction atomisation, borrows
Inner fan wind-force is helped to come out.Ultrasonic ultrasonic delay line memory using electronics high frequency oscillation (frequency of oscillation be 1.7MHz or 2.4MHz,
More than the audibility range of people, the electronic is absolutely not injured to human body and animal), will by the high-frequency resonant of ceramic atomizing piece
Aqueous water minor structure is broken up and produces the elegant water smoke of nature, is not required to heat or is added any chemical reagent.With heating atomization
Mode compares, energy saving 90%.Substantial amounts of anion will be discharged in atomization process in addition, itself and the cigarette floated in air
Mist, dust etc. produce electrostatic reaction, precipitate it, while the nuisances such as formaldehyde, carbon monoxide, bacterium can also be removed effectively
Matter, is purified air, reduces the generation of disease.
But atomizing piece has the individual feature to be exactly：Optimal atomizing effect could be only produced in resonance point, driving frequency is slightly
Micro- off-resonance point, atomization quantity just drastically declines.
Such as patent application 201410450118.4 discloses atomizer and its applicable control method, and atomizer is used for liquid
Body is atomized, comprising：Atomization circuit, with piezo-activator, for being atomized the liquid into by piezo-activator with operating；Power supply electricity
Road, is electrically connected with atomization circuit, for selectively power to atomization circuit, to drive atomization circuit to operate；Sample circuit, with mist
Change circuit electrical connection, piezo-activator is produced with harmonic signal when being operated under working frequency for sampling；Filter circuit；With adopting
Sample circuit is electrically connected, for capturing specific frequency of the sampling circuit samples in harmonic signal；Circuit is controlled, with power circuit
And filter circuit electrical connection, for by sampling circuit samples to specific frequency be compared with setpoint frequency, with foundation compare
As a result judge whether liquid exhausts, and then controlling power circuit is stopped power supply to atomization circuit when liquid depletion.The patent Shen
Please the frequency of atomizer be that the specific frequency in harmonic signal is captured by using circuit, the frequency that this method is used is simultaneously unstable
Fixed, easily by various interference, nebulization efficiency is not fine.
The content of the invention
Based on this, therefore the primary mesh of the present invention be to provide a kind of fractional frequency division reduction frequency jitter circuit and method,
This method can efficiently control atomization rate-adaptive pacemaker, solve the problem of output frequency shake is more than stepping, and resonance point is stable,
Nebulization efficiency is high, reliable.
It is to provide a kind of fractional frequency division reduction frequency jitter circuit and method, this method mist another mesh of the present invention
Changing rate-adaptive pacemaker can control in the range of 1.5MHz-3.6MHz, and the frequency that 5KHz can be less than with stepping accuracy changes, by algorithm
The resonance point that searches step by step is controlled, and realizes simplicity, it is with low cost.
To achieve the above object, the technical scheme is that：
A kind of fractional frequency division reduces frequency jitter circuit, it is characterised in that the circuit includes PFD (phase discriminator), CP (electricity
Lotus pump), LPF (loop filter), VCO (voltage controlled oscillator), third order sigma-delta, programmable frequency divider (Programbale
Divider), DIV (frequency divider DIVIDER), PFD, CP, LPF, VCO are sequentially connected, programmable frequency divider be connected to VCO and PFD it
Between, third order sigma-delta is connected to programmable frequency divider, and VCO and programmable frequency divider are connected to DIV；Fvco output frequency passes through three
After rank sigma-delta, programmable frequency divider frequency dividing, PFD is input to, is compared with the PFD reference clocks inputted, two of PFD are defeated
Enter the frequency of clock and any difference of phase, corresponding voltage signal can be all converted to by CP, then high frequency is filtered by LPF
After noise, input VCO regulations Fvco output frequency and phase, until the frequency and phase of PFD two input clocks are approached
Untill identical, at this moment Fvco can export desired frequency and phase.
Further, the PFD (phase discriminator), CP (charge pump), LPF (loop filter), VCO (voltage controlled oscillator) are in mould
Intend part to realize, third order sigma-delta, programmable frequency divider (Programbale divider), DIV are realized in numerical portion.
Further, third order sigma-delta is made up of three groups of X+Y, DEF, and three groups of groups X+Y, DEF are connected in parallel, and being connected to can
Programming frequency division device.
Further, described two groups are connected to DEF between X+Y, DEF.
Further, the programmable frequency divider is FVCO diviver.
The third order sigma-delta, the effect of programmable frequency divider are the divide ratios that programmable frequency divider is controlled by algorithm
In DIV_INT, DIV_INT-1, DIV_INT-2, DIV_INT-3, DIV_INT-4, DIV_INT+1, DIV_INT+2, DIV_INT
Change between+3 this 8 number according to certain rule.
The fractional frequency division reduction frequency jitter method that the present invention is realized, it is characterised in that this method carries out output frequency and matched somebody with somebody
Put, make frequency to change between 1.5MHz-4.5MHz, Fvco output frequency is by third order sigma-delta, programmable frequency divider point
After frequency, PFD is input to, is compared with the PFD reference clocks inputted, meanwhile, DIV_INT inputs to programmable frequency divider；PFD
Two input clocks frequency and any difference of phase, corresponding voltage signal can be all converted to by CP, then by LPF
Filter after high-frequency noise, input VCO regulation Fvco output frequency and phase, until PFD two input clocks frequency and
Phase is close to untill identical, and at this moment Fvco can export desired frequency and phase.
Further, when 1.5MHz-4.5MHz to be obtained output frequency, DIV_INT is from 12-36 for configuration, obtains Fvco
12MHz-36MHz is exported, then 8 frequency dividings or 16 frequency dividings are carried out to Fvco, 1.5MHz-4.5MHz output frequency is obtained.
Third order sigma-delta, the effect of programmable frequency divider are to control the divide ratio of programmable frequency divider to exist by algorithm
DIV_INT、DIV_INT-1、DIV_INT-2、DIV_INT-3、DIV_INT-4、DIV_INT+1、DIV_INT+2、DIV_INT+3
Change (the integral frequency divisioil system that DIV_INT is configuration) according to certain rule between this 8 number so that last Fvco output frequency
Rate such as following formula relation：
Found out by formula, DIV_FRAC often increases and reduced a value, Fvco change 244Hz frequencies.
Further, the fractional frequency division reduces frequency jitter method, and its concrete implementation step is：
101. configuration register DIV_INT [5:0], DIV_FRAC [11:0]；
102. judge whether DIV_INT is more than 18；
If 103. DIV_INT is less than 18, DIV_INT=DIV_INT+12；
104. fractional frequency division ratio is obtained by 3 rank sigma-delta computings summation, and DIV_INT is combined, and draws Fvco points of voltage controlled frequency
The phase discriminator incoming frequency PFD_CLK of frequency, then exports Fvco frequencies by VCO；
105. and because if DIV_INT is less than 18, it is necessary to obtain divide ratio plldiv=4,16 frequency dividings；
106. realizing that the 105th step 16 is divided by frequency dividing circuit, output frequency pwmout=1.5MHz~2.25MHz is obtained；
If 107. DIV_INT is more than 18, DIV_INT=DIV_INT-1；
108. fractional frequency division ratio is obtained by 3 rank sigma-delta computings summation, and DIV_INT is combined, and draws Fvco points of voltage controlled frequency
The phase discriminator incoming frequency PFD_CLK of frequency, then exports Fvco frequencies by VCO；
109. and because if DIV_INT is equal to greatly 18, it is necessary to obtain divide ratio plldiv=3,8 frequency dividings；
110. by frequency dividing circuit realize the 109th step 8 frequency dividing, obtain output frequency pwmout=2.2.5MHz~
4.5MHz。
Thus achieve by different segment factors to show that output frequency pwmout is steady to segmentation voltage controlled frequency Fvco frequency dividings
It is qualitative.
Fractional frequency division reduction frequency jitter circuit and method that the present invention is realized, are realized small by numeral and simulation combination
The function of number frequency dividing, can configure output frequency, and control frequency between 1.5MHz-4.5MHz to change, and frequency change is minimum
(i.e. stepping accuracy) can be accomplished to be less than 5KHz, and the shake of atomization chip output frequency is controlled within a stepping, so
Just can effectively it be made a distinction between two neighboring frequency.So as to solve the problem of output frequency shake is more than stepping, and resonance
Point is stable, and nebulization efficiency is high, reliable.
Brief description of the drawings
Fig. 1 is the circuit diagram that the present invention is implemented.
Fig. 2 is the circuit diagram that the present invention implements third order sigma-delta and programmable frequency divider.
Fig. 3 is the flow chart that the present invention is implemented.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
It is that the present invention realizes that fractional frequency division reduces the circuit diagram of frequency jitter circuit, shown in figure, the electricity shown in Fig. 1
Road includes PFD (phase discriminator), CP (charge pump), LPF (loop filter), VCO (voltage controlled oscillator), third order sigma-delta, can compiled
Journey frequency divider (Programbale divider), DIV (frequency divider DIVIDER), PFD, CP, LPF, VCO are sequentially connected, can compiled
Journey frequency divider is connected between VCO and PFD, and third order sigma-delta is connected to programmable frequency divider, and VCO and programmable frequency divider are connected to
DIV；Fvco output frequency is input to PFD, the reference inputted with PFD after third order sigma-delta, programmable frequency divider frequency dividing
Clock is compared, the frequency and any difference of phase of PFD two input clocks, and corresponding electricity can be all converted to by CP
Signal is pressed, then after LPF filters high-frequency noise, input VCO regulations Fvco output frequency and phase, until two of PFD
The frequency and phase of input clock are close to untill identical, and at this moment Fvco can export desired frequency and phase.
PFD (phase discriminator), CP (charge pump), LPF (loop filter), VCO (voltage controlled oscillator) analog portion realize,
Third order sigma-delta, programmable frequency divider (Programbale divider), DIV are realized in numerical portion.Main realization of the invention
It is numerical portion circuit realiration, analog circuit is made up of prior art, as long as producing output frequency according to interlock circuit
Fvco.
With reference to shown in Fig. 2, third order sigma-delta is made up of three groups of X+Y, DEF, and three groups of groups X+Y, DEF are connected in parallel, and are connected to
Programmable frequency divider.Two groups are connected to DEF between X+Y, DEF.
Programmable frequency divider is realized by FVCO diviver.
Third order sigma-delta, the effect of programmable frequency divider are to control the divide ratio of programmable frequency divider to exist by algorithm
DIV_INT、DIV_INT-1、DIV_INT-2、DIV_INT-3、DIV_INT-4、DIV_INT+1、DIV_INT+2、DIV_INT+3
Change between this 8 number according to certain rule.
In actual chip application scene, Fvco output frequencies are not required nothing more than can realize stepping as 244Hz.
It is required that the shake of output frequency is less than a stepping.Because if the scope of frequency jitter is more than a stepping, it will obtain in mist
Change in device application, the energy production between two close frequencies is overlapping, causes system can not be made a distinction to the two frequencies, from
And the optimum resonant frequency of atomizing piece can not be found.
And actual conditions, the output frequency for the 2.5MHz-4.5MHz that 8 frequency dividings are obtained is carried out to 18MHz-36MHz Fvco
Shake is less than a step-length；12MHz-18MHz Fvco carries out the output frequency shake for the 1.5MHz-2.5MHz that 8 frequency dividings are obtained
More than one step-length.The scope of such case frequency jitter is more than a stepping, will obtain in atomizer application, two close
Energy production between frequency is overlapping, causes system can not be made a distinction to the two frequencies, so that atomizing piece can not be found
Optimum resonant frequency.
Thus, a kind of new fractional frequency division reduction frequency jitter method is proposed in the present invention, is not increasing filter capacitor
In the case of, effectively reduction shake.This method is trembled by way of being segmented frequency dividing the output frequency that obtains 1.5MHz-4.5MHz
Dynamic scope is less than a stepping length, and system effectively recognizes that rank enters frequency, so as to find the optimum resonant frequency of atomizing piece.
Shown in reference picture 3, specifically, implementation step is：
101. configuration register DIV_INT [5:0], DIV_FRAC [11:0], required 16 DFF trigger.
102. judge whether DIV_INT is more than 18.Required 16 bit comparator.
If 103. DIV_INT is less than 18, DIV_INT=DIV_INT+12, required 16 adder.
104. fractional frequency division ratio is obtained by 3 rank sigma-delta computings summation, and DIV_INT is combined, and draws Fvco points of voltage controlled frequency
The phase discriminator incoming frequency PFD_CLK of frequency, then exports Fvco frequencies by VCO.
105. and because if DIV_INT is less than 18, it is necessary to obtain divide ratio plldiv=4,16 frequency dividings.Required 1
Selector.
106. realizing that the 105th step 16 is divided by frequency dividing circuit, output frequency pwmout=1.5MHz~2.25MHz is obtained
(because of Fvco=24MHz~36MHz, being determined by DIV_INT numerical value), required 4 frequency dividing circuits.
If 107. DIV_INT is more than 18, DIV_INT=DIV_INT-1, required 16 adder.
108. fractional frequency division ratio is obtained by 3 rank sigma-delta computings summation, and DIV_INT is combined, and draws Fvco points of voltage controlled frequency
The phase discriminator incoming frequency PFD_CLK of frequency, then exports Fvco frequencies by VCO.
109. and because if DIV_INT is equal to greatly 18, it is necessary to obtain divide ratio plldiv=3,8 frequency dividings.Multiplexing the
The selector of 104 steps.
110. realizing 8 frequency dividings of the 109th step by frequency dividing circuit, output frequency pwmout=2.2.5MHz~4.5MHz is obtained
(because Fvco=18MHz~36MHz is determined by DIV_INT numerical value), is multiplexed the 106th step frequency dividing circuit.
111. thus achieve by different segment factors to draw output frequency to segmentation voltage controlled frequency Fvco frequency dividings
Pwmout stability.
Circuit and method that the present invention is realized, the function of fractional frequency division is realized by numeral and simulation combination, makes output
Frequency can configure, and control frequency between 1.5MHz-4.5MHz to change, and frequency change minimum (i.e. stepping accuracy) can be accomplished
Less than 5KHz, the shake of atomization chip output frequency is controlled within a stepping, with regard to energy between so two neighboring frequency
Effectively made a distinction.So as to solve the problem of output frequency shake is more than stepping, and resonance point is stable, nebulization efficiency is high, can
Lean on.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
Any modifications, equivalent substitutions and improvements made within refreshing and principle etc., should be included in the scope of the protection.
Claims (10)
1. a kind of fractional frequency division reduces frequency jitter circuit, it is characterised in that the circuit includes PFD, CP, LPF, VCO, three ranks
Sigma-delta, programmable frequency divider, DIV, PFD, CP, LPF, VCO are sequentially connected, and programmable frequency divider is connected between VCO and PFD, and three
Rank sigma-delta is connected to programmable frequency divider, and VCO and programmable frequency divider are connected to DIV；Fvco output frequency by three rank Σ-
After Δ, programmable frequency divider frequency dividing, PFD is input to, is compared with the PFD reference clocks inputted, PFD two input clocks
Frequency and phase any difference, can all be converted to corresponding voltage signal by CP, then high-frequency noise is filtered by LPF
Afterwards, input VCO regulations Fvco output frequency and phase, until PFD two input clocks frequency and phase close to identical
Untill, at this moment Fvco can export desired frequency and phase.
2. fractional frequency division as claimed in claim 1 reduces frequency jitter circuit, it is characterised in that described PFD, CP, LPF, VCO
Realized in analog portion, third order sigma-delta, programmable frequency divider, DIV are realized in numerical portion.
3. fractional frequency division as claimed in claim 1 reduces frequency jitter circuit, it is characterised in that third order sigma-delta by three groups of X+Y,
DEF is constituted, and three groups of groups X+Y, DEF are connected in parallel, and are connected to programmable frequency divider.
4. fractional frequency division as claimed in claim 3 reduces frequency jitter circuit, it is characterised in that described two groups of X+Y, DEF it
Between be connected to DEF.
5. fractional frequency division as claimed in claim 4 reduces frequency jitter circuit, it is characterised in that the programmable frequency divider is
FVCO diviver。
6. fractional frequency division as claimed in claim 5 reduces frequency jitter circuit, it is characterised in that the third order sigma-delta, can compile
The effect of journey frequency divider is to control the divide ratio of programmable frequency divider in DIV_INT, DIV_INT-1, DIV_ by algorithm
According to a set pattern between this 8 number of INT-2, DIV_INT-3, DIV_INT-4, DIV_INT+1, DIV_INT+2, DIV_INT+3
Rule change.
7. a kind of fractional frequency division reduces frequency jitter method, it is characterised in that this method carries out output frequency configuration, frequency is existed
To change between 1.5MHz-4.5MHz, Fvco output frequency is input to after third order sigma-delta, programmable frequency divider frequency dividing
PFD, is compared with the PFD reference clocks inputted, meanwhile, DIV_INT inputs to programmable frequency divider；PFD two inputs
The frequency of clock and any difference of phase, corresponding voltage signal can be all converted to by CP, then filters high frequency by LPF and is made an uproar
After sound, input VCO regulations Fvco output frequency and phase, until PFD two input clocks frequency and phase close to phase
With untill, at this moment Fvco can export desired frequency and phase.
8. fractional frequency division as claimed in claim 7 reduces frequency jitter method, it is characterised in that as 1.5MHz- to be obtained
During 4.5MHz output frequency, DIV_INT is from 12-36 for configuration, obtains Fvco output 12MHz-36MHz, then carry out 8 points to Fvco
Frequency or 16 frequency dividings, obtain 1.5MHz-4.5MHz output frequency.
9. fractional frequency division as claimed in claim 8 reduces frequency jitter circuit, it is characterised in that third order sigma-delta, programmable point
The effect of frequency device be by algorithm control programmable frequency divider divide ratio DIV_INT, DIV_INT-1, DIV_INT-2,
Change between this 8 number of DIV_INT-3, DIV_INT-4, DIV_INT+1, DIV_INT+2, DIV_INT+3 according to certain rule,
So that last Fvco output frequency such as following formula relation：
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Found out by formula, DIV_FRAC often increases and reduced a value, Fvco change 244Hz frequencies.
10. fractional frequency division reduction frequency jitter circuit as claimed in claim 9, it is characterised in that the fractional frequency division reduces frequency
Dither method, its concrete implementation step is：
101. configuration register DIV_INT [5:0], DIV_FRAC [11:0]；
102. judge whether DIV_INT is more than 18；
If 103. DIV_INT is less than 18, DIV_INT=DIV_INT+12；
104. fractional frequency division ratio is obtained by 3 rank sigma-delta computings summation, and DIV_INT is combined, and draws voltage controlled frequency Fvco frequency dividings
Phase discriminator incoming frequency PFD_CLK, then exports Fvco frequencies by VCO；
105. and because if DIV_INT is less than 18, it is necessary to obtain divide ratio plldiv=4,16 frequency dividings；
106. realizing that the 105th step 16 is divided by frequency dividing circuit, output frequency pwmout=1.5MHz~2.25MHz is obtained；
If 107. DIV_INT is more than 18, DIV_INT=DIV_INT-1；
108. fractional frequency division ratio is obtained by 3 rank sigma-delta computings summation, and DIV_INT is combined, and draws voltage controlled frequency Fvco frequency dividings
Phase discriminator incoming frequency PFD_CLK, then exports Fvco frequencies by VCO；
109. and because if DIV_INT is equal to greatly 18, it is necessary to obtain divide ratio plldiv=3,8 frequency dividings；
110. realizing 8 frequency dividings of the 109th step by frequency dividing circuit, output frequency pwmout=2.2.5MHz~4.5MHz is obtained.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109150177A (en) * | 2018-06-26 | 2019-01-04 | 杭州雄迈集成电路技术有限公司 | A kind of fractional frequency division implementation method of the jittered mechanism of band |
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