CN1714510A - Variable frequency synthesizer comprising a sigma-delta Modulator - Google Patents
Variable frequency synthesizer comprising a sigma-delta Modulator Download PDFInfo
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- CN1714510A CN1714510A CN03825623.1A CN03825623A CN1714510A CN 1714510 A CN1714510 A CN 1714510A CN 03825623 A CN03825623 A CN 03825623A CN 1714510 A CN1714510 A CN 1714510A
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- accumulator
- signal
- frequency
- divider
- spill over
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
- H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3002—Conversion to or from differential modulation
- H03M7/3004—Digital delta-sigma modulation
- H03M7/3006—Compensating for, or preventing of, undesired influence of physical parameters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3002—Conversion to or from differential modulation
- H03M7/3004—Digital delta-sigma modulation
- H03M7/3015—Structural details of digital delta-sigma modulators
- H03M7/302—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution
- H03M7/3022—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type
Abstract
A variable frequency synthesizer comprising a sigma-delta modulator is provided. Such synthesizers provide an exact average frequency whereas the instantaneous frequencies are varied. The sigma-delta modulator comprises a plurality of accumulator stages being connected in cascade. At least one input value of an accumulator (51, 52, 53, 54) being part of the sigma-delta modulator has a second component, which is equal to an overflow signal (of1, of2, of3, of4) multiplied by a factor. This feedback reduces the maximum fluctuation of the instantaneous frequencies. Phase jitter generated by non-linearity of the phase detector, the charge pump and the VCO is therefore reduced.
Description
Technical field
The present invention relates generally to a kind of frequency synthesizer, more specifically, relate to a kind of frequency synthesizer of the preamble according to claim 1, according to the method for the operation divider ratio controller of the divider ratio controller of the preamble of claim 5 and a kind of preamble according to claim 6.
Background technology
It is the output signal of the definite multiple of reference frequency that frequency synthesizer produces frequency.The precision of this output signal frequency is to be determined by the precision of reference frequency and stability.Under the prior art level, frequency synthesizer is usually based on phase-locked loop (PLL) circuit.
In general, PLL comprises phase detector circuit, amplifier or charge pump, filter circuit and voltage controlled oscillator.Phase detector circuit detects the phase difference of two signals.One of these two signals are reference signal.Another signal produces in PLL.Charge pump produces the analog signal with the high current drives that is applicable to VCO control.Charge pump signal has two fixed current values usually, and these two current value sizes are identical, but opposite in sign, corresponding to provide by phase detectors and representative between two signals, have the numeral 0 and 1 of phase difference by the phase detectors comparison.Frequency to VCO is regulated, up to reference signal and the signal Synchronization that compares with reference signal.
Charge pump being provided before signal presents to VCO, in loop filter, decay usually to high-frequency noise.This filter is low pass filter and the signal that is provided by charge pump is asked average.The signal of VCO at first carries out frequency division by frequency divider, and then is fed to phase detectors.Therefore VCO has produced the frequency of the multiple that is provided by the inverse of divider ratio than reference frequency height.
In general, divider circuit only can be divided by integer value.Like this, the incremental change of output frequency can be less than reference frequency itself.Therefore, for the frequency synthesizer with very little step sizes is provided, need low-down reference frequency.But, low reference frequency is unacceptable, because they have limited frequency range and have caused the time of keeping steady (settling time) very long.
Little step sizes can make decimally, and frequency divider realizes.Disclosed such in the U.S. Patent No. of submitting on December 23rd, 1,973 3,928,813 as C.A.Kingsford-Smith, such frequency divider realizes that by change divider ratio between integer value during several frequency division cycles non-integer divides frequency.If expected frequency is 1MHz for for example 1000.1Hz and reference frequency, then the divider ratio corresponding to nine circulations can be 1000, and is 1001 corresponding to the divider ratio of a circulation.
Such PLL circuit only provides correct average frequency, and instantaneous divider ratio never is correct, and this causes having obtained phase error at the output of phase detectors.The frequency of phase error signal modulation VCO, the result has produced parasitic signal, is called phase jitter.In order to alleviate the problem relevant, can use the signal that is used to repair phase error with shake---a kind of technology that is called phase interpolation.But, very difficult generation is used to repair the signal of phase error accurately, and this Technology Need is complicated and expensive circuit.
DE 690 23 219 discloses a kind of frequency synthesizer, and wherein divider ratio is by Sigma-delta modulator circuit control.Produce effect very much, the low frequency phase noise has obtained inhibition, and has therefore suppressed parasitic signal.But, the variation of the divider ratio that obtains of result may be relatively large.For such variation, the signal that imposes on VCO no longer is the linear function of the detected phase shift of phase detectors (phase shift), so that VCO can not produce the average frequency that in fact it should produce.As a result, the average frequency of the signal that produces in the PLL circuit also may comprise a considerable amount of noises.
The EP 125790 that N.J.Wells submitted on April 11st, 1984 has introduced a kind of all well and good frequency synthesizer, wherein by being that the multiple order of the continuous row in zero the Pascal triangle (Pascal ' s triangle) changes divider ratio and makes phase noise obtain inhibition according to the expression summation.But, noise is very big too for low frequency for this frequency synthesizer, has caused aforesaid problem.
According to David Owen (IFR Americas, Inc.) application note of being shown " decimal-N synthesizer (Fractional-N Synthesizers) " can use the divider ratio controller shown in the accompanying drawing 2 to realize disclosed frequency synthesizer among the EP 125790.Described divider ratio controller is made of several accumulators AC21, AC22, AC23, the AC24 that are connected in series.The output of an accumulator is connected with the input of next accumulator.Decimal (fractionalnumber) is promptly expected the fractional part of average divide device ratio, is provided to the input of first accumulator.When the value of storing in the accumulator surpassed the given limit of capacity by each accumulator, accumulator overflowed, and produces spill over of
1, of
2, of
3And of
4These spill overs are by differentiator DIF21, DIF22, DIF23 and DIF24 differential, and addition, and to form signal delta N, this signal is added on the integer word (integer word), that is, be added on the integer part of expection average divide device ratio.
Provided the model of basic accumulator stage in the accompanying drawing 3.In this expression, z is the Laplce's variable in the discrete time territory, vi
i(z), vo
i(z) and of
i(z) be the input signal vi of accumulator stage respectively
i, accumulator stage output signal vo
iWith spill over of
iThe z conversion (below with vi
i(z) be abbreviated as vi
i, or the like).1/ (1-z
-1) be the transfer function of accumulator stage.Therefore, vi
iCan be expressed as:
vi
i＝(1-z
-1)×(vo
i+of
i)-z
-1×of
i (1)
Utilize equation (1), can be with of
iBe written as:
of
i＝-vo
i×(1-z
-1)+vi
i (2)
The output signal vo of accumulator stage
iBe the input signal vi of next accumulator stage (that is, order is the accumulator stage of i+1)
I+1Therefore, of
I+1Can be expressed as:
of
i+1＝-vo
i+1×(1-z
-1)+vo
i (3)
To of
I+1Carry out differential, that is, multiply by delay operator D=(1-z
-1), and with D * of
I+1With of
iAddition obtains vo
iCompensation:
D×of
i+1+of
i＝-vo
i×(1-z
-1)+vi
i+(1-z
-1)×((-vo
i+1×(1-z
-1)+vo
i))
＝vi
i-(1-z
-1)
2×vo
i+1 (4)
Identical scheme can be expanded to system with m accumulator stage.For such system, the output signal Δ N of Sigma-delta modulator is provided by following formula:
ΔN＝vi
0-(1-z
-1)
m×vo
m (5)
Owing to the pace of change of accumulator contents along with its sequence number (order) increases, the pace of change of N increases along with the increase of number of accumulators too.The rapid fluctuations of N is littler than slow oscillator to the interference of the operation of variable ratio frequency changer synthesizer, and this is because low pass filter has reduced to be included in the high-frequency noise in the signal that offers input.As a result, reduced phase jitter.
Utilize
ω wherein
nBe normalized frequency (| z
1|≤1), can estimate the maximum fluctuation g of Δ N
m:
g
m＝|(1-z
-1)
m×vo
m| (6)
Frequency to electric capacity is carried out normalization, vo
mWill be less than 1 (vo
m＜1).Use v
m=1, will obtain and the irrelevant g of actual capacitance
mValue.
With reference to accompanying drawing 4, provided at expection average divide device ratio N
IntThe curve chart of the output signal of=10.62501526 divider ratio controller with level Four.According to equation (6), maximum fluctuation g
mBe 16.
Summary of the invention
The problem that constitutes basis of the present invention provides a kind of improved variable ratio frequency changer synthesizer.And, the facilitated method that corresponding divider ratio controller also will be provided and operate this divider ratio controller.
The feature of the characteristic by claim 1, the variable ratio frequency changer synthesizer at according to the preamble of claim 1 has solved the problem that constitutes basis of the present invention.
According to claim 1, the variable ratio frequency changer synthesizer comprises: voltage controlled oscillator, and this voltage controlled oscillator produces the oscillator signal that frequency depends on the input signal that imposes on described voltage controlled oscillator; Frequency divider, this frequency divider receive described oscillator signal and produce frequency and equal the frequency divider signal of the frequency of described oscillator signal divided by divider ratio; Phase detectors, these phase detectors provide phase signal according to the phase difference between described frequency divider signal and the reference signal, and described phase signal decision imposes on the described input signal of described voltage controlled oscillator; The divider ratio controller, comprise Sigma-delta modulator and described divider ratio is provided, described Sigma-delta modulator comprises a plurality of accumulator stages being connected in cascade, each accumulator stage adds up to input value and provide spill over when reaching peaked, first accumulator stage in the described series connection receives first component of the fractional part of expection average divide device ratio as input value, each follow-up accumulator receive be positioned at before the described follow-up accumulator and the accumulator value of the accumulator adjacent with described follow-up accumulator as first component of input value, each spill over value is in the identical number of times of progression of the accumulator before the accumulator that described each spill over value is provided in differential and the described series connection, add up to all spill over values forming the output signal of described Sigma-delta modulator afterwards, described divider ratio be described Sigma-delta modulator described output signal and expection average divide device ratio integer part and; It is characterized in that at least one input value has second component, this second component equals spill over and multiply by a coefficient.
One of advantage of the present invention is that the fluctuation of divider ratio has obtained reducing, and then phase jitter has obtained reducing.
According to a feature of the present invention, each accumulator stage receives has the input value of second component, and this second component equals described accumulator stage spill over separately and multiply by a coefficient.
According to another feature of the present invention, charge pump circuit is connected between described phase detectors and the described voltage controlled oscillator, the input that is used to receive described phase detectors signal and charge pump signal is offered described voltage controlled oscillator.
According to further improvement of the present invention, loop filter is connected between described charge pump and the described voltage controlled oscillator, is used for before described charge pump signal is provided to the input of described voltage controlled oscillator described charge pump signal being carried out filtering.
The feature of the characteristic by claim 5 has solved the problem according to the divider ratio controller of the preamble of claim 5.
According to claim 5, the divider ratio controller in the middle of a kind of variable ratio frequency changer synthesizer, the variable ratio frequency changer synthesizer comprises: voltage controlled oscillator, this voltage controlled oscillator produces the oscillator signal that frequency depends on the input signal that imposes on described voltage controlled oscillator; Frequency divider, this frequency divider receive described oscillator signal and produce frequency and equal the frequency divider signal of the frequency of described oscillator signal divided by divider ratio; Phase detectors, these phase detectors provide phase signal according to the phase difference between described frequency divider signal and the reference signal, and described phase signal decision imposes on the described input signal of described voltage controlled oscillator; Described divider ratio controller comprises Sigma-delta modulator and described divider ratio is provided, described Sigma-delta modulator comprises a plurality of accumulator stages being connected in cascade, each accumulator stage adds up to input value and provide spill over when reaching peaked, first accumulator stage in the described series connection receives first component of the fractional part of expection average divide device ratio as input value, each follow-up accumulator receive be positioned at before the described follow-up accumulator and the accumulator value of the accumulator adjacent with described follow-up accumulator as first component of input value, each spill over value is in the identical number of times of progression of the accumulator before the accumulator that described each spill over value is provided in differential and the described series connection, add up to all spill over values forming the output signal of described Sigma-delta modulator afterwards, described divider ratio be described Sigma-delta modulator described output signal and expection average divide device ratio integer part and; It is characterized in that at least one input value has second component, this second component equals spill over and multiply by a coefficient.
By the feature of claim 6 characteristic, solved problem according to the method for the operation divider ratio controller of the preamble of claim 6.
According to claim 6, a kind of method of operating the central divider ratio controller of variable ratio frequency changer synthesizer, this variable ratio frequency changer synthesizer has: voltage controlled oscillator, and this voltage controlled oscillator produces the oscillator signal that frequency depends on the input signal that imposes on described voltage controlled oscillator; Frequency divider, this frequency divider receive described oscillator signal and produce frequency and equal the frequency divider signal of the frequency of described oscillator signal divided by divider ratio; Phase detectors, these phase detectors provide phase signal according to the phase difference between described frequency divider signal and the reference signal, and described phase signal decision imposes on the described input signal of described voltage controlled oscillator; Described divider ratio controller comprises the Sigma-delta modulator with a plurality of accumulator stages and described divider ratio is provided, described accumulator stage is connected in series, described method comprises step: first accumulator stage in the described series connection receives first component of the fractional part of expection average divide device ratio as input value, each follow-up accumulator receive be positioned at before the described follow-up accumulator and the accumulator value of the accumulator adjacent with described follow-up accumulator as first component of input value; Each accumulator stage adds up to input value; Each accumulator stage provides the spill over value when reaching peaked; Each spill over value is in the identical number of times of progression of the accumulator before the accumulator that described each spill over value is provided in differential and the described series connection; The integer part that adds up to described spill over the expection average divide device ratio of described Sigma-delta modulator is to produce described divider ratio; It is characterized in that following step: spill over be multiply by a coefficient and be provided as the second component of input value.
Description of drawings
Now with reference to accompanying drawing, only, introduce embodiments of the invention in the mode of example, wherein:
Accompanying drawing 3 is models of accumulator stage in the prior art;
Accompanying drawing 4 is figures of the output signal of the controller of divider ratio described in the prior art;
Accompanying drawing 5 is the schematic diagrames according to divider ratio controller of the present invention;
Accompanying drawing 6 is the models according to accumulator stage of the present invention;
Accompanying drawing 7 is figures of the output signal of foundation described divider ratio controller of the present invention under the situation of K=0.5;
Accompanying drawing 8 is figures of the output signal of foundation described divider ratio controller of the present invention under the situation of K=0.75;
Accompanying drawing 9 is expression tables according to the dynamic characteristic of described divider ratio controller of the present invention;
Accompanying drawing 10 is first optional embodiment according to divider ratio controller of the present invention;
Accompanying drawing 11 is second optional embodiment according to divider ratio controller of the present invention;
Accompanying drawing 12 is the 3rd optional embodiment according to divider ratio controller of the present invention.
Embodiment
With reference to accompanying drawing 5, the divider ratio controller is made of several accumulators AC51, AC52, AC53, the AC54 that are connected in series.The output of accumulator and the input of next accumulator are connected in series.When the value in being stored in accumulator surpassed by the given limiting value of accumulator capacity separately, accumulator overflowed, and produces spill over of
1, of
2, of
3And of
4These spill overs are fed back to the input of each accumulator after divided by coupling coefficient K.Therefore, the input signal of each accumulator has two components.The input signal of first accumulator is made up of the spill over of decimal and feedback, and the input signal of accumulator subsequently is made up of the output signal of previous accumulator and the spill over of feedback.These spill overs carry out differential and addition by differentiator DIF51, DIF52, DIF53 and DIF54, are added to whole numercal signal delta N with formation.The quantity of accumulator stage is actually arbitrarily.Why selecting four accumulator stages, is because this quantity is very suitable for illustrating basic functional principle.
Provided in the accompanying drawing 6 basic accumulator stage model (below, equally with vi
i(z) be abbreviated as vi
i, or the like).
Similar with equation (2), of
iCan be write as:
The output signal vo of accumulator stage
iBe the input signal vi of next accumulator stage
I+1, that is, order is the accumulator stage of i+1.Therefore, of
I+1Can be expressed as:
According to prior art, to of
I+1Differential promptly, multiply by D=(1-z
-1), and with D * of
I+1And of
iAddition obtains vo
iCompensation.
Same scheme can be expanded to the system with m accumulator stage equally.For such system, the output signal Δ N of Sigma-delta modulator is provided by following formula:
Therefore, the maximum fluctuation g of Δ N
mCan be estimated as:
Under the situation of K=0, equation (13) is equivalent to describe in the prior art equation (6) of the maximum fluctuation of Sigma-delta modulator.
With reference to accompanying drawing 7, coupling coefficient K=0.5 and expection average divide device ratio N have been provided
IntThe figure of the output signal of the divider ratio controller under=0.62501526 the situation.According to equation (11), maximum fluctuation g
m=10.66.Compare maximum fluctuation g with the divider ratio controller of prior art
mObviously reduce.
With reference to accompanying drawing 8, coupling coefficient K=0.75 and expection average divide device ratio N have been provided
IntThe figure of the output signal of the divider ratio controller under=0.62501526 the situation.According to equation (11), maximum fluctuation g
m=9.14.Compare maximum fluctuation g with the divider ratio controller of K=0.5
mFurther reduce.
Accompanying drawing 9 shows the dynamic characteristic of the divider ratio controller shown in the accompanying drawing 5.In this example, the capacity of each accumulator is 31.Decimal is 10, is equivalent to 0.625 numerical value.
In first cycle period, decimal fractions 10 is loaded among the AC51.The input value of accumulator subsequently is equivalent to the accumulator value of previous accumulator,, is stored in the value in the accumulator separately that is.Therefore, the content of capacitor AC51, AC52, AC53, AC54 is increased to 10 from 0.
In second cycle period, the input value of each accumulator is added on the accumulator content separately.The input value vi of accumulator AC52
2The output valve vo that is equivalent to accumulator AC51
1, or the like.But, the accumulator value of accumulator AC53 has exceeded capacity.Therefore, produced spill over of
3The accumulator value of accumulator AC53 cut with spill over be worth (that is, 32) accordingly.The input value of accumulator 54 is equivalent to the accumulator value of accumulator 53 equally.Spill over of
3By differentiator DIF52, DIF51 differential twice, then with other null spill over addition.
Each differential is equivalent to multiply by (1-z
-1).For clock cycle i, z
-1Equal the spill over that during clock cycle i-1, produces and z
-2Correspondingly equal the spill over that during clock cycle i-2, produces, or the like.Like this, spill over of
3Contribution to Δ N is provided by following formula:
con
3＝(1-z
-1)
2×of
3
＝(1-2z
-1+z
-2)×of
3
＝(1-2×0+0)×1＝1
Δ N is provided by following formula:
ΔN＝con
1+con
2+con
3+con
4
＝0+0+1+0
In the 3rd cycle period, (in the figure of divider ratio controller, this is multiplied each other is labeled as divided by 2 to multiply by 16 at spill over.In fact coupling coefficient refers to spill over and is worth accordingly, that is, and and 32.) afterwards, with the spill over of that produces during the last clock cycle
3With the output signal addition of accumulator AC52, to form the input signal of accumulator AC53.In this circulation, accumulator AC52 and AC54 also can overflow.Contribution con at accumulator AC52
2Before the adding, to the spill over of of accumulator AC52
2Differential once, wherein con2 is provided by following:
con
2＝(1-z
-1)×of
2
＝(1-0)×1＝1
Contribution con at accumulator AC54
4Before being added into, to the spill over of of accumulator AC54
4Differential three times, wherein con
4Provide by following formula:
con
4＝(1-z
-1)
3×of
4
＝(1-3z
-1+3z
-2-z
-3)×of
4
＝(1-3×0+3×0-0)×1＝1
Another contribution con to Δ N
3Provide by following formula:
con
3＝(1-z
-1)
2×of
3
＝(1-2z
-1+z
-2)×of
3
＝(1-2×1+0)×1＝-1
Like this, Δ N equals:
ΔN＝con
1+con
2+con
3+con
4
＝0+1-1+1＝1
Other value in the table can be calculated according to identical mode.As shown in Figure 5, be used as of of example
4And of
3Be actually to of
4Carried out addition after the subdifferential.But, the variation of order does not influence result of calculation, and selected implementation needs differentiator seldom.
Provided the optional embodiment of divider ratio controller in the accompanying drawing 10 to 12.Generally speaking, the coefficient that the spill over of accumulator is taken advantage of before the spill over accumulator feeds back to accumulator input separately can have value arbitrarily, and for each the different accumulator as the part of same divider ratio controller, coefficient can be different.In addition, and nonessential spill over to all accumulator stages feed back.The input signal of accumulator can have three-component, and this three-component depends on the spill over from another accumulator.At last, the second component of accumulator input signal can not depend on accumulator spill over separately, but can depend on the spill over of another accumulator.
With reference to accompanying drawing 10, the input signal of accumulator 102 only is made up of the output signal of last accumulator.Accumulator 102 does not have second component.Before the spill over accumulator 104 feeds back to accumulator input separately, with the spill over of accumulator 104 divided by 4 (multiply by 1/4).
With reference to accompanying drawing 11, the input signal of accumulator 111 has three-component, and this three-component is provided divided by 2 by the spill over of back one accumulator 112.The spill over of accumulator 112 does not feed back to its input.
With reference to accompanying drawing 12, the second component of the input signal of accumulator 121 is provided divided by 2 by the spill over of accumulator 122.The spill over of accumulator 121 does not feed back to its input.
Claims (6)
1. variable ratio frequency changer synthesizer comprises:
-voltage controlled oscillator (VCO), this voltage controlled oscillator generated frequency depends on the input signal (u that imposes on described voltage controlled oscillator (VCO)
Cp) oscillator signal (u
VCO);
-frequency divider, this frequency divider receive described oscillator signal and produce frequency and equal the frequency divider signal (u of the frequency of described oscillator signal divided by divider ratio
DIV);
-phase detectors (PD), these phase detectors are according to described frequency divider signal (u
DIV) and reference signal (u
REF) between phase difference phase signal (u is provided
PD), described phase signal decision imposes on the described input signal of described voltage controlled oscillator;
-divider ratio controller (DRC), comprise Sigma-delta modulator and described divider ratio is provided, described Sigma-delta modulator comprises a plurality of accumulator stages being connected in cascade, each accumulator stage adds up to input value and provide spill over when reaching peaked, first accumulator stage in the described series connection receives first component of the fractional part of expection average divide device ratio as input value, each follow-up accumulator receive be positioned at before the described follow-up accumulator and the accumulator value of the accumulator adjacent with described follow-up accumulator as first component of input value, each spill over value is in the identical number of times of progression of the accumulator before the accumulator that described each spill over value is provided in differential and the described series connection, add up to all spill over values forming the output signal of described Sigma-delta modulator afterwards, described divider ratio be described Sigma-delta modulator described output signal and expection average divide device ratio integer part and;
It is characterized in that:
At least one input value has second component, and this second component equals spill over and multiply by a coefficient.
2. variable ratio frequency changer synthesizer according to claim 1 is characterized in that:
Each accumulator stage receives has the input value of second component, and the spill over that this second component equals described each accumulator stage multiply by a coefficient.
3. according to the described variable ratio frequency changer synthesizer of aforementioned any one claim, it is characterized in that
Charge pump circuit is connected between described phase detectors and the described voltage controlled oscillator, the input that is used to receive described phase detectors signal and charge pump signal is offered described voltage controlled oscillator.
4. variable ratio frequency changer synthesizer according to claim 3 is characterized in that:
Loop filter is connected between described charge pump and the described voltage controlled oscillator, is used for before described charge pump signal is provided to the input of described voltage controlled oscillator described charge pump signal being carried out filtering.
5. the divider ratio controller in the middle of the variable ratio frequency changer synthesizer, described variable ratio frequency changer synthesizer comprises:
-voltage controlled oscillator (VCO), this voltage controlled oscillator produce frequency and depend on the input signal (u that imposes on described voltage controlled oscillator (VCO)
Cp) oscillator signal (u
VCO);
-frequency divider, this frequency divider receive described oscillator signal and produce frequency and equal the frequency divider signal (u of the frequency of described oscillator signal divided by divider ratio
DIV);
-phase detectors (PD), these phase detectors are according to described frequency divider signal (u
DIV) and reference signal (u
REF) between phase difference phase signal (u is provided
PD), described phase signal decision imposes on the described input signal of described voltage controlled oscillator;
Described divider ratio controller (DRC) comprises Sigma-delta modulator and described divider ratio is provided, described Sigma-delta modulator comprises a plurality of accumulator stages being connected in cascade, each accumulator stage adds up to input value and provide spill over when reaching peaked, first accumulator stage in the described series connection receives first component of the fractional part of expection average divide device ratio as input value, each follow-up accumulator receive be positioned at before the described follow-up accumulator and the accumulator value of the accumulator adjacent with described follow-up accumulator as first component of input value, each spill over value is in the identical number of times of progression of the accumulator before the accumulator that described each spill over value is provided in differential and the described series connection, add up to all spill over values forming the output signal of described Sigma-delta modulator afterwards, described divider ratio be described Sigma-delta modulator described output signal and expection average divide device ratio integer part and;
It is characterized in that:
At least one input value has second component, and this second component equals spill over and multiply by a coefficient.
6. method of operating the divider ratio controller in the middle of the variable ratio frequency changer synthesizer, this variable ratio frequency changer synthesizer has: voltage controlled oscillator (VCO), this voltage controlled oscillator produce frequency and depend on the input signal (u that imposes on described voltage controlled oscillator (VCO)
Cp) oscillator signal (u
VCO); Frequency divider, this frequency divider receive described oscillator signal and produce frequency and equal the frequency divider signal (u of the frequency of described oscillator signal divided by divider ratio
DIV); Phase detectors (PD), these phase detectors are according to described frequency divider signal (u
DIV) and reference signal (u
REF) between phase difference phase signal (u is provided
PD), described phase signal decision imposes on the described input signal of described voltage controlled oscillator; Described divider ratio controller (DRC) comprises the Sigma-delta modulator with a plurality of accumulator stages and described divider ratio is provided, and described accumulator stage is connected in series, and described method comprises step:
First accumulator stage in the-described series connection receives first component of the fractional part of expection average divide device ratio as input value, each follow-up accumulator receive be positioned at before the described follow-up accumulator and the accumulator value of the accumulator adjacent with described follow-up accumulator as first component of input value;
-each accumulator stage adds up to input value;
-each accumulator stage provides the spill over value when reaching peaked;
-each spill over value is in the identical number of times of progression of the accumulator before the accumulator that described each spill over value is provided in differential and the described series connection;
-add up to the integer part of described spill over the expection average divide device ratio of described Sigma-delta modulator, to produce described divider ratio;
It is characterized in that following step:
-spill over be multiply by a coefficient and be provided as the second component of input value.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/EP2003/008233 WO2005015744A1 (en) | 2003-07-25 | 2003-07-25 | Variable frequency synthesizer comprising a sigma-delta modulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1714510A true CN1714510A (en) | 2005-12-28 |
| CN100399701C CN100399701C (en) | 2008-07-02 |
Family
ID=34129887
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB038256231A Expired - Fee Related CN100399701C (en) | 2003-07-25 | 2003-07-25 | Variable frequency synthesizer comprising a sigma-delta Modulator |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US7081798B2 (en) |
| EP (1) | EP1649601A1 (en) |
| JP (1) | JP2007515813A (en) |
| CN (1) | CN100399701C (en) |
| AU (1) | AU2003263187A1 (en) |
| WO (1) | WO2005015744A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101114832B (en) * | 2006-07-28 | 2011-05-25 | 晨星半导体股份有限公司 | Delta-sigma modulated fractional-n pll frequency synthesizer |
| CN107248862A (en) * | 2017-06-09 | 2017-10-13 | 芯海科技（深圳）股份有限公司 | A kind of fractional frequency division reduction frequency jitter circuit and method |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI376877B (en) * | 2008-12-26 | 2012-11-11 | Ind Tech Res Inst | Clock generator and multimodulus frequency divider and delta-sigma modulator thereof |
| US8816724B2 (en) | 2011-12-16 | 2014-08-26 | University College Cork—National University of Ireland, Cork | Nested digital delta-sigma modulator |
| CN111884655B (en) * | 2020-07-27 | 2024-02-20 | 中国电子科技集团公司第三十六研究所 | Variable-analog-to-decimal frequency conversion serial signal processing method and device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2019297A1 (en) * | 1990-01-23 | 1991-07-23 | Brian M. Miller | Multiple-modulator fractional-n divider |
| US5305362A (en) * | 1992-12-10 | 1994-04-19 | Hewlett-Packard Company | Spur reduction for multiple modulator based synthesis |
| JP3256422B2 (en) * | 1995-10-23 | 2002-02-12 | 日本電気株式会社 | Frequency synthesizer |
| US6600788B1 (en) * | 1999-09-10 | 2003-07-29 | Xilinx, Inc. | Narrow-band filter including sigma-delta modulator implemented in a programmable logic device |
| US6717998B2 (en) * | 1999-12-13 | 2004-04-06 | Matsushita Electric Industrial Co., Ltd. | Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method |
| US6570452B2 (en) * | 2001-09-26 | 2003-05-27 | Ashvattha Semiconductor, Inc. | Fractional-N type frequency synthesizer |
-
2003
- 2003-07-25 JP JP2005507502A patent/JP2007515813A/en not_active Withdrawn
- 2003-07-25 AU AU2003263187A patent/AU2003263187A1/en not_active Abandoned
- 2003-07-25 EP EP03817933A patent/EP1649601A1/en not_active Withdrawn
- 2003-07-25 WO PCT/EP2003/008233 patent/WO2005015744A1/en active Application Filing
- 2003-07-25 CN CNB038256231A patent/CN100399701C/en not_active Expired - Fee Related
-
2005
- 2005-08-05 US US11/197,778 patent/US7081798B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101114832B (en) * | 2006-07-28 | 2011-05-25 | 晨星半导体股份有限公司 | Delta-sigma modulated fractional-n pll frequency synthesizer |
| CN107248862A (en) * | 2017-06-09 | 2017-10-13 | 芯海科技（深圳）股份有限公司 | A kind of fractional frequency division reduction frequency jitter circuit and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100399701C (en) | 2008-07-02 |
| AU2003263187A1 (en) | 2005-02-25 |
| EP1649601A1 (en) | 2006-04-26 |
| WO2005015744A1 (en) | 2005-02-17 |
| US20060055469A1 (en) | 2006-03-16 |
| US7081798B2 (en) | 2006-07-25 |
| JP2007515813A (en) | 2007-06-14 |
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