CN101421927A

CN101421927A - RF synthesizer and RF transmitter or receiver incorporating the synthesizer

Info

Publication number: CN101421927A
Application number: CN 200680033046
Authority: CN
Inventors: 索伦·彼得·拉森; 雅各布·特拉内高·汉森
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 2005-09-08
Filing date: 2006-08-25
Publication date: 2009-04-29
Also published as: WO2007030358A3; GB2430090A; GB2430090B; EP1929676A4; EP1929676A2; GB0518215D0; WO2007030358A2

Abstract

An RF (radio frequency) synthesizer (200) includes a VCO (voltage controlled oscillator) (120) operable to provide an output signal at a desired frequency, a phase locked loop (130) including (i) the VCO; (ii) a frequency divider (114) operable to receive an output signal of the VCO and to provide a feedback signal which is divided in frequency relative to the output signal of the VCO; and (iii) a phase frequency detector (110) operable to receive the feedback signal produced by the VCO and to compare a phase and frequency of the feedback signal with the phase and frequency of a reference signal; and is characterised by (iv) a further control loop (230) inside the phase locked loop (130); and (v) a phase rotator (205) connected to an output of the VCO and operable to equalise a phase error of an output signal produced by the VCO, the further control loop being connected to the phase rotator to provide a control signal to the phase rotator. The synthesizer may beneficially include an integrated circuit which incorporates at least part of the VCO, the phase locked loop and the further control loop. Also described is a RF transmitter or receiver, e.g. for use in a base transceiver station, which incorporates the synthesizer.

Description

RADIO FREQUENCY SYNTHESIZER and the transmitter or the receiver that contain this synthesizer

Technical field

The RF transmitter or the receiver that the present invention relates to a kind of RF (radio frequency) synthesizer and contain this RF synthesizer.Especially, the present invention relates to a kind of RF synthesizer of stablizing the RF signal that is used to generate, comprising the VCO that can be used for transmitting set or receiver (voltage controlled oscillator).

Background technology

Carrier frequency signaling in the RF communication transmitter is generated by frequency synthesizer usually, and wherein this frequency synthesizer comprises the VCO that is connected with phase-locked loop (PLL).The phase-locked loop that comprises this VCO provides moderately stable output signal with the frequency of explication.This VCO adopts resonator part, tuning part and amplifier or active part usually, this resonator partly provides the vibration in including the given frequency range of this output signal frequency, this tuning part for example adopts one or more voltage operated devices (for example variable capacitance diode), comes to carry out tuning to output frequency according to input control voltage.

The RF synthesizer can also be used in the RF receiver, so that accurate benchmark (local oscillator) frequency signal to be provided.In many cases, this Receiver And Transmitter is combined in the single transceiver unit.

In the prior art, adopted frequency divider, be used for providing suitable feedback at phase-locked loop based on the synthesizer of VCO in the phase-locked loop.In many cases, these frequency dividers are variable frequency divider, and promptly they will be from this feedback signal of VCO divided by variable divisor number.An example of this frequency divider is exactly so-called " decimal-N " frequency divider.Be known that and use this frequency divider, particularly variable frequency divider, can in the output spectrum of VCO, produce the pseudo-peak value of not expecting.When the VCO frequency of operation increased, the problem of these pseudo-peak values can worsen.

Various settings is exactly in order to solve the above-mentioned pseudo-spike problem of not expecting in the prior art.US-A-6 for example, 642,800, US-A-6,515,525, the example described in WO-A-2004/100380 and the WO-2002/058243.But the beneficial effect that the invention provides settling mode and therefore acquisition is not predict in the prior art.

Summary of the invention

According to a first aspect of the invention, provide a kind of as claims 1 defined RF synthesizer.

According to a second aspect of the invention, provide a kind of as claims 22 defined RF transmitters.

According to a third aspect of the present invention, provide a kind of as claims 23 defined RF transmitters.

Further feature of the present invention defines in appended dependent claims, and discloses in the embodiment of the invention that will describe.

By the present invention, a kind of synthesizer is provided, wherein solved problem as occurring in the described prior art in early time in a kind of new mode, the i.e. pseudo-peak value of not expecting that produces owing to frequency division (particularly for example the variable frequency divider of decimal-Fractional-N frequency device) is to provide feedback in phase-locked loop.Extra control loop is provided, in order to the phase error in the output signal of measuring the synthesizer VCO that causes owing to this puppet peak value, and phase rotation device is provided, in order to changing the phase place of this VCO output signal, thereby the phase error that records has been proofreaied and correct (equilibrium).

Can provide to the VCO of the new synthesizer of small part valuably with the form of integrated circuit (for example semiconductor chip), it can also comprise the circuit to small part PLL.This is impracticable for realizing in the prior art such as less than the output frequency of 1GHz, because can't satisfy the phase noise performance of the synthesizer of this form under these frequencies.

Embodiments of the invention are described below with reference to accompanying drawings by way of example, wherein:

Description of drawings

Fig. 1 is the schematic block diagram of explanation according to the frequency synthesizer of the embodiment of the invention;

Fig. 2 schematically illustrates integrated circuit, and wherein this integrated circuit has comprised the parts of the synthesizer of Fig. 2 in the integrated circuit zone;

Fig. 3 illustrates the schematic block diagram of frequency synthesizer according to another embodiment of the present invention;

Fig. 4 schematically illustrates integrated circuit, and wherein this integrated circuit has comprised the parts of the synthesizer of Fig. 3 in the integrated circuit zone;

Fig. 5 is the block diagram that uses the replaceable setting of parts in the synthesizer of key diagram 1;

Fig. 6 is the block diagram that uses another replaceable setting of parts in the synthesizer of key diagram 1;

Fig. 7 is the block diagram of the more detailed part of setting in the displayed map 5; And

Fig. 8 is the schematic block diagram of the phase rotation device in the synthesizer that is useful in Fig. 1 when containing being provided with of Fig. 5 and 7.

Embodiment

Referring now to Fig. 1, wherein Fig. 1 is generally drawn and is made 200 schematic circuit for embodying frequency synthesizer of the present invention.This frequency synthesizer 200 comprises: reference oscillator 102 (for example crystal oscillator), controller 108, phase-frequency detector 110, charge pump 117, loop filter 118, VCO 120 and feedback divider 114.This VCO 120 comprises following component part: VCO tuning and resonance piece or part 12 and active of VCO or part 16.This reference oscillator 102 is connected with phase-frequency detector 110.This feedback divider 114 is connected with phase-frequency detector 110, controller 108 and active 116 of VCO.This charge pump 117 is connected with phase-frequency detector 110 and loop filter 118.This loop filter 118 is connected with resonance piece 112 and charge pump 117 with VCO is tuning.Active 116 of this VCO is connected with resonance piece 112 and feedback divider 114 with VCO is tuning.The loop that includes VCO120, frequency divider 114, phase-frequency detector 110, charge pump 117 and loop filter 118 has formed PLL (phase-locked loop) 130.

This reference oscillator 102 offers phase-frequency detector 110 with reference signal.This feedback divider 114 receives has frequency F _OUTFeedback signal as output from active 116 of VCO.This feedback divider 114 divided by divisor M, and will have frequency F with the frequency of this signal _OUTThe signal that obtains of/M offers phase-frequency detector 110.The respective phase and the frequency of the feedback signal that 110 pairs of these reference signals of this phase-frequency detector and it receive compare, and generate the output control signal in response.

Typically, the operation of this phase-frequency detector 110 is as follows.This phase-frequency detector 110 receives two input signals and generates one of two possibility (replaceable) output signals.This input signal is from (variable) reference signal of reference oscillator 102 and from the feedback signal of feedback divider 114.These two may output signal be two types impulse form, i.e. first pulse pattern and second pulse pattern, for example known " Up (making progress) " with variable-width and " Down (downwards) " pulse.When making that less than the frequency of reference signal reference signal is led over feedback signal owing to the frequency of this feedback signal, this phase-frequency detector 110 generates the pulse (for example " Up " pulse) of the first kind, and is leading in order to point out this reference signal.On the contrary, when making that greater than the frequency of reference signal reference signal lags behind feedback signal owing to the frequency of this feedback signal, this phase-frequency detector 110 generates the pulse (for example " Down " pulse) of second type, lags behind in order to point out this reference signal.The pulse duration of this first kind pulse and the second type pulse detected phase difference all and between this reference signal and feedback signal is proportional, (therefore, causing this phase-frequency detector 110 that linear phase difference response is provided).Difference on the frequency and phase difference between two inputs of this phase-frequency detector 110 are provided by for example phase-frequency detector 110, to allow for example when this PLL120 is used in the radio transmitter, the value by the severals M above changing is for example proofreaied and correct the difference on the frequency that occurs as startup PLL130 or when switching the channel frequence of this PLL130.

This phase-frequency detector 110 comprises the amplifier (not shown), and it amplifies the signal that is provided as output control signal (pulse of suitable above-mentioned first or second type).This phase-frequency detector 110 offers charge pump 17 and loop filter 118 with its output control signal.If this charge pump 117 has received first kind of pulse from phase-frequency detector 110, then it orders about electric current and enters into loop filter 118.If this charge pump 117 has received second kind of pulse from phase-frequency detector 110, then it pulls out electric current from this loop filter 118.To and comprise that by the adjusted in this way loop filter 118 of charge pump 117 conversion of signals of a series of pulses is synthetic output control voltage V from phase-frequency detector 110 _OUT, wherein voltage V is controlled in this output that obtains _OUTCan be applied in the tuning and resonance piece of this VCO 112 as adjusting bias voltage.

The output control voltage V that this VCO is tuning and resonance piece 112 receives according to it _OUTValue, the output frequency F of the signal that its is generated _OUTBe adjusted into and equal desired value.When this PLL130 becomes when stablizing this V _OUTThe frequency dependence of the value reference signal that will provide with the value of divisor M and by this reference oscillator 102.Therefore when this synthesizer 200 of design, select these parameter values, to provide desired output frequency F _OUTActive 116 pairs frequencies tuning by this VCO and that resonance piece 112 generates of this VCO are F _OUTSignal amplify, and with its as frequency for having frequency F _OUTOutput signal offer outgoing route 150 and offer feedback divider 114 among the PLL130.

Loop filter 118 in this synthesizer 100 also filters away the shake that is for example caused by the noise of this charge pump 117, and prevents voltage overshoot.

Controller 108 in this synthesizer 100 provides the control to this divisor M value, and provides this V _OUTThe adjustment of value.In a kind of feedback divider 114 of form, this frequency divider 114 can be variable frequency divider.In this form, can switch fast according to the predefine changeover program between first Integer N and second integer (for example N+1) by controller 108, change the value of M.The effect of doing has so just provided the mean value of the M that equals the value between the N and second integer.Under situation about switching between continuous integral number N and the N+1, variable feedback frequency divider known in the art is exactly " decimal-N " frequency divider.

In fact this controller 108 can be programmable digital signal processor.When this synthesizer 100 was used in the RF transceiver, this controller 108 can be carried out other controls and the signal processing function of this transceiver.

This synthesizer 200 comprises extra (further) control loop 230 that is arranged in PLL 120.This extra control loop 230 comprises phase detectors 201 that are connected with extra loop path filter 203 and the phase rotation device 205 that is connected with extra loop path filter 203.This phase rotation device 205 is arranged in path 207, in this path 207 between VCO 120 and the outgoing route 150 and between VCO 120 and feedback divider 114.These phase detectors 201 are connected with feedback divider 114 and are connected with reference divider 104, and receive from the feedback signal of this feedback divider 114 and from the reference signal of this reference oscillator 102 as input signal.Any phase difference that these phase detectors 201 detect between this feedback signal and the reference signal, and correspondingly this output signal is offered loop filter 203.203 pairs of output signals from phase detectors 201 of this loop filter are carried out filtering and are quadratured, and control signal is offered phase rotation device 205.

The purpose of extra control loop 230 that includes phase rotation device 205 is as follows.Feedback divider 114 in using phase-locked loop 230 is as variable frequency divider, for example described in early time decimal-Fractional-N frequency device, just false signal might occur in the spectral sideband of the output signal that is generated by VCO 120, this is that quick switching owing to the divisor M value that is applied in feedback division by feedback divider 114 causes.This false signal from variable feedback frequency divider is known in this area.These phase detectors 201 are measured any phase error that produces in this manner in the output signal that is generated by VCO 120, and by loop filter 203 this are pointed out that the control signal of phase error offers phase rotation device 205.This phase rotation device 205 puts on phase change the output signal that is provided by this VCO 120.Come definite adaptively phase changing capacity that applies by this phase rotation device 205 by the control signal that applies self loop filter 203, and thus this phase changing capacity is adjusted continuously, to be suitable for that the detected phase error in the output signal that is provided by this VCO 120 is carried out equilibrium.

This phase rotation device 205 is known equipment, is used to make phase of input signals Spin Control amount, and wherein this controlled quentity controlled variable is by the aequum that applies from the input control signal appointment of this extra control loop 230.This phase rotation device 205 can be the analog or digital phase rotation device.When this phase rotation device 205 is the digit phase circulator, it can according to the modulator of phase modulated RF transmitter in the similar mode of known digital phase rotation device used operate, be used for the phase place of carrier signal is modulated.To the example of the digit phase circulator of preferred particular form be described with reference to Fig. 8 in the back.

Select the loop bandwidth of main loop (being PLL130) in this synthesizer 200, realize maximum phase noise suppressed by the output signal of this VCO 120 generations.Therefore, for example for F _VCO=10 to 20GHz, and this bandwidth is narrow, for example the scope of 2kHz to 10MHz, the preferably scope of 2kHz to 5MHz.On the contrary, select the loop bandwidth of secondary ring (being extra control loop 230), realize the fast speed phase error equalization and the suitable stability of a system.Therefore satisfactorily, the loop bandwidth of this extra control loop 230 for example is at least approximately twice of PLL 130 bandwidth much larger than the bandwidth of PLL 130, about ten times at least of PLL 130 bandwidth especially typically.For example for F _VCO=10MHz to 20GHz, satisfactorily, the bandwidth of this extra control loop 230 is at least 10MHz, for example from 10MHz to 100MHz.

In fact the controller 108 of this synthesizer 200 can be programmable digital signal processor.When this synthesizer 200 was used in the RF transceiver, this controller 108 can be carried out other the known controls and the signal processing function of this transceiver.

The form that can by using known manufacturing technology the VCO120 and the miscellaneous part of this synthesizer 200 be fabricated to integrated circuit valuably, for example semiconductor chip.This integrated circuit can comprise most of miscellaneous part of this synthesizer 200.The parts that provide discretely just normally are provided for this reference oscillator 102 and loop filter 118 and 203.In other words, can be with integrated circuit, for example the form of semiconductor chip is made all parts that are surrounded by dotted line shown in Fig. 1 260 together.In some cases, in this integrated circuit even can comprise loop filter 118 and/or loop filter 203.

Fig. 2 schematically describes integrated circuit 270, and comprising the parts that are surrounded as dotted line among Fig. 1 260, it is shown as the zone 280 of integrated circuit 270.This integrated circuit 270 can provide alternatively by one or more other functions that part provided in another zone 290 of integrated circuit 270.

Referring now to Fig. 3, Fig. 3 is the schematic circuit of the frequency synthesizer (generally being marked as 300) of further embodiment according to the present invention.Among Fig. 3 with the synthesizer 200 of Fig. 1 in the parts of parts with same reference numbers have with these parts identical functions and according to identical mode and operate.This synthesizer 300 is the modification of synthesizer 200.The example that is revised as following setting in this synthesizer 300 reduces the output signal that obtains desired frequency by the output signal that is generated by high frequency VCO is carried out frequency division in this is provided with.This set is the theme of the applicant in the common unsettled UK patent application that proposes on the same day.

In the frequency synthesizer 300 of Fig. 3, replace VCO120 among Fig. 1 with VCO 320.This VCO 320 has the tuning and resonance piece 312 of VCO and VCO active 316.(for given output frequency) this VCO 320 is operating than VCO 120 higher frequency places.For example, if the scope of desired output frequency is 100MHz to 1GHz, then this VCO 320 can vibrate with the frequency of 6GHz at least, and generates output signal, this output signal has the frequency FVCO that is at least 6GHz, for example in the scope of 6GHz to 60GHz.With the same in the synthesizer 200, the output signal that is generated by this VCO 320 is applied in feedback divider 114, and wherein this feedback divider 114 all is arranged in PLL 330 with phase-frequency detector 110, charge pump 117, loop filter 118 and VCO 320.This PLL 330 operates in the mode identical with PLL 130, but is to use the signal from the higher frequency of VCO 320.

The output signal that is generated by this VCO 320 also is applied in outgoing route 350, and this outgoing route has two branches 351 and 352.The branch 351 of this outgoing route 350 comprises output frequency divider 341.The branch 352 of this outgoing route 350 comprises output frequency divider 343.This

output frequency divider

341 and 343 is operated in known manner, is used for using respectively fixed number N1 and N2 to the output signal frequency F from VCO 320 _VCOCarry out frequency division.341 couples of frequency F of output frequency divider _VCOCarry out the used several N1 of frequency division and be different from 343 couples of frequency F of output frequency divider _VCOCarry out the used several N2 of frequency division.Number N1 and N2 depend on F _VCOValue and the value of desired output frequency.For example, work as F _VCODuring for 10GHz, N1 can for 12 and N2 can be 24, they have provided the frequency that has 10/12GHz and 10/24GHz respectively respectively, i.e. approximately 833MHz and the approximately frequency of 416MHz.To pass to the band selector 345 of operation under controller 347 controls by the signal of this

output frequency divider

341 and 343 different frequencies that generate.This band selector 345 provides to have desired frequency F from output frequency divider 341 or from the output signal of output frequency divider 343 by selecting by rights _OUTOutput signal.

In fact this controller 347 can be programmable digital signal processor.It can be combined in the single unit with controller 108.When this synthesizer 300 was used in the RF transceiver, this controller 347 can be carried out other controls and the signal processing function of this transceiver.

This synthesizer 300 has illustrated and has used a plurality of output frequency dividers to generate different output frequencies.In principle, can use a plurality of different output frequency divider of any amount.Replacedly, this outgoing route 350 can be connected with single output frequency divider.

Though describe synthesizer 300 according to the single frequency division that applies by

output frequency divider

341 and 343 above, it will be apparent to one skilled in the art that very clearly to be, can in two or more levels of series connection, carry out required frequency division.For example, can obtain on the whole 24 frequency divisions by 8 continuous frequency divisions and 3 frequency divisions.

By the frequency shift (FS) with VCO 320 is the frequency that is higher than VCO 120 far away, can further make the product of the VCO 320 of integrated circuit form, for example makes on semiconductor chip by known methods.The integrated circuit that includes VCO 320 can also comprise most of miscellaneous part of this synthesizer 300.The discrete parts that provide just normally are provided for this reference oscillator 102 and loop filter 118 and 203.In other words, can make all parts that are surrounded by dotted line 360 together with the form of integrated circuit.In some cases, this integrated circuit even can comprise loop filter 118 and/or loop filter 203.

Fig. 4 schematically describes integrated circuit 370, and comprising the parts of pointing out as dotted line among Fig. 3 360, it is shown as the zone 380 of integrated circuit 370.One or more other functions that provided by the parts in another zone 390 of integrated circuit can be provided this integrated circuit 270 alternatively.

Operate in the PLL pierce circuit of 10GHz frequency or in the optical communication industry, be widely used, and the technology that is used to produce these circuit can be applicable to suitably that use produces synthesizer 300 by the zone 380 pointed parts of integrated circuit 370 with the more multicircuit of integrated circuit form manufacturing.

By

output frequency divider

341 and 343 pairs of VCO output frequencies of output frequency divider F _VCOCarry out frequency division and significantly improved the phase noise performance of this synthesizer 300.Especially, be F with frequency _VCOSignal compare, the phase noise performance of this output signal is at frequency F _OUTBe enhanced factor 20log ₁₀(N _x), this frequency F wherein _OUTOutput signal be to have frequency F by making _VCOSignal divided by the number N _xAnd generate.For example, be approximately the output frequency of 800MHz, the phase noise performance that can access is approximately: when 10kHz is offset-120dBc, when 25kHz is offset-130dBc, 500Hz be offset time-150dBc and when 2MHz is offset approximately-170dBc.Be approximately the output frequency of 400MHz, the phase noise performance that can access is approximately: 10kHz be offset time-125dBc, when 25kHz is offset-135dBc, when 500kHz is offset-150dBc and when 2MHz is offset approximately-170dBc.

In this

synthesizer

200 and 300, this reference oscillator 102 is desired low noise oscillator, and it is in the frequency place operation of 100MHz (for example scope of 100MHz to 200MHz) at least.A kind of suitable low noise oscillator as reference-frequency oscillator 102 is exactly the product of selling with trade mark Vectron VCC1-B3B-155M52, and it produces the output reference frequency signal when 155MHz.

Fig. 5 shows the replaceable of parts that similarly uses in the synthesizer with synthesizer 200 (or synthesizer 300) and is provided with 600, has replaced comprising the setting of phase detectors 201, loop filter 203, phase rotation device 205 and VCO 120.This is provided with 600 is to replace the Alternative digital setting that employed simulation is provided with in the synthesizer 200.This is provided with 600 and comprises: the phase-frequency detector 400 that is connected with up/down (up/down) counter 402, the digital encoder 404 that is connected with this up/down counter 402 and phase rotation device 406 and the VCO 408 that is connected with this phase rotation device 406.This phase-frequency detector 400 is according to operating with the similar mode of phase-frequency detector 110 (Fig. 1).This phase-frequency detector 400 receives reference signal " REF " from reference oscillator 102 (Fig. 1), and receives feedback or variable signal " VAR " from feedback divider 114 (Fig. 1).If VAR is prior to REF, then this phase-frequency detector 400 generates " make progress " and (Up) exports pulse, and if REF prior to VAR, then generation " downwards " (Down) is exported pulse." making progress " of each generation or " downwards " pulse all have and signal VAR and REF between the proportional width of phase difference.Should " making progress " or " downwards " pulse be sent to up/down counter 402.This up/down counter 402 play in numeric field by carrying out integral function with analog domain in low pass filter similarly act on.402 pairs of " making progress " and " downwards " pulses that generated by this phase-frequency detector 400 of counter are counted, for " making progress " pulse, then this counter 402 increases progressively, and for " downwards " pulse, then this counter 402 successively decreases, and wherein each increasing or decreasing is all proportional with the pulse duration that receives.This counter 402 is output as numeric word, for example, and 16 bit words, the sum that its expression obtains by increasing or decreasing process (for given sampled signal frame).The numeric word that is produced by this counter 402 is provided for digital encoder 404, and this digital encoder 404 is translated as this numeric word can be by the digital control word of these phase rotation device 406 uses, for example 64 bit words.This phase rotation device 406 uses this numeric word to operate by according to as the mode of back with reference to Fig. 8 detailed description, to change the phase place from the output signal of VCO 408.This VCO 408 is suitable for the form of the mode that will describe with reference to Fig. 7 in the back, be used for providing output signal, in order to obtain by from the pointed suitable phase place of the output numeric word of digital encoder 404 with various phase components that this phase rotation device 406 adopts.

Fig. 6 shows the further replaceable of parts that similarly uses in the synthesizer with synthesizer 200 (or synthesizer 300) and is provided with 700, has replaced comprising the setting of phase detectors 201, loop filter 203, phase rotation device 205 and VCO 120.This is provided with 700 for numeral 600 similar half modules plan forms being set.This is provided with 700 and comprises: phase-frequency detector 500, and it is connected with charge pump 502, and next this charge pump is connected with analog loop filter 504.Transducer 506 is connected this analog loop filter 504 with A/D (mould-number), and next this analog-digital converter 506 is connected with digital encoder 508.This digital encoder 508 is connected with phase rotation device 40, and this phase rotation device is identical with phase rotation device 406 among Fig. 5.

This phase-frequency detector 500 is according to operating with the similar mode of phase-frequency detector (Fig. 1).This charge pump 502 and analog loop filter 503 are respectively according to operating with charge pump 117 and the loop filter 203 similar modes of Fig. 1.This A/D converter 506 will be converted to numeric word by the analog output signal that this analog loop filter 504 generates, and this numeric word has been delivered to digital encoder.The numeric word that this digital encoder 508 receives it is translated as can be by the digital control word of these phase rotation device 406 uses.This phase rotation device 406 according to will be in the back with reference to Fig. 8 mode in greater detail, use this digital control word to operate, in order to change the phase place of the output signal that generates by this VCO 408.

What Fig. 7 had illustrated parts in the embodiment of the invention is provided with 800, and it is provided with 600 or the more detailed form that 700 parts are set of Fig. 6 for Fig. 5's.Be provided with in 800 at this, the input signal that phase rotation device 406 receives from the combination of following item: (i) phase splitter and inverter 614 and (ii) VCO 612, they are equal to the VCO 408 shown in Fig. 5 and 6 together.This phase rotation device 406 also receives the digital coding control signal from digital encoder (for example digital encoder 404 (Fig. 5) or digital encoder 508 (Fig. 6)).This VCO 612 generates output signal according to the mode identical with VCO noted earlier 120.Output signal is divided into four component signals, and these four component signals have the 90 degree phase places of being separated by phase splitter and inverter 614 respectively.The VCO that oscillator for example produces this component signal is known as a kind of oscillator with " four phase clocks " configuration in the art.These four component signals are represented as signal psi 0 in Fig. 7, φ 90, φ 180 and φ 270.This phase splitter and inverter 614 also generate four extraneous component signals, and they equal four component signal φ 0, and φ 90, the inversion signal of each among φ 180 and the φ 270.These signals are represented as signal psi 0 _INV, φ 90 _INV, φ 180 _INVAnd φ 270 _INVLike this, this phase splitter and inverter 614 produce eight component signals altogether, are used to pass to phase rotation device 406, and wherein these eight component signals are respectively component signal φ 0, and φ 90, φ 180 and φ 270, and their inversion signal φ 0 _INV, φ 90 _INV, φ 180 _INVAnd φ 270 _INV

In fact, the output signal that this component signal φ 0 can be used as from VCO 612, and only need just can obtain component signal φ 90 by single phase change from this component signal, and then use anti-phase process to obtain other component signals.Component signal φ 180 is inversion signals of φ 0, and signal psi 270 is inversion signals of φ 90.Each component signal φ 0 _INV, φ 90 _INV, φ 180 _INVAnd φ 270 _INVAll be the component signal φ 0 that obtains, φ 90, the inversion signal of one of φ 180 and φ 270.

Can realize phase splitter and the inverter 614 of this VCO612 and Fig. 7 by it will be apparent to one skilled in the art that known multiple mode, it has adopted " four phase clocks " to add the form of inverter.For example, this VCO 612 can be configured to quadrature VCO, and it generates four desired phase component φ 0 inherently, and φ 90, φ 180 and φ 270.The out-of-phase component that generates these components also is known simple procedure, and is widely used in the circuit design, for example by using difference channel.

Replacedly, be provided with in that another kind is known, generally generate output signals (according to reference Fig. 1 with reference to VCO 120 described modes), but be twice with desired frequency by VCO 612.This signal can be transmitted through frequency divider, and wherein this frequency divider carries out frequency division by the latch that uses two triggers.Then can be in known manner, obtain needed φ 90 component signals from the terminal of joint between this latch, and can obtain φ 0 component signal from lead-out terminal in known manner.If as be known in the art such, this latch is realized that by difference channel then following also can be by anti-phase component φ 180 and the φ 270 of obtaining.

Replacedly, be provided with in that another kind is known, the output signal that is generated by this VCO 612 (according to reference Fig. 1 with reference to VCO 120 described modes) usually is transmitted through multiphase filter, wherein this multiphase filter generates the phase shift of 90 degree, that is to say, this multiphase filter generates component signal φ 90 from input signal φ 0, and then by anti-phase other required component φ 180 and φ 270 that generate.

Fig. 8 illustrates in greater detail the particular form that phase rotation device 406 can be realized in an embodiment of the present invention.The circuit of phase rotation device shown in Fig. 8 406 is the differential signal form.This is the circuit form of frequent use in the integrated circuit (IC) design, because it has strengthened the vulnerability to jamming for noise.By using conductor to generating all signals, and the value of desired signal is the voltage difference between the conductor.

This phase rotation device 406 comprises level Four, and every grade all comprises a pair of back-to-back transistor, and like this, this level Four comprises (i) transistor T 1 and T2; (ii) transistor T 3 and T4; (iii) transistor T 5 and T6; And (iv) transistor T 7 and T8.Every pair of transistor, for example, transistor T 1 and T2 have formed differential pair; In other words, the signal that puts on each differential pair is another inversion signal.Transistor T 1 to T8 shown in Fig. 8 is the field-effect transistor of NMOS (negative metal-oxide semiconductor (MOS)) form, but also can be other form known, for example bipolar form, and this it will be apparent to one skilled in the art that to be very clearly.Each transistor T 1, T3, T5 has the electrode (drain electrode) that is connected with first conductor 658 with T7, and each transistor T 2, T4, T6 has the electrode (drain electrode) that is connected with second conductor 660 with T8.Conductor 658 is V by resistance R 1 with current potential _DDPositive rail (rail) 652 be connected, and conductor 6660 is V by resistance R 2 with current potential _DD Positive rail 652 be connected.This set has been realized the function of " interpolation ", is used to add phase vectors as described below.

Each transistor T 1 to T8 is all at its grid receiving inputted signal, and wherein this input signal is in early time with reference to one of described component signal of Fig. 7.Like this, transistor T 1 received signal φ 0, transistor T 2 received signal φ 0 _INV, transistor T 3 received signal φ 90, transistor T 4 received signal φ 90 _INV, transistor T 5 received signal φ 180, transistor T 6 received signal φ 180 _INV, transistor T 7 received signal φ 270, and transistor T 8 received signal φ 270 _INV

Each transistor T 1 all be connected at its source electrode place with T2 (be shown as the NMOS form again, but also can realize) by other forms with four transistor switch SW1, SW2, SW3 and SW4 bunch (bank).This transistor switch SW1, SW2, SW3 and SW4 are as the voltage controlled current switch.Each transistor switch SW1, SW2, SW3 and SW4 all fetch by its grid is linked to each other with number bus 650 carry out voltage-controlled.

Similarly, each transistor T 3 all be connected at its source electrode place with T4 (be shown as the NMOS form again, but also can realize) by other forms with four tail current transistor switch SW 5, SW6, SW7 and SW8 bunch (bank).This transistor switch SW5, SW6, SW7 and SW8 are as the voltage controlled current switch.Each transistor switch SW5, SW6, SW7 and SW7 all fetch by its grid is linked to each other with number bus 650 carry out voltage-controlled.

Similarly, each transistor T 5 and T6 at its source electrode place all with bunch be connected (be shown as the NMOS form again, but also can realize) of four tail current transistor switch SW 9, SW10, SW11 and SW12 by other forms.This transistor switch SW9, SW10, SW11 and SW12 are as the voltage controlled current switch.Each transistor switch SW9, SW10, SW11 and SW12 all fetch by its grid is linked to each other with number bus 650 carry out voltage-controlled.

Similarly, each transistor T 7 and T8 at its source electrode place all with bunch be connected (be shown as the NMOS form again, but also can realize) of four tail current transistor switch SW 13, SW14, SW15 and SW16 by other forms.This transistor switch SW13, SW14, SW15 and SW16 are as the voltage controlled current switch.Each transistor switch SW13, SW14, SW15 and SW16 all fetch by its grid is linked to each other with digital bias bus 650 carry out voltage-controlled.

The phase rotation device 406 of Fig. 8 also comprises a series of 16 identical voltage-controlled current source transistor Ts 9 to T24 (be shown as the NMOS form again, but also can be realized by other forms).Each transistor switch SW1 to SW16 its source electrode place all with voltage-controlled current source transistor T 9 to T24 in a corresponding transistor drain be connected.Each current source transistor T9 to T24 makes its grid and bias voltage current potential V _BIASCommon analog offset line 670 be connected, and make its source ground.Because this transistor T 9 to T24 is identical, so they transport identical electric current.Each transistor switch that provides in this manner and the series connection of corresponding current source transistor thereof (for example transistor switch SW1 and current source transistor T9, or transistor switch SW2 and current source transistor T10) but the current source of switch is provided.By transmit and point to the signal of particular switch along number bus 650, control each transistor switch SW1 to SW16.These signals are that the digital encoder from control loop 230 receives, for example the digital encoder 508 among the digital encoder among Fig. 5 404 or Fig. 6.Each sort signal that is used for each switch SW 1 to SW16 all is " height " (for example 5V) or " low " (for example 0V).For example, when the signal that points to transistor switch SW7 by bus 650 when being high, this transistor switch SW7 is with conduction current.When the signal that points to transistor switch SW7 by bus 650 when low, this transistor switch SW7 will can conduction current.This transistor SW1 to SW16 is identical, and all operations in a comparable manner, promptly according to the respective signal conduction or the non-conducting electric current that receive by number bus 650.

By the selected combination of the transistor switch SW1 to SW16 that wants conducting being switched as required according to the signal that receives by number bus 650, just can revise (with difference form) as required and be transfused to the output that has desired phase place with generation in four phase places of the phase rotation device 406 of transistor T 1 to T8 each.This output is right as the differential signal on conductor shown in Fig. 8 658 and 660, i.e. signal psi OUT and its inversion signal φ OUT _INV

The phase place of signal psi 0, φ 90, φ 180 and φ 270 can be regarded as vector, can this vector be increased in the different amounts according to the combination of the transistor switch SW1 to SW16 of selected conducting.For example, the desired output phase place of supposing signal psi OUT is 225 degree.This obtains by transistor switch SW9 and SW10 and transistor switch SW13 and SW14 are switched to conducting.Other all transistor switches are off (non-conduction) all.The transistor switch of conducting, i.e. SW9 and SW10 and SW13 and SW14, provide 180 degree and 270 degree etc. " amount " phase vectors, with obtain 225 required weighted average of spending or vector with.

The phase rotation device 406 of the particular form of describing with reference to Fig. 8 has four current sources, can be used for revising the phase place at each input stage place of phase rotation device 406 in the quantization step.In fact, can use quantity, to obtain suitable small-scale quantization step more than 4.For example, every grade (input phase) 16 current sources that provided by 64 transistor switches have altogether just provided suitable phase quantization step.

It will be apparent to one skilled in the art that very clearly and be, with Fig. 1 or 3 in feedback control loop 230 similar feedback control loops in can use and with numeral 600 (comprising up/down counter and digital encoder) or half module are set and propose to put and similarly be provided with for 700 (comprising analog-digital converter and digital encoder), be used to control the digital controlled signal of VCO 130 with generation.

Synthesizer

200 and 300 among the various embodiment of the invention described above (comprising described similar type) is suitable for use in the RF transceiver, for example, and the carrier frequency signaling that is provided for transmitting or be provided for the local oscillator signals that receiver is handled.This

synthesizer

200 and 300 is specially adapted to the transceiver with high power levels emission or reception high sensitivity level.The example of high power transmitter level is exactly the output RF power of 10Watts (watt) at least, and wherein this output RF power is that radiator (antenna) at transmitter is located to measure.The example of high sensitive receiver is exactly, for π/4 difference quadrature phase shift keying (DQPSK) modulation signals, have than 3% static BER (bit error rate (BER))-the better sensitivity of 118dBm.This transceiver is applicable to the base station transceiver of mobile radio communications system, for example especially for the transceiver that uses according to the TRTRA standard.

Claims

1. RF (radio frequency) synthesizer that comprises VCO (voltage controlled oscillator), described VCO (voltage controlled oscillator) is used to the output signal with expected frequency is provided in operation, and phase-locked loop comprises: (i) described VCO; (ii) frequency divider is used to receive the output signal of described VCO in operation and is used to provide feedback signal, wherein with respect to the output signal of described VCO described feedback signal is carried out frequency division; And (iii) phase-frequency detector, be used in operation receive the described feedback signal that generates by described extra frequency divider, and the phase place of described feedback signal and the phase place and the frequency of frequency and reference signal are compared; And it is characterized in that,

(iv) be positioned at the extra control loop of described phase-locked loop inside; And

(v) phase rotation device, this phase rotation device is connected with the output of described VCO and is used for the phase error of equilibrium by the output signal of described VCO generation in operation, described extra control loop is connected with described phase rotation device, to provide control signal to described phase rotation device.

2. according to the RF synthesizer of claim 1, wherein said frequency divider is a variable frequency divider.

3. according to the RF synthesizer of claim 2, wherein said frequency divider is decimal-Fractional-N frequency device.

4. according to the RF synthesizer of any one claim of front, wherein said phase rotation device is the analog or digital phase rotation device.

5. according to the RF synthesizer of claim 4, comprise: phase splitter, be used for generating four component signals from the described output signal that generates by described VCO, the relative phase that described four component signals have 90 degree differs, wherein said phase rotation device is digit phase circulator and the phase place that is used for selecting and being offset the one or more component signals of described component signal in operation, and the selected component signal that will comprise any phase shift that applies makes up, to have generated the phase place of described phase error balanced.

6. according to the RF synthesizer of claim 5, wherein said phase rotation device comprises four levels, be used for applying respectively described four component signals and be used to make a plurality of current sources to be connected in operation with each level, wherein each current source in described a plurality of current source is optionally operated by signal from described extra control loop, be used for electric current is injected into described level, thereby the phase place of the described component signal that puts on this grade is offset.

7. according to the RF synthesizer of claim 6, wherein each grade comprises the transistor that is connected with described a plurality of current sources.

8. according to the RF synthesizer of claim 6 or 7, the described current source of wherein each comprises transistor switch.

9. RF synthesizer according to Claim 8, wherein each described current source comprises the transistor switch that is connected in series with current source transistor.

10. according to the RF synthesizer of any one claim of front, wherein said extra control loop comprises phase detectors and loop filter, described phase detectors are used to receive the described feedback signal that generated by described frequency divider in operation and the phase place of described feedback signal and the phase place of reference signal are compared, and described loop filter is used to receive the signal by described phase detectors generation in operation.

11. RF synthesizer according to claim 10, wherein said extra control loop comprises analog-digital converter and digital encoder, described analog-digital converter is used to receive the signal that is generated by described loop filter in operation, the conversion of signals that described digital encoder is used for being generated by described analog-digital converter in operation is a digital controlled signal, to put on described phase rotation device.

12. according to any one RF synthesizer among the claim 1-9, wherein said extra control loop comprises: phase-frequency detector, counter, and digital encoder, wherein said phase-frequency detector is used for the output of production burst form in operation, described counter is used for the output signal of pointing out the pulse sum counted is counted and generated in the pulse that is generated by described phase-frequency detector in operation, the output signal that described digital encoder is used for being generated by described counter in operation is converted to digital controlled signal, to put on described phase rotation device.

13. according to the RF synthesizer of any one claim of front, wherein said extra control loop has the bandwidth greater than described bandwidth of phase lock loop.

14. according to the RF synthesizer of claim 13, the bandwidth of wherein said phase-locked loop is not more than 10MHz, and the bandwidth of described extra control loop is not less than 10MHz.

15. according to the RF synthesizer of claim 14, the bandwidth range of wherein said phase-locked loop is from 2kHz to 5MHz, and the bandwidth range of described extra control loop is from 10MHz to 100MHz.

16. according to any one RF synthesizer among the claim 12-15, comprise reference oscillator, this reference oscillator is used in operation that the reference signal of 100MHz frequency passes to described phase detectors and described extra phase place with having at least.

17. according to the RF synthesizer of any one claim of front, wherein said VCO is used for vibrating at 6GHz frequency place at least in operation.

18. according to the RF synthesizer of claim 17, it is used to generate the output signal that has greater than one or more frequencies of 100MHz in operation.

19. the RF synthesizer according to any one claim of front includes integrated circuit, wherein said integrated circuit comprises at least a portion of described VCO.

20. according to the RF synthesizer of claim 19, wherein said integrated circuit also comprises at least a portion of phase-locked loop.

21. according to the RF synthesizer of claim 19 or 20, wherein said integrated circuit comprises at least a portion of described extra control loop.

22. a RF transmitter that is used for radio communication comprises the RF synthesizer according to any one claim of front.

23. a RF receiver that is used for radio communication comprises according to any one RF synthesizer among the claim 1-21 of front.

24., be applicable to the base station transceiver of mobile radio telecommunications according to the RF reflector of claim 22 or according to the RF receiver of claim 23.

25. according among the claim 1-21 any one and basically as with reference to any one or a plurality of described RF synthesizer in the accompanying drawing 2 to 9.