CN115347868B - Signal generating apparatus and signal generating method for generating low phase noise signal - Google Patents
Signal generating apparatus and signal generating method for generating low phase noise signal Download PDFInfo
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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Abstract
The application discloses a signal generating device and a signal generating method for generating low-phase noise signals, wherein the signal generating device comprises a signal preprocessing circuit, a frequency mixing phase-locked loop circuit and a signal post-processing circuit, the signal preprocessing circuit is used for carrying out frequency division or frequency multiplication processing on signals to be optimized so as to obtain preprocessed signals, the frequency mixing phase-locked loop circuit is used for carrying out loop locking on the preprocessed signals so as to obtain loop phase-locked signals, the signal post-processing circuit is used for carrying out amplification, frequency division or frequency multiplication processing on the loop phase-locked signals, and the obtained noise reduction processing signals are output as optimized signals. The frequency mixing phase-locked loop circuit is characterized in that a frequency mixer is used for building a frequency mixing loop to make up for the limitation of a decimal loop, and the stray of signals is optimized. The signal generating device is not limited by the frequency of input and output signals, can realize ultra-wideband input and output from low frequency to millimeter wave frequency band, and can be suitable for various radio frequency systems.
Description
Technical Field
The invention relates to the technical field of microwave and millimeter wave, in particular to a signal generating device and a signal generating method for generating a low-phase noise signal.
Background
In modern microwave and millimeter wave systems, phase noise is an important parameter index for transmitters and receivers. The magnitude of the phase noise can reflect the quality of the radio frequency system, and when the radio frequency system is designed and used, the influence of the phase noise on the radio frequency system needs to be noticed, and the smaller the phase noise is, the better the performance of the radio frequency system is. The phase noise of the whole radio frequency system is limited by the phase noise of the output signal of the phase-locked loop; in a mixer-pll circuit, the magnitude of the phase noise of the pll output signal is limited by the phase noise of the reference signal. Therefore, to improve the phase noise of the whole rf system, it is first necessary to generate a signal with good phase noise index.
Disclosure of Invention
The invention mainly solves the technical problem of how to generate signals with lower phase noise indexes.
According to a first aspect, the present invention provides a signal generating apparatus for generating a low phase noise signal, comprising a signal preprocessing circuit, a mixer phase-locked loop circuit, and a signal post-processing circuit;
the signal preprocessing circuit comprises a first signal connecting end and a second signal connecting end; the first signal connecting end of the signal preprocessing circuit is used as a signal input end of the signal generating device and used for inputting a preset signal to be optimized; the second signal connecting end of the signal preprocessing circuit is connected with the frequency mixing phase-locked loop circuit; the signal preprocessing circuit is used for carrying out frequency division or frequency multiplication on the signal to be optimized and sending a preprocessed signal obtained after the frequency division or frequency multiplication to the frequency mixing phase-locked loop circuit;
the frequency mixing phase-locked loop circuit comprises a first connecting end, a second connecting end, a phase discriminator, a loop filter circuit, a voltage-controlled oscillator, a power divider, a frequency mixer and a first amplifier; the first connecting end of the frequency mixing phase-locked loop circuit is connected with the second signal connecting end of the signal preprocessing circuit, the second connecting end of the frequency mixing phase-locked loop circuit is connected with the signal post-processing circuit, and the frequency mixing phase-locked loop circuit is used for carrying out loop locking on the preprocessed signal and sending a loop phase-locked signal obtained by loop locking to the signal post-processing circuit;
the phase discriminator comprises a first signal input end, a second signal input end and a first discrimination signal output end, the first signal input end of the phase discriminator is connected with the first connection end of the frequency mixing phase-locked loop circuit, the second signal input end of the phase discriminator is connected with the first amplifier, and the first discrimination signal output end of the phase discriminator is connected with the loop filter circuit;
the loop filter circuit comprises a first connecting end and a second connecting end, the first connecting end of the loop filter circuit is connected with the first discrimination signal output end of the phase discriminator, and the second connecting end of the loop filter circuit is connected with the voltage-controlled oscillator;
the voltage-controlled oscillator comprises a first connecting end and a second connecting end, the first connecting end of the voltage-controlled oscillator is connected with the second connecting end of the loop filter circuit, and the second connecting end of the voltage-controlled oscillator is connected with the power divider;
the power divider comprises a first power signal input end, a first power signal output end and a second power signal output end, the first power signal input end of the power divider is connected with the second connecting end of the voltage-controlled oscillator, the first power signal output end of the power divider is connected with the second connecting end of the frequency-mixing phase-locked loop circuit, and the second power signal output end of the power divider is connected with the frequency mixer;
the frequency mixer comprises a local oscillation signal input end, a signal to be mixed and a mixed signal output end, wherein the local oscillation signal input end of the frequency mixer is used for inputting a preset local oscillation signal, the signal to be mixed input end of the frequency mixer is connected with the second power signal output end of the power distributor, and the mixed signal output end of the frequency mixer is connected with the first amplifier;
the first amplifier comprises a first connecting end and a second connecting end, the first connecting end of the first amplifier is connected with the mixed-frequency signal output end of the frequency mixer, and the second connecting end of the first amplifier is connected with the second signal input end of the phase discriminator;
the signal post-processing circuit comprises a first signal connecting end and a second signal connecting end; the first signal connecting end of the signal post-processing circuit is connected with the second connecting end of the frequency mixing phase-locked loop circuit, and the second signal connecting end of the signal post-processing circuit is used as the signal output end of the signal generating device; the signal post-processing circuit is used for amplifying, frequency dividing or frequency doubling the loop phase-locked signal and outputting a noise reduction processing signal obtained by amplifying, frequency dividing or frequency doubling as an optimized signal.
According to a second aspect, the present invention provides a signal generating method for generating a low phase noise signal, characterized by being applied to the signal generating apparatus according to the first aspect, the signal generating method comprising:
carrying out frequency division or frequency multiplication on a signal to be optimized to obtain a preprocessed signal;
performing loop locking on the preprocessed signal to obtain a loop phase-locked signal;
and amplifying, dividing or multiplying the loop phase-locked signal, and outputting a noise reduction processing signal obtained by amplifying, dividing or multiplying the loop phase-locked signal as an optimized signal.
In the signal generating apparatus provided in the above embodiment, the mixer phase-locked loop circuit is limited by the fractional loop by using a method in which a mixer is used to build a mixer loop to compensate fractional frequency division, so as to optimize signal spurious. The signal generating device is not limited by the frequency of input and output signals, can realize ultra-wideband input and output from low frequency to millimeter wave frequency band, and can be suitable for various radio frequency systems.
Drawings
FIG. 1 is a block diagram of a signal generating apparatus according to an embodiment;
fig. 2 is a schematic flow chart of a signal generation method according to an embodiment.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments have been given like element numbers associated therewith. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of clearly describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where a certain sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" as used herein includes both direct and indirect connections (couplings), unless otherwise specified.
In the prior art, a signal generating circuit for generating a low-phase noise signal generally reduces the phase noise of the signal by using a method of building a fractional loop by fractional frequency division (see patent No. CN201410245306.3 entitled chinese patent document of a device and a method for generating a phase-discrimination reference signal with extremely low phase noise).
According to the signal generating circuit disclosed in the embodiment of the application, the frequency mixer is used for building the frequency mixing loop to make up the limitation of the decimal loop on the method for decimal frequency division, and then the stray of signals can be optimized. Meanwhile, the signal generating circuit is not limited by the frequency of input and output signals, and realizes ultra-wideband input and output from low frequency to millimeter wave frequency bands, so that the signal generating circuit can be applied to various radio frequency systems.
The first embodiment is as follows:
referring to fig. 1, a block diagram of a signal generating apparatus in an embodiment is shown, where the signal generating apparatus includes a signal preprocessing circuit 10, a mixer pll circuit 20, and a signal post-processing circuit 30. The signal preprocessing circuit 10 includes a first signal connection end and a second signal connection end, and the first signal connection end of the signal preprocessing circuit 10 is used as a signal input end of the signal generating device and is used for inputting a preset signal to be optimized. The second signal connection end of the signal preprocessing circuit 10 is connected to the mixer pll circuit 20, and the signal preprocessing circuit 10 is configured to perform frequency division or frequency multiplication on a signal to be optimized, and send a preprocessed signal obtained after the frequency division or frequency multiplication to the mixer pll circuit 20. The mixer pll circuit 20 includes a first connection terminal, a second connection terminal, a phase detector 21, a loop filter circuit 22, a voltage controlled oscillator 23, a power divider 24, a mixer 25, and a first amplifier 26. The first connection end of the frequency mixing phase-locked loop circuit 20 is connected to the second signal connection end of the signal preprocessing circuit 10, the second connection end of the frequency mixing phase-locked loop circuit is connected to the signal post-processing circuit 30, and the frequency mixing phase-locked loop circuit 20 is configured to perform loop locking on the preprocessed signal and send a loop phase-locked signal obtained by the loop locking to the signal post-processing circuit 30. The phase detector 21 comprises a first signal input end, a second signal input end and a first phase detection signal output end, the first signal input end of the phase detector 21 is connected with the first connection end of the mixing phase-locked loop circuit 20, the second signal input end of the phase detector 21 is connected with the first amplifier 26, and the first phase detection signal output end of the phase detector 21 is connected with the loop filter circuit 22. The loop filter circuit 22 includes a first connection end and a second connection end, the first connection end of the loop filter circuit 22 is connected to the first phase discriminator signal output end of the phase discriminator 21, and the second connection end of the loop filter circuit 22 is connected to the voltage-controlled oscillator 23. The voltage-controlled oscillator 23 includes a first connection end and a second connection end, the first connection end of the voltage-controlled oscillator 23 is connected to the second connection end of the loop filter circuit 22, and the second connection end of the voltage-controlled oscillator 23 is connected to the power divider 24. The power divider 24 includes a first power signal input terminal, a first power signal output terminal, and a second power signal output terminal, the first power signal input terminal of the power divider 24 is connected to the second connection terminal of the voltage-controlled oscillator 23, the first power signal output terminal of the power divider 24 is connected to the second connection terminal of the mixer pll circuit 20, and the second power signal output terminal of the power divider 24 is connected to the mixer 25. The mixer 25 includes a local oscillation signal input terminal, a signal to be mixed input terminal, and a mixed signal output terminal, the local oscillation signal input terminal of the mixer 25 is used for inputting a preset local oscillation signal, the signal to be mixed input terminal of the mixer 25 is connected with the second power signal output terminal of the power divider 24, and the mixed signal output terminal of the mixer 25 is connected with the first amplifier 26. The first amplifier 26 includes a first connection end and a second connection end, the first connection end of the first amplifier 26 is connected to the mixed-frequency signal output end of the mixer 25, and the second connection end of the first amplifier 26 is connected to the second signal input end of the phase detector 21. The signal post-processing circuit 30 includes a first signal connection end and a second signal connection end, the first signal connection end of the signal post-processing circuit 30 is connected with the second connection end of the mixer phase-locked loop circuit 20, and the second signal connection end of the signal post-processing circuit 30 is used as a signal output end of the signal generating device. The signal post-processing circuit 30 is configured to perform amplification, frequency division, or frequency multiplication on the loop phase-locked signal, and output a noise reduction processing signal obtained through the amplification, frequency division, or frequency multiplication as an optimized signal.
In one embodiment, the signal preprocessing circuit 10 includes a first switch circuit 11, a second switch circuit 14, a first programmable frequency divider 12, and a first frequency multiplier 13. The first switch circuit 11 includes a first connection end, a second connection end, a third connection end and a fourth connection end, the first connection end of the first switch circuit 11 is connected with the first signal connection end of the signal preprocessing circuit 10, the second connection end of the first switch circuit 11 is connected with the first programmable frequency divider 12, the third connection end of the first switch circuit 10 is connected with the second switch circuit 14, and the fourth connection end of the first switch circuit 11 is connected with the first frequency multiplier 13. The first switch circuit 11 is configured to output a signal to be optimized to the second switch circuit, the first programmable frequency divider 12, or the first frequency multiplier 13. The first programmable frequency divider 12 includes a first connection end and a second connection end, the first connection end of the first programmable frequency divider 12 is connected with the first connection end of the first switch circuit 11, and the second connection end of the first programmable frequency divider 12 is connected with the second switch circuit 14. The first programmable frequency divider 12 is used for frequency division processing of the signal to be optimized. The first frequency multiplier 13 includes a first connection end and a second connection end, the first connection end of the first frequency multiplier 13 is connected with the fourth connection end of the first switch circuit 11, and the second connection end of the first frequency multiplier 13 is connected with the second switch circuit 14. The first frequency multiplier 13 is configured to perform frequency multiplication on the signal to be optimized. The second switch circuit 14 includes a first connection end, a second connection end, a third connection end and a fourth connection end, the first connection end of the second switch circuit 14 is connected with the second signal connection end of the signal preprocessing circuit 10, the second connection end of the second switch circuit 14 is connected with the first programmable frequency divider 12, the third connection end of the second switch circuit 14 is connected with the first switch circuit 11, and the fourth connection end of the second switch circuit 14 is connected with the first frequency multiplier 13. The second switch circuit 14 is configured to send the signal to be optimized output by the first switch circuit 11, the signal to be optimized after frequency division processing by the first programmable frequency divider 12, or the signal to be optimized after frequency multiplication processing by the first frequency multiplier 13 to the mixer phase-locked loop circuit 20 as a pre-processed signal.
In one embodiment, the signal post-processing circuit 30 includes a third switch circuit 31, a fourth switch circuit 35, a second programmable frequency divider 32, a second amplifier 33, and a second frequency multiplier 34. The third switch circuit 31 includes a first connection end, a second connection end, a third connection end and a fourth connection end, the first connection end of the third switch circuit 31 is connected with the first signal connection end of the signal post-processing circuit 30, the second connection end of the third switch circuit 31 is connected with the second programmable frequency divider 32, the third connection end of the third switch circuit 31 is connected with the second amplifier 33, and the fourth connection end of the third switch circuit 31 is connected with the second frequency multiplier 34. The third switch circuit 31 is used to send the loop-locked signal 20 to the second programmable divider 32, the second amplifier 33, or the second frequency multiplier 34. The second programmable frequency divider 32 includes a first connection end and a second connection end, the first connection end of the second programmable frequency divider 32 is connected with the second connection end of the third switch circuit 31, and the second connection end of the second programmable frequency divider 32 is connected with the fourth switch circuit 35. The second amplifier 33 includes a first connection terminal and a second connection terminal, the first connection terminal of the second amplifier 33 is connected to the third connection terminal of the third switch circuit 31, and the second connection terminal of the second amplifier 33 is connected to the fourth switch circuit 35. The second frequency multiplier 34 includes a first connection end and a second connection end, the first connection end of the second frequency multiplier 34 is connected with the fourth connection end of the third change-over switch circuit 31, and the second connection end of the second frequency multiplier 34 is connected with the fourth change-over switch circuit 35. The fourth switch circuit 35 includes a first connection end, a second connection end, a third connection end and a fourth connection end, the first connection end of the fourth switch circuit 35 is connected to the second signal connection end of the signal post-processing circuit 30, the second connection end of the fourth switch circuit 35 is connected to the second programmable frequency divider 32, the third connection end of the fourth switch circuit 35 is connected to the second amplifier 33, and the fourth connection end of the fourth switch circuit is connected to the second frequency multiplier 34. The fourth switch circuit 35 is configured to output the loop phase-locked signal subjected to frequency division processing by the second programmable frequency divider 32, the loop phase-locked signal amplified by the second amplifier 33, or the loop phase-locked signal subjected to frequency multiplication processing by the second frequency multiplier 34 as an optimized signal.
In one embodiment, the first switch circuit 11, the second switch circuit 14, the third switch circuit 31 and the fourth switch circuit 35 are one-out-of-three signal switch circuits. In one embodiment, the local oscillator signal is generated by a comb generator circuit or comb generator. In one embodiment, the first programmable divider 12 and the second programmable divider 32 employ fractional division mode and/or employ integer division mode. In one embodiment, the output of the first phase detection signal output terminal of the phase detector 21 is a square wave signal. In one embodiment, the phase detection frequency of the phase detector is 50MHz.
In this application embodiment, a signal to be optimized is divided into three paths by a first change-over switch circuit, a signal higher than a phase detection frequency range of a phase detector is subjected to frequency division by a first programmable frequency divider and then sent to the phase detector by a second change-over switch circuit, a signal lower than the phase detection range of the phase detector is subjected to frequency multiplication by the first frequency multiplier and then sent to the phase detector by the second change-over switch circuit, and a signal in the phase detection frequency range of the phase detector is directly sent to the phase detector by the second change-over switch circuit. The phase detector (PFD) is connected with a Loop Filter (LF) and a Voltage Controlled Oscillator (VCO) in sequence, the voltage controlled oscillator is connected with a power divider in sequence, the power divider has two paths of outputs, one path of output is supplied to the mixer and is used as an RF signal input, and the mixed intermediate frequency signal is subjected to phase discrimination with a preprocessing signal through a first amplifier; one path is sent to the third change-over switch circuit and is used as an output signal of the signal generating device after being processed by the post-processing circuit. The first type is directly output by the fourth change-over switch circuit after being amplified by the second amplifier, the second type is directly output by the fourth change-over switch circuit after being subjected to frequency division processing by the second programmable frequency divider, and the third type is directly output by the fourth change-over switch circuit after being subjected to frequency multiplication processing by the second frequency multiplier.
In an embodiment, the local oscillation signal LO of the mixer is generated by a comb generation circuit or a comb generator, and is obtained by frequency-selective filtering, and a local oscillation signal with a lower phase noise level can be obtained, where if the input of the comb generation circuit or the comb generator is 50MHz, the obtained local oscillation signal is (50 × N) MHz (N is the order of the comb generation circuit or the comb generator, and is a positive integer); the step recovery diode can be used for building, and can also be realized by an integrated chip. The RF end of the RF signal of the mixer is generated by a Voltage Controlled Oscillator (VCO) and obtained through a power divider, and the generated IF signal is phase-discriminated from the preprocessed signal through an amplifier 1. Namely, the method comprises the following steps:
the preprocessed signal can be expressed as:
REF=IF=LO±VCO。
different comb wave generation circuits or comb wave generators are selected to generate local oscillation signals according to actual use conditions, and different reference signal phase noise and stray can be optimized. The local oscillator signal of the mixer is generated by a comb wave generating circuit and/or a comb wave generator, and the comb wave generating circuit is not a protection point of the invention, and therefore, the details are not described herein. According to the phase noise theory:
ideal frequency multipliers and frequency dividers. Multiplying the frequency of a signal by a factor of N using an ideal frequency multiplier increases the phase noise of the multiplied signal by 20lg (N) dB. Similarly, dividing the signal frequency by N may reduce the phase noise of the output signal by 20lg (N) dB.
From this theory it can be deduced that:
for a frequency modulated signal:
f(t) = cos(ωct + βsin(ωmt))；
after N frequency doubling, the method comprises the following steps:
f(t) = cos(Nωct + Nβsin(ωmt))；
the amplitude of the signal sideband after N times of frequency multiplication is increased by N times, namely increased by 20lg (N) dB. In the frequency multiplied signal, the sideband offset from the carrier is the same as the original signal.
After N frequency division, the method comprises the following steps:
f(t) = cos((ωc/N)t +(β/N)sin(ωmt))；
the amplitude of the signal sideband after N frequency division is reduced by N times, namely 20lg (N) dB. In the frequency-divided signal, the sideband offset from the carrier is the same as the original signal.
According to the theory, the devices such as the switch switching circuit, the phase discriminator, the loop filter, the voltage-controlled oscillator, the power divider, the mixer, the amplifier and the like can not deteriorate the phase noise; one signal is divided by N and its phase noise is reduced by 20lg (N) dB. The optimized phase-to-noise ratio is 20lg (N) dBc/Hz lower than the phase-to-noise ratio to be optimized.
And the sideband amplitude is reduced by 20lg (N) dB for the spurious signal, and the frequency offset is the same as the original signal.
Therefore, the mixer is used in the mixing phase-locked loop circuit to reduce the output frequency of the VCO to the frequency required by the PFD through a mixing mode, so that the phase-locked loop circuit can be obtained, and the phase-locked loop circuit can output various required frequency ranges without changing the phase noise and the stray of signals.
Fig. 2 is a schematic flow chart of a signal generation method in an embodiment, which is applied to the signal generation apparatus for generating a low phase noise signal. The signal generating method comprises the following steps:
And performing frequency division or frequency multiplication on the signal to be optimized to obtain a preprocessed signal.
And carrying out loop locking on the preprocessed signal to obtain a loop phase-locked signal. In one embodiment, the pll phase-locked signal is a square wave signal converted by a sine wave.
And step 300, outputting the optimized signal.
And amplifying, dividing or multiplying the loop phase-locked signal, and outputting a noise reduction processing signal obtained by amplifying, dividing or multiplying the loop phase-locked signal as an optimized signal.
The following describes technical effects of the signal generating device disclosed in the present application through specific application examples, which specifically include:
setting the output range of a voltage controlled oscillator VCO to be 1-2G; the phase discriminator generally adopts square waves and low frequency to discriminate the phase in order to obtain the best phase noise, and the phase discriminator has the phase discrimination frequency range of 10M-1300M; the local oscillation signals are generated by a comb wave generator according to different use scenes and are obtained by frequency selection and filtering.
For example, one: setting the phase discrimination frequency to be 50M, the signal to be optimized to be 2000MHz, the phase noise at the offset of 100KHz to be-130 dBc/Hz, carrying out frequency division by a first programmable frequency divider, the frequency division ratio to be 2000M/50M =40, optimizing the phase noise at the position by 20lg40dB, namely optimizing 32dB, setting the signal reaching the phase discriminator to be 50M, the phase noise at the offset of 100KHz to be-162 dBc/Hz, outputting a signal to be 2000MHz by the VCO, outputting the signal to be-162 dBc/Hz by the offset of 100KHz, outputting the signal by a second amplifier, optimizing the phase noise of the signal by 32dB compared with the input signal of 2000MHz and the phase noise at the offset of 100KHz to be-130 dBc/Hz, and optimizing the stray by 32dB.
Example two: setting the phase discrimination frequency to be 50M; the phase noise at the position deviated from 100KHz is-135 dBc/Hz, the frequency multiplication needs to be carried out through a first frequency multiplier, the frequency multiplication ratio is 50M/1M =50, the phase noise at the position deviated from 100KHz is deteriorated by 20lg50dB, namely deteriorated by 34dB, the signal reaching the phase discriminator is 50M, the phase noise at the position deviated from 100KHz is-101 dBc/Hz, the signal output by the VCO is 1000MHz, the phase noise at the position deviated from 100KHz is-101 dBc/Hz, the signal is output by a second programmable frequency divider at the moment, the frequency division ratio is 1000M/1M =1000, the phase noise of the signal is optimized by 20lg1000dB, namely optimized by 60dB, the output signal at the moment is 1MHz, the phase noise at the position deviated from 100KHz is-161 dBc/Hz, and the phase noise at the position deviated from 100KHz is-135 dBc/Hz relative to the input signal to be optimized by 1MHz, and 26dB is optimized; also the spurs are optimized 26dB.
Example three: setting the phase discrimination frequency to be 50M; the input signal is 50MHz, the phase noise at the offset of 100KHz is-135 dBc/Hz, the input signal directly enters the phase discriminator to discriminate, the signal reaching the phase discriminator is 50M, the phase noise at the offset of 100KHz is-135 dBc/Hz, the output signal through the VCO is 2000MHz, the phase noise at the offset of 100KHz is-135 dBc/Hz, the output signal at the time is output through the programmable frequency divider 2, the frequency dividing ratio is 2000M/50M =40, the phase noise of the signal is optimized to 2lg40 dB, namely, 32dB is optimized, the output signal at the time is 50M, the phase noise at the offset of 100KHz is-167 dBc/Hz, the phase noise at the offset of 100KHz is-135 dBc/Hz relative to the input signal of 50MHz, and the phase noise at the offset of 100KHz is-135 dBc/Hz, so that 32dB is optimized; also the spurs are optimized 32dB.
In the above example, the first programmable frequency divider and the second programmable frequency divider both work in an integer mode, and input and output frequency points are the same, and in this mode, the programmable frequency divider has no fractional frequency division spur, but the obtained frequency points are relatively fixed; if any output frequency point is desired, two methods are provided, one is a decimal frequency division mode adopting a programmable frequency divider, decimal frequency division stray can be introduced in the decimal frequency division mode, and the method can be used if the decimal frequency division stray can be accepted; the other method is that a series of input and output frequency points can be designed to cover the required frequency points by adopting the method of different input and output frequency points and adopting the programmable frequency divider to divide frequency by integers, and the signal obtained by the method has better stray.
The signal generation device disclosed in the embodiment of the application comprises a signal preprocessing circuit, a frequency mixing phase-locked loop circuit and a signal post-processing circuit, wherein the signal preprocessing circuit is used for performing frequency division or frequency multiplication on a signal to be optimized to obtain a preprocessed signal, the frequency mixing phase-locked loop circuit is used for performing loop locking on the preprocessed signal to obtain a loop phase-locked signal, and the signal post-processing circuit is used for performing amplification, frequency division or frequency multiplication on the loop phase-locked signal and outputting the obtained noise reduction processed signal as an optimized signal. The frequency mixing phase-locked loop circuit is characterized in that a frequency mixer is used for building a frequency mixing loop to make up for the limitation of a decimal loop, and the stray of signals is optimized. The signal generating device is not limited by the frequency of input and output signals, can realize ultra-wideband input and output from low frequency to millimeter wave frequency band, and can be suitable for various radio frequency systems.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.
Claims (10)
1. A signal generating device for generating a low phase noise signal, comprising a signal preprocessing circuit, a mixing phase-locked loop circuit and a signal post-processing circuit;
the signal preprocessing circuit comprises a first signal connecting end and a second signal connecting end; the first signal connecting end of the signal preprocessing circuit is used as a signal input end of the signal generating device and used for inputting a preset signal to be optimized; the second signal connecting end of the signal preprocessing circuit is connected with the frequency mixing phase-locked loop circuit; the signal preprocessing circuit is used for carrying out frequency division or frequency multiplication processing on the signal to be optimized and sending a preprocessed signal obtained after the frequency division or frequency multiplication processing to the frequency mixing phase-locked loop circuit;
the frequency mixing phase-locked loop circuit comprises a first connecting end, a second connecting end, a phase discriminator, a loop filter circuit, a voltage-controlled oscillator, a power divider, a frequency mixer and a first amplifier; the first connecting end of the frequency mixing phase-locked loop circuit is connected with the second signal connecting end of the signal preprocessing circuit, the second connecting end of the frequency mixing phase-locked loop circuit is connected with the signal post-processing circuit, and the frequency mixing phase-locked loop circuit is used for carrying out loop locking on the preprocessed signal and sending a loop phase-locked signal obtained by loop locking to the signal post-processing circuit;
the phase discriminator comprises a first signal input end, a second signal input end and a first discrimination signal output end, the first signal input end of the phase discriminator is connected with the first connection end of the frequency mixing phase-locked loop circuit, the second signal input end of the phase discriminator is connected with the first amplifier, and the first discrimination signal output end of the phase discriminator is connected with the loop filter circuit;
the loop filter circuit comprises a first connecting end and a second connecting end, the first connecting end of the loop filter circuit is connected with the first phase discriminator signal output end of the phase discriminator, and the second connecting end of the loop filter circuit is connected with the voltage-controlled oscillator;
the voltage-controlled oscillator comprises a first connecting end and a second connecting end, the first connecting end of the voltage-controlled oscillator is connected with the second connecting end of the loop filter circuit, and the second connecting end of the voltage-controlled oscillator is connected with the power divider;
the power divider comprises a first power signal input end, a first power signal output end and a second power signal output end, the first power signal input end of the power divider is connected with the second connecting end of the voltage-controlled oscillator, the first power signal output end of the power divider is connected with the second connecting end of the frequency mixing phase-locked loop circuit, and the second power signal output end of the power divider is connected with the frequency mixer;
the frequency mixer comprises a local oscillation signal input end, a signal to be mixed and a mixed signal output end, wherein the local oscillation signal input end of the frequency mixer is used for inputting a preset local oscillation signal, the signal to be mixed input end of the frequency mixer is connected with the second power signal output end of the power distributor, and the mixed signal output end of the frequency mixer is connected with the first amplifier;
the first amplifier comprises a first connecting end and a second connecting end, the first connecting end of the first amplifier is connected with the mixed-frequency signal output end of the frequency mixer, and the second connecting end of the first amplifier is connected with the second signal input end of the phase discriminator;
the signal post-processing circuit comprises a first signal connecting end and a second signal connecting end; the first signal connecting end of the signal post-processing circuit is connected with the second connecting end of the frequency mixing phase-locked loop circuit, and the second signal connecting end of the signal post-processing circuit is used as the signal output end of the signal generating device; the signal post-processing circuit is used for amplifying, frequency dividing or frequency doubling the loop phase-locked signal and outputting a noise reduction processing signal obtained by amplifying, frequency dividing or frequency doubling as an optimized signal.
2. The signal generating apparatus of claim 1, wherein the signal preprocessing circuit comprises a first switch circuit, a second switch circuit, a first programmable frequency divider, and a first frequency multiplier;
the first change-over switch circuit comprises a first connecting end, a second connecting end, a third connecting end and a fourth connecting end, the first connecting end of the first change-over switch circuit is connected with the first signal connecting end of the signal preprocessing circuit, the second connecting end of the first change-over switch circuit is connected with the first programmable frequency divider, and the third connecting end of the first change-over switch circuit is connected with the second change-over switch circuit; a fourth connecting end of the first change-over switch circuit is connected with the first frequency multiplier; the first change-over switch circuit is used for outputting the signal to be optimized to the second change-over switch circuit, the first programmable frequency divider or the first frequency multiplier;
the first programmable frequency divider comprises a first connecting end and a second connecting end, the first connecting end of the first programmable frequency divider is connected with the first connecting end of the first change-over switch circuit, and the second connecting end of the first programmable frequency divider is connected with the second change-over switch circuit; the first programmable frequency divider is used for carrying out frequency division processing on the signal to be optimized;
the first frequency multiplier comprises a first connecting end and a second connecting end, the first connecting end of the first frequency multiplier is connected with the fourth connecting end of the first change-over switch circuit, and the second connecting end of the first frequency multiplier is connected with the second change-over switch circuit; the first frequency multiplier is used for carrying out frequency multiplication processing on the signal to be optimized;
the second change-over switch circuit comprises a first connecting end, a second connecting end, a third connecting end and a fourth connecting end, the first connecting end of the second change-over switch circuit is connected with the second signal connecting end of the signal preprocessing circuit, the second connecting end of the second change-over switch circuit is connected with the first programmable frequency divider, and the third connecting end of the second change-over switch circuit is connected with the first change-over switch circuit; a fourth connecting end of the second change-over switch circuit is connected with the first frequency multiplier; the second switch circuit is used for sending the signal to be optimized output by the first switch circuit, the signal to be optimized after frequency division processing by the first programmable frequency divider or the signal to be optimized after frequency multiplication processing by the first frequency multiplier to the frequency mixing phase-locked loop circuit as the preprocessing signal.
3. The signal generating apparatus of claim 2, wherein the signal post-processing circuit comprises a third switch circuit, a fourth switch circuit, a second programmable divider, a second amplifier, and a second frequency multiplier;
the third change-over switch circuit comprises a first connecting end, a second connecting end, a third connecting end and a fourth connecting end, the first connecting end of the third change-over switch circuit is connected with the first signal connecting end of the signal post-processing circuit, the second connecting end of the third change-over switch circuit is connected with the second programmable frequency divider, the third connecting end of the third change-over switch circuit is connected with the second amplifier, and the fourth connecting end of the third change-over switch circuit is connected with the second frequency multiplier; the third switch circuit is configured to send the loop lock signal to the second programmable frequency divider, the second amplifier, or the second frequency multiplier;
the second programmable frequency divider comprises a first connecting end and a second connecting end, the first connecting end of the second programmable frequency divider is connected with the second connecting end of the third change-over switch circuit, and the second connecting end of the second programmable frequency divider is connected with the fourth change-over switch circuit;
the second amplifier comprises a first connecting end and a second connecting end, the first connecting end of the second amplifier is connected with the third connecting end of the third change-over switch circuit, and the second connecting end of the second amplifier is connected with the fourth change-over switch circuit;
the second frequency multiplier comprises a first connecting end and a second connecting end, the first connecting end of the second frequency multiplier is connected with the fourth connecting end of the third change-over switch circuit, and the second connecting end of the second frequency multiplier is connected with the fourth change-over switch circuit;
the fourth switch circuit comprises a first connecting end, a second connecting end, a third connecting end and a fourth connecting end, the first connecting end of the fourth switch circuit is connected with the second signal connecting end of the signal post-processing circuit, the second connecting end of the fourth switch circuit is connected with the second programmable frequency divider, the third connecting end of the fourth switch circuit is connected with the second amplifier, and the fourth connecting end of the fourth switch circuit is connected with the second frequency multiplier; the fourth switch circuit is configured to output the loop phase-locked signal subjected to frequency division processing by the second programmable frequency divider, the loop phase-locked signal amplified by the second amplifier, or the loop phase-locked signal subjected to frequency multiplication processing by the second frequency multiplier as the optimized signal.
4. The signal generating apparatus of claim 3, wherein the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit are one-of-three signal switch circuits.
5. A signal generation apparatus according to claim 3, wherein the local oscillator signal is generated by a comb generation circuit or a comb generator.
6. The signal generating apparatus of claim 3, wherein the first programmable divider and the second programmable divider employ a fractional division mode and/or employ an integer division mode.
7. The signal generating apparatus as claimed in claim 3, wherein the output of the first phase detector signal output terminal is a square wave signal.
8. The signal generating apparatus of claim 7, wherein the phase detection frequency of the phase detector is 50MHz.
9. A signal generation method for generating a low phase noise signal, applied to the signal generation apparatus according to any one of claims 1 to 8, the signal generation method comprising:
carrying out frequency division or frequency multiplication on a signal to be optimized to obtain a preprocessed signal;
performing loop locking on the preprocessed signal to obtain a loop phase-locked signal;
and amplifying, dividing or multiplying the loop phase-locked signal, and outputting a noise reduction processing signal obtained by amplifying, dividing or multiplying the loop phase-locked signal as an optimized signal.
10. The signal generating method of claim 9, wherein the loop phase lock signal is a square wave signal.
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| CN202211282959.XA CN115347868B (en) | 2022-10-20 | 2022-10-20 | Signal generating apparatus and signal generating method for generating low phase noise signal |
| PCT/CN2023/089468 WO2024082586A1 (en) | 2022-10-20 | 2023-04-20 | Signal generation apparatus and method for generating low-phase noise signal |
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| CN202211282959.XA CN115347868B (en) | 2022-10-20 | 2022-10-20 | Signal generating apparatus and signal generating method for generating low phase noise signal |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000078003A (en) * | 1998-08-28 | 2000-03-14 | Seiko Epson Corp | Pll circuit |
| US6405022B1 (en) * | 2000-05-17 | 2002-06-11 | Intersil Americas Inc. | Apparatus for radio frequency processing with single oscillator for intermediate frequency processing |
| CN207939498U (en) * | 2018-07-16 | 2018-10-02 | 成都仁健微波技术有限公司 | A kind of Low phase noise frequency synthesizer |
| CN113422604A (en) * | 2021-08-24 | 2021-09-21 | 深圳市鼎阳科技股份有限公司 | Frequency synthesizer |
| CN113541678A (en) * | 2020-04-16 | 2021-10-22 | 颜佳 | Double-loop mixing phase-locking circuit, device and phase-locking method |
| CN114070302A (en) * | 2022-01-17 | 2022-02-18 | 中国电子科技集团公司第二十九研究所 | Broadband fine stepping frequency synthesis circuit and method |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1624576A1 (en) * | 2004-08-02 | 2006-02-08 | Digital Multimedia Technologies S.P.A. | A PLL based frequency synthesizer having a frequency mixer in the feedback branch |
| CN105071804B (en) * | 2015-07-23 | 2018-04-10 | 中国电子科技集团公司第四十一研究所 | A kind of Low phase noise broadband microwave local oscillator source circuit and its implementation method |
| CN106385255B (en) * | 2016-08-17 | 2019-07-26 | 中国电子科技集团公司第四十一研究所 | A kind of polycyclic apparatus for frequency synthesizing that low noise high-resolution is tunable and method |
| CN112485768B (en) * | 2020-11-16 | 2023-07-21 | 西安电子工程研究所 | High-precision continuous wave speed measuring radar echo simulation method based on frequency division and multiplication mode |
| CN115347868B (en) * | 2022-10-20 | 2022-12-13 | 深圳市鼎阳科技股份有限公司 | Signal generating apparatus and signal generating method for generating low phase noise signal |
-
2022
- 2022-10-20 CN CN202211282959.XA patent/CN115347868B/en active Active
-
2023
- 2023-04-20 WO PCT/CN2023/089468 patent/WO2024082586A1/en unknown
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000078003A (en) * | 1998-08-28 | 2000-03-14 | Seiko Epson Corp | Pll circuit |
| US6405022B1 (en) * | 2000-05-17 | 2002-06-11 | Intersil Americas Inc. | Apparatus for radio frequency processing with single oscillator for intermediate frequency processing |
| CN207939498U (en) * | 2018-07-16 | 2018-10-02 | 成都仁健微波技术有限公司 | A kind of Low phase noise frequency synthesizer |
| CN113541678A (en) * | 2020-04-16 | 2021-10-22 | 颜佳 | Double-loop mixing phase-locking circuit, device and phase-locking method |
| CN113422604A (en) * | 2021-08-24 | 2021-09-21 | 深圳市鼎阳科技股份有限公司 | Frequency synthesizer |
| CN114070302A (en) * | 2022-01-17 | 2022-02-18 | 中国电子科技集团公司第二十九研究所 | Broadband fine stepping frequency synthesis circuit and method |
Non-Patent Citations (1)
| Title |
|---|
| 用混频环单元实现某分析接收机的二本振信号;陈家松等;《船舶电子工程》;20050228(第2期);第118-120页 * |
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