WO2007030358A2

WO2007030358A2 - Rf synthesizer and rf transmitter or receiver incorporating the synthesizer

Info

Publication number: WO2007030358A2
Application number: PCT/US2006/033611
Authority: WO
Inventors: Soren Peter Larsen; Jacob Tranegaard Hansen
Original assignee: Motorola Inc.
Priority date: 2005-09-08
Filing date: 2006-08-25
Publication date: 2007-03-15
Also published as: GB2430090A; WO2007030358A3; CN101421927A; EP1929676A2; GB2430090B; EP1929676A4; GB0518215D0

Abstract

An RF (radio frequency) synthesizer (200) includes a VCO (voltage controlled oscillator) (120) operable to provide an output signal at a desired frequency, a phase locked loop (130) including (i) the VCO; (ii) a frequency divider (114) operable to receive an output signal of the VCO and to provide a feedback signal which is divided in frequency relative to the output signal of the VCO; and (iii) a phase frequency detector (110) operable to receive the feedback signal produced by the VCO and to compare a phase and frequency of the feedback signal with the phase and frequency of a reference signal; and is characterised by (iv) a further control loop (230) inside the phase locked loop (130); and (v) a phase rotator (205) connected to an output of the VCO and operable to equalise a phase error of an output signal produced by the VCO, the further control loop being connected to the phase rotator to provide a control signal to the phase rotator. The synthesizer may beneficially include an integrated circuit which incorporates at least part of the VCO, the phase locked loop and the further control loop. Also described is a RF transmitter or receiver, e.g. for use in a base transceiver station, which incorporates the synthesizer.

Description

TITLE: RF SYNTHESIZER AND RF TRANSMITTER OR RECEIVER INCORPORATING THE SYNTHESIZER

FIELD OF THE INVENTION

The present invention relates to an RF (radio frequency) synthesizer and an RF transmitter or receiver incorporating the RF synthesizer. In particular, the invention relates to an RF synthesizer which incorporates a VCO (voltage controlled oscillator) useful in a wireless transmitter or receiver for generating a stable RF signal.

BACKGROUND OF THE INVENTION

Carrier frequency signals in RF communications transmitters are conventionally generated by a frequency synthesizer including a VCO connected in a phase locked loop (PLL). The phase locked loop, including the VCO, provides an appropriate stable output signal at a precisely defined frequency. The VCO usually employs a resonator portion which provides oscillations in a given frequency band which includes the output signal frequency, a tuning portion, e.g. employing one or more voltage controlled devices such as varactors, which provides tuning of the output frequency in accordance with an input control voltage and an amplifier or active portion.

RF synthesizers may also be used in RF receivers to provide accurate reference (local oscillator) frequency signals. In many cases, the receiver and transmitter are combined in a single transceiver unit. In the prior art, synthesizers based upon VCOs in a phase locked loop have employed a frequency divider to provide suitable feedback in the phase locked loop. In many cases these frequency dividers are variable dividers, i.e. they divide the feedback signal from the VCO by a variable divisor number. An example of such a divider is a so called 'fractional-N' divider. Use of such frequency dividers, particularly variable dividers, is known to generate undesirable spurious peaks in the output spectrum of the VCO. The problem of these spurious peaks is worsened as the VCO operating frequency increases. Various arrangements are known in the prior art which aim to solve the problem of undesirable spurious peaks mentioned above. Examples are described in US-A-6,642,800, US-A- 6,515,525, WO-A-2004/100380 and WO-2002/058243. However, the solution provided by the present invention and benefits obtained thereby are not contemplated in the prior art.

SUMMARY OF THE INVENTION

According to the present invention in a first aspect there is provided a RF synthesizer as defined in claim 1 of the accompanying claims.

According to the present invention in a second aspect there is provided a RF transmitter as defined in claim 22 of the accompanying claims.

According to the present invention in a third aspect there is provided a RF transmitter as defined in claim 23 of the accompanying claims.

Further features of the invention are defined in the accompanying dependent claims and are disclosed in the embodiments of the invention to be described.

By the invention, a synthesizer is provided in which the problem, obtained in the prior art as described earlier, of spurious undesirable peaks produced by frequency division to provide feedback in a phase locked loop, especially by a variable divider such as a fractional-N divider, is solved in a novel way. A further control loop is provided to measure a phase error in an output signal from the VCO of the synthesizer caused by the spurious peak and a phase rotator is provided to change a phase of the output signal from the VCO to correct for (equalize) the measured phase error. At least part of the VCO of the novel synthesizer may beneficially be provided in the form of an integrated circuit, e.g. a semiconductor chip, which may also include at least part of the PLL circuitry. This is not practicable to achieve in the prior art for output frequencies of, say, less than 1 GHz, as the phase noise performance of the synthesizer in this form at these frequencies is not satisfactory. Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which: BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block circuit illustrating a frequency synthesizer in accordance with an embodiment of the present invention. FIG. 2 schematically depicts an integrated circuit which includes the components of the synthesizer of FIG. 2 in an area of the integrated circuit.

FIG. 3 is a schematic block circuit illustrating a frequency synthesizer in accordance with a further embodiment of the present invention.

FIG. 4 schematically depicts an integrated circuit which includes the components of the synthesizer of FIG. 3 in an area of the integrated circuit.

FIG. 5 is a block schematic diagram illustrating an alternative arrangement of components for use in the synthesizer of FIG. 1.

FIG. 6 is a block schematic diagram illustrating a further alternative arrangement of components for use in the synthesizer of FIG. 1. FIG. 7 is a block schematic diagram showing in more detail part of the arrangement of FIG. 5.

FIG. 8 is a schematic circuit diagram of a phase rotator suitable for use in the synthesizer of FIG. 1 when incorporating the arrangement of FIGS. 5 and 7.

DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Reference is now made to FIG. 1, which is a schematic block circuit illustration of a frequency synthesizer, generally referenced as 200, embodying the invention. The frequency synthesizer 200 includes a reference oscillator 102, e.g. a crystal oscillator, a controller 108, a phase frequency detector 110, a charge pump 117, a loop filter 118, a VCO 120 and a feedback frequency divider 114. The VCO 120 includes as constituent parts a VCO tuning and resonating block or portion 112 and a VCO active block or portion 116. The reference oscillator 102 is connected to the phase frequency detector 110. The feedback frequency divider 114 is connected to the phase frequency detector 110, the controller 108 and the VCO active block 116. The charge pump 117 is connected to the phase frequency detector 110 and the loop filter 118. The loop filter 118 is connected to the VCO tuning and resonating block 112 as well as the charge pump 117. The VCO active block 116 is connected to the VCO tuning and resonating block 112 and to the feedback frequency divider 114. The loop including the VCO 120, the divider 114, the phase frequency detector 110, the charge pump 117 and the loop filter 118 forms a PLL (phase locked loop) 130. The reference oscillator 102 provides a reference signal to the phase frequency detector 110. The feedback frequency divider 114 receives a feedback signal, having a frequency F_OU_T, as an output from the VCO active block 116. The feedback frequency divider 114 divides the frequency of this signal by a divisor number M and provides a resultant signal, having the frequency Fouτ/M, to the phase frequency detector 110. The phase frequency detector 110 compares the respective phase and frequency of the reference and feedback signals it receives and generates an output control signal in response. Typically, the phase frequency detector 110 operates as follows. The phase frequency detector 110 receives two input signals and can produce one of two possible (alternative) output signals. The input signals are the (variable) reference signal from the reference oscillator 102 and the feedback signal from the feedback frequency divider 114. The two possible output signals are in the form of pulses of two types, i.e. a first type of pulse and a second type of pulse, e.g. known respectively as 'Up' and 'Down' pulses, of variable width. When the reference signal is leading the feedback signal because the frequency of the feedback signal is less than that of the reference signal, the phase frequency detector 110 produces a pulse of the first type, e.g. an 'Up' pulse, to indicate this leading by the reference signal. Conversely, when the reference signal is lagging the feedback signal because the frequency of the feedback signal is greater than that of the reference signal, the phase frequency detector 110 produces a pulse of the second type, e.g. a 'Down' pulse, to indicate this lagging. The pulse width of both the first type of pulse and the second type of pulse is proportional to the phase difference detected between the reference signal and the feedback signal, (thereby causing the phase frequency detector 110 to provide a linear phase difference response). The detection of frequency difference as well as phase difference between the two inputs to the phase frequency detector 110 is provided by the phase frequency detector 110 for example to allow for correction of the frequency difference that occurs when starting up the PLL 130 or when switching channel frequency of the PLL 130, e.g. when the PLL 130 is used in a radio transmitter, e.g. by changing the value of the number M referred to above.

The phase frequency detector 110 includes an amplifier (not shown) which amplifies the signal provided as an output control signal (a pulse of the first or second type described above, as appropriate). The phase frequency detector 110 provides its output control signal to the charge pump 117 and the loop filter 118. If the charge pump 117 receives a pulse of the first kind from the phase frequency detector 110, it drives current into the loop filter 118. If the charge pump 117 receives a pulse of the second kind from the phase frequency detector 110, it draws current out of the loop filter 118. The loop filter 118, adjusted in this manner by the charge pump 117, converts the signal from the phase frequency detector 110 comprising a series of pulses into a resultant output control voltage V_OUT which is applied as an adjustable bias voltage to the VCO tuning and resonating block 112.

Depending on the value of the output control voltage V_OU_T it receives, the VCO tuning and resonating block 112 adjusts an output frequency F_OUT of a signal it produces to be equal to a desired value. When the PLL 130 becomes stable, the value of V_OU_T is related to the values of the divisor number M and the frequency of the reference signal provided by the reference oscillator 102. The values of these parameters are therefore selected in design of the synthesizer 200 to give a desired output frequency F_OUT- The VCO active block 116 amplifies the signal of frequency FOUT produced by the VCO tuning and resonating block 112 and provides it as an output signal having a frequency F_OU_T to an output path 150 as well as to the feedback frequency divider 114 in the PLL 130.

The loop filter 118 in the synthesizer 100 also filters out jitter, e.g. caused by noise of the charge pump 117, and prevents voltage overshoot.

The controller 108 in the synthesizer 100 provides control of the value of the divisor number M and thereby provides adjustment of the value of V_OU_T. In one form of the feedback frequency divider 114, the divider 114 may be a variable divider. In this form, the value of M may be varied by rapid switching by the controller 108 according to a pre-defined switching program between a first integer N and a second integer, e.g. N+l. This has the effect of providing an average value of M equal to a value between N and the second integer. In the case where the switching is between successive integers N and N+l, the variable feedback frequency divider is known in the art as a 'fractional-N' divider.

The controller 108 may in practice be a programmed digital signal processor. Where the synthesizer 100 is employed in a RF transceiver the controller 108 may perform other control and signal processing functions of the transceiver.

The synthesizer 200 includes a further control loop 230 inside the PLL 130. The further control loop 230 includes a phase detector 201 connected to a further loop filter 203 and a phase rotator 205 connected to the further loop filter 203. The phase rotator 205 is in a path 207 between the VCO 120 and an output path 150 and between the VCO 120 and the feedback frequency divider 114. The phase detector

201 is connected to the feedback frequency divider 114 and to the reference frequency divider 104 and receives as input signals a feedback signal from the feedback frequency divider 114 and a reference signal from the reference oscillator 102. The phase detector 201 detects any phase difference between the feedback signal and the reference signal and provides an output signal accordingly to the loop filter 203. The loop filter 203 filters and integrates the output signal from the phase detector 201 and provides a control signal to the phase rotator 205.

The purpose of the further control loop 230 including the phase rotator 205 is as follows. When using the feedback frequency divider 114 in the phase locked loop 230 as a variable divider, e.g. as a fractional-N divider as described earlier, spurious signals can be present in the sideband of the spectrum of the output signal produced by VCO 120 as a result of the rapid switches in the value of the divisor number M applied in the feedback frequency division by the feedback frequency divider 114. Such spurious signals from variable feedback frequency dividers are known in the art. The phase detector 201 measures any phase error arising in this way in the output signal produced by the VCO 120, and a control signal indicating the phase error is provided by the loop filter 203 to the phase rotator 205. The phase rotator 205 applies a phase change to the output signal provided by the VCO 120. The amount of the phase change applied by the phase rotator 205 is determined adaptively by the control signal applied from the loop filter 203 and is thereby adjusted continuously to be suitable to equalize the detected phase error in the output signal provided by the VCO 120. The phase rotator 205 is a known device which rotates the phase of an input signal by a controlled amount, the required amount being as specified by an input control signal applied from the further control loop 230. The phase rotator 205 may be an analog or digital phase rotator. Where the phase rotator 205 is a digital phase rotator, it may operate in a similar manner to a known digital phase rotator used in a modulator of a phase modulated RF transmitter to modulate the phase of a carrier signal. An example of a particular form of digital phase rotator which is preferred is described later with reference to FIG. 8.

The loop bandwidth of the primary loop, i.e. the PLL 130, in the synthesizer 200 is selected to give maximum phase noise suppression of the output signal produced by the VCO 120. Such a bandwidth is therefore narrow, e.g. in the range 2 IcHz to 10 MHz, preferably in the range 2 IcHz to 5 MHz, e.g. for F_Vco = 10 to 20 GHz. In contrast, the loop bandwidth of the secondary loop, i.e. the further control loop 230, is selected to give rapid phase error equalization and suitable system stability. The loop bandwidth of the further control loop 230 is therefore desirably much greater than that of the PLL 130, e.g. at least about twice, in particular typically at least about ten times, the bandwidth of the PLL 130. The bandwidth of the further control loop 230 is desirably at least 10 MHz, e.g. from 10 MHz to 100 MHz, e.g. for F_Vco= 10 MHz to 20 GHz. The controller 108 of the synthesizer 200 may in practice be a programmed digital signal processor. Where the synthesizer 200 is employed in an RF transceiver, the controller 108 may perform other known control and signal processing functions of the transceiver.

The VCO 120 and other components of the synthesizer 200 may beneficially be fabricated in the form of an integrated circuit, e.g. on a semiconductor chip using known fabrication technology. The integrated circuit may also include most of the other components of the synthesizer 200. The reference oscillator 102 and the loop filters 118 and 203 are the only components that will normally need to be supplied separately. In other words, all components enclosed by a dashed line 260 shown in FIG. 1 may be fabricated together in the form of an integrated circuit, e.g. a semiconductor chip. In some cases, it may even be possible to include the loop filter 118 and/or the loop filter 203 in the integrated circuit. FIG. 2 schematically depicts an integrated circuit 270 which includes the components indicated as enclosed by dashed line 260 in FIG. 1 shown as an area 280 of the integrated circuit 270. The integrated circuit 270 optionally may provide one or more other functions as provided by components in another area 290 of the integrated circuit 270.

Reference is now made to FIG. 3, which is a schematic block circuit diagram of a frequency synthesizer, generally referenced as 300, in accordance with a further embodiment of the invention. Components which have the same reference numerals in FIG. 3 as components in the synthesizer 200 of FIG. 1 have the same function as such components and operate in the same way. The synthesizer 300 is a modified form of the synthesizer 200. The modification employed in the synthesizer 300 is an example of an arrangement in which an output signal of desired frequency is obtained by dividing down the frequency of an output signal produced by a high frequency VCO. Such an arrangement is the subject of a copending UK patent application of even date by the Applicant.

In the frequency synthesizer 300 of FIG. 3, the VCO 120 of FIG. 1 is replaced by a VCO 320. The VCO 320 has a VCO tuning and resonating block 312 and a VCO active block 316. The VCO 320 operates at a higher frequency than the VCO 120 (for a given output frequency). For example, if the desired output frequency is in the range 100 MHz to 1 GHz, the VCO 320 may oscillate at a frequency of at least 6 GHz and produce an output signal having a frequency Fyco of at least 6 GHz, e.g. in the range 6 GHz to 60 GHz. The output signal produced by the VCO 320 is applied, as in the synthesizer 200, to the feedback frequency divider 114, which together with the phase frequency detector 110, the charge pump 117, the loop filter 118 and the VCO 320 is in a PLL 330. The PLL 330 operates in the same way as the PLL 130 but using a higher frequency signal from the VCO 320.

The output signal produced by the VCO 320 is also applied to an output path 350 which has two branches 351 and 352. The branch 351 of the output path 350 includes an output frequency divider 341. The branch 352 of the output path 350 includes an output frequency divider 343. The output frequency dividers 341 and 343 operate in a known manner to divide the frequency Fγco of the output signal from the VCO 320 by fixed numbers Nl and N2 respectively. The number Nl by which the output frequency divider 341 divides the frequency Fvco is different from the number N2 by which the output frequency divider 343 divides the frequency F_Vco- The numbers Nl and N2 depend on the value of Fvco and the value of desired output frequencies. For example, where Fvco is 10 GHz, Nl may be 12 and N2 may be 24 giving respectively output signals having frequencies respectively of 10/12 GHz and 10/24 GHz, i.e. frequencies of about 833 MHz and about 416 MHz. The signals of different frequency produced by the output frequency dividers 341 and 343 are delivered to a band selector 345 operating under the control of a controller 347. The band selector 345 provides an output signal having a desired frequency Four by selecting an output signal from either the output frequency divider 341 or from the output frequency divider 343 as appropriate.

The controller 347 in practice may also be a programmed digital signal processor. It may be combined with the controller 108 in a single unit. Where the synthesizer 300 is employed in a RF transceiver, the controller 347 may perform other control and signal processing functions of the transceiver.

The synthesizer 300 illustrates use of multiple output frequency dividers to produce different output frequencies. In principle, any multiple number of different output frequency dividers may be used. Alternatively, the output path 350 could be connected to a single output frequency divider. Although the synthesizer 300 has been described above in terms of a single frequency division being applied by the output frequency divider 341 and 343, the required division may, as will be apparent to those skilled in the art, be carried out in two or more stages in series. For example, an overall frequency division of 24 may be obtained by successive divisions of 8 and 3. By shifting the frequency of the VCO 320 to a much higher frequency than the frequency of the VCO 120, the production of the VCO 320 in the form of an integrated circuit, e.g. fabricated on a semiconductor chip in a known manner, is further facilitated. The integrated circuit incorporating the VCO 320 may also include most of the other components of the synthesizer 300. The reference oscillator 102 and the loop filters 118 and 203 are the only components that will normally need to be supplied separately. In other words, all components enclosed by a dashed line 360 may be fabricated together in the form of an integrated circuit. In some cases, it may even be possible to include the loop filter 118 and/or the loop filter 203 in the integrated circuit.

FIG. 4 schematically depicts an integrated circuit 370 which includes the components indicated by dashed line 360 in FIG. 3 shown as an area 380 of the integrated circuit 370. The integrated circuit 370 optionally may provide one or more other functions as provided by components in another area 390 of the integrated circuit.

PLL oscillator circuits operating at frequencies of 10 GHz or more fabricated in integrated circuit form are already in wide use in the optical communications industry and the technology for producing such circuits can suitably be adapted to produce the synthesizer 300 using the components indicated by area 380 of the integrated circuit 370.

Dividing the VCO output frequency Fycoby the output frequency divider 341 and by the output frequency divider 343 significantly improves the phase noise performance of the synthesizer 300. In particular, the phase noise performance of the output signal at a frequency F_OU_T produced by dividing by a number N_x the frequency of a signal having a frequency Fvco is enhanced by a factor 20*log₁₀(N_x) compared with the signal of frequency F_Vco- For example, at an output frequency of about 800 MHz, the phase noise performance which can be obtained is about -12OdBc at 10kHz offset, -130 dBc for 25 kHz offset, -150 dBc at 500IcHz offset and about -170 dBc for a 2 MHz offset. At an output frequency of about 400 MHz, the phase noise performance which can be obtained is about -125dBc at 10kHz offset, -135 dBc at 25 IcHz offset, -15OdBc at 500IcHz offset and about -170 dBc at 2 MHz offset.

In the synthesizers 200 and 300 the reference oscillator 102 is desirably a low noise oscillator operating at a frequency of at least 100 MHz, e.g. in the range 100 MHz to 200 MHz. A suitable low noise oscillator for use as the reference frequency oscillator 102 is the product sold under the trade name Vectron VCC1-B3B-155M52 which produces an output reference frequency signal at 155 MHz.

FIG. 5 shows an alternative arrangement 600 of components for use in a synthesizer analogous to the synthesizer 200 (or to the synthesizer 300) in place of the arrangement comprising the phase detector 201, the loop filter 203, the phase rotator 205 and the VCO 120. The arrangement 600 is a digital alternative to the analog arrangement it replaces as used in the synthesizer 200. The arrangement 600 includes a phase frequency detector 400 connected to an Up/Down counter 402, a digital encoder 404 connected to the Up/Down counter 402 and to a phase rotator 406 and a VCO 408 connected to the phase rotator 406. The phase frequency detector 400 operates in a manner similar to the phase frequency detector 110 (FIG. 1). The phase frequency detector 400 receives a reference signal 'REF' from the reference oscillator 102 (FIG. 1) and a feedback or variable signal 'VAR' from the feedback frequency divider 114 (FIG. 1). The phase frequency detector 400 produces an 'Up' output pulse if VAR leads REF and a 'Down' output pulse if REF leads VAR. Each 'Up' or 'Down' pulse produced has a width that is proportional to the phase difference between the signals VAR and REF. The 'Up' and 'Down' pulses are delivered to the Up/Down counter 402. The Up/Down counter 402 performs a role in the digital domain analogous to a low pass filter in the analog domain by performing an integration function. The 'Up' and 'Down' pulses produced by the phase frequency detector 400 are counted by the counter 402 which increments for 'Up' pulses and decrements for 'Down' pulses, each increment or decrement being proportional to the received pulse width. The output of the counter 402 is a digital word, for example a 16 bit word which represents the total number obtained (for a given sampled signal frame) by the incrementing and decrementing procedure. The digital word produced by the counter 402 is fed to the digital encoder 404 which translates the digital word to a digital control word for use by the phase rotator 406, for example a 64 bit word. The phase rotator 406 operates using such a digital word in a manner described in more detail later with reference to FIG. 8 to change a phase of an output signal from the VCO 408. The VCO 408 is in a form suitable to provide, in a manner described later with reference to FIG. 7, an output signal having various phase components which may be employed in the phase rotator 406 to obtain a suitable phase as indicated by the output digital word from the digital encoder 404.

FIG. 6 shows a further alternative arrangement 700 of components for use in a synthesizer analogous to the synthesizer 200 (or in the synthesizer 300) in place of the arrangement comprising the phase detector 201, the loop filter 203, the phase rotator 205 and the VCO 120. The arrangement 700 is a semi-analog form analogous to the digital arrangement 600. The arrangement 700 includes a phase frequency detector 500 connected to a charge pump 502 which in turn is connected to an analog loop filter 504. The analog loop filter 504 is connected to an A/D (analog to digital) converter 506 which in turn is connected to a digital encoder 508. The digital encoder 508 is connected to a phase rotator 406, which is the same as the phase rotator 406 of FIG. 5.

The phase frequency detector 500 operates in a manner similar to the phase frequency detector 110 (FIG. 1). The charge pump 502 and the analog loop filter 504 operate in a manner similar respectively to the charge pump 117 and the loop filter 203 in FIG. 1. The A/D converter 506 converts an analog output signal produced by the analog loop filter 504 into a digital word which is delivered to the digital encoder 508. The digital encoder 508 translates the digital word it receives into a digital control word for use by the phase rotator 406. The phase rotator 406 operates using the digital control word in a manner described in more detail later with reference to FIG. 8 to change a phase of an output signal produced by the VCO 408. FIG. 7 illustrates an arrangement 800 of components in an embodiment of the invention which is a more detailed form of part of the arrangement 600 of FIG. 5 or of the arrangement 700 of FIG. 6. In the arrangement 800 the phase rotator 406 receives input signals from a combination of (i) a phase splitter and inverter 614 and (ii) a VCO 612 which together are equivalent to the VCO 408 shown in FIGS. 5 and 6. The phase rotator 406 also receives a digital encoding signal which is from a digital encoder such as the digital encoder 404 (FIG. 5) or the digital encoder 508 (FIG. 6). The VCO 612 produces an output signal in the manner as described earlier for the VCO 120. The output signal is divided into four component signals which have phases respectively ninety degrees apart by the phase splitter and inverter 614. An oscillator such as a VCO producing such component signals is known in the art as one which is in a 'four phase clock' configuration. The four component signals are indicated in FIG. 7 as signals φO, φ90, φl80 and φ270. The phase splitter and inverter 614 also produces four further component signals which are equivalent to the inverse of each of the four component signals φO, φ90, φl80 and φ270. These are indicated as signals φOiNv, ψ90mv, φl80mv and φ270nw. Thus the phase splitter and inverter 614 produces in total eight component signals for delivery to the phase rotator 406 which are the component signals φθ, φ90, φl80 and φ270 and their inverse signals φOj_Nv, φ90iNv, φl80iNv and φ270iMv-

In practice, the component signal φO is available as an output signal from the VCO 612 and it is necessary only to obtain the component signal φ90 from this component signal by a single phase change and then to use an inversion procedure to obtain the other components signals. The component signal φl80 is the inverse of φO and the component signal φ270 is the inverse of φ 90. Each of the component signals φOiNv, ψ90mγ, φl80iNv and φ270iNvis the inverse of one of the resulting component signals φO, φ90, φl80 andφ270. The VCO 612 and the phase splitter and inverter 614 of FIG. 7 in the form of a

'four phase clock' plus inverter may be implemented in a number of ways well known to those skilled in the art. For example, the VCO 612 may be configured as a quadrature VCO which intrinsically produces the desired four phase components φO, φ90, φl80 and ψ270. Producing the inverse of these components is a simple procedure well known and widely used in circuit design, e.g. by use of differential circuits.

Alternatively, in another known arrangement, the output signal is produced normally by the VCO 612 (in the manner described for the VCO 120 with reference to FIG. 1) but at twice the desired frequency. This signal may be passed through a frequency divider which divides the frequency by two using two flip flop latches. The required φ90 component signal may then be obtained in a known manner from a terminal at the junction between the latches and the φO component signal may be obtained in a known manner from the output terminal. If the latches are implemented as differential circuits as is well known in the art then the components φl80 and φ270 are also obtained by inversion. Alternatively, in another known arrangement, the output signal produced by the VCO 612 normally (in the manner described with reference to the VCO 120 with reference to FIG. 1) is passed through a polyphase filter which produces a phase shift of ninety degrees, i.e. the polyphase filter produces the component signal φ90 from the input signal φO, and then produces the other components required φl80 and φ270 by inversion.

FIG. 8 shows in more detail a particular form in which the phase rotator 406 may be implemented in an embodiment of the invention. The circuit of the phase rotator 406 shown in FIG. 8 is in differential signalling form. This is the most commonly used circuit form used in integrated circuit design as it improves immunity to noise. All signals are produced using a pair of conductors, and the value of the required signal is the voltage difference between the conductors. The phase rotator 406 includes four stages each comprising a pair of back to back transistors. Thus, the four stages comprise (i) transistors Tl and T2; (ii) transistors T3 and T4; (iii) transistors T5 and T6; and (iv) transistors T7 and T8. The transistors of each pair, e.g. the transistors Tl and T2, form a differential pair; in other words the signals applied to each are the inverse of one another. The transistors Tl to T8 are shown in FIG. 8 as field effect transistors in NMOS (negative metal oxide semiconductor) form but could be in other known forms, e.g. bipolar form, as will be apparent to those skilled in the art. The transistors Tl, T3, T5 and T7 each have an electrode (drain electrode) connected to a first conductor 658 and the transistors T2, T4, T6, T8 each have an electrode (drain electrode) connected to a second conductor 660. The conductor 658 is connected via a resistor Rl to a positive rail 652 at a potential VD_D and the conductor 660 is connected to the positive rail 652 at a potential VDD via a resistor R2. This arrangement implements an "add" function for the addition of phase vectors as described below.

Each of the transistors Tl to T8 receives at its gate electrode an input signal which is one of the component signals described earlier with reference to FIG. 7. Thus the transistor Tl receives the signal φO, the transistor T2 receives the signal φOmv, the transistor T3 receives the signal φ90, the transistor T4 receives the signal φ90mv, the transistor T5 receives the signal φl80, the transistor T6 receives the signal φl80i_Mv, the transistor T7 receives the signal φ270 and the transistor T8 receives the signal ψ270_INV.

Each of the transistors Tl and T2 is connected at its source electrode to a bank of four transistor switches SWl, SW2, SW3 and SW4 (again shown in NMOS form but which may be implemented in other forms). The transistor switches SWl, SW2, SW3 and SW4 act as voltage controlled current switches. Each of the transistor switches SWl, SW2, SW3 and SW4 is voltage controlled by a connection at its gate electrode to a digital bus line 650. Similarly, each of the transistors T3 and T4 is connected at its source electrode to a bank of four tail current transistor switches SW5, SW6, SW7 and SW8 (again shown in NMOS form but which may be implemented in other forms). The transistor switches SW5, SW6, SW7 and SW8 act as voltage controlled current switches. Each of the transistor switches SW5, SW6, SW7 and SW8 is voltage controlled by a connection at its gate electrode to the digital bus line 650.

Similarly, each of the transistors T5 and T6 is connected at its source electrode to a bank of four tail current transistor switches SW9, SWlO, SWl 1 and SW12 (again shown in NMOS form but which may be implemented in other forms). The transistor switches SW9, SWlO, SWl 1 and SWl 2 act as voltage controlled current switches.

Each of the transistor switches SW9, SWlO, SWl 1 and SW12 is voltage controlled by a connection at its gate electrode to the digital bus line 650.

Similarly, each of the transistors T7 and T8 is connected at its source electrode to a bank of four tail current transistor switches SW13, SW14, SW15 and SW16 (again shown in NMOS form but which may be implemented in other forms). The transistor switches SWl 3, SWl 4, SWl 5 and SWl 6 act as voltage controlled current switches. Each of the transistor switches SW13, SW14, SW15 and SW16 is voltage controlled by a connection at its gate electrode to the digital bias bus line 650. The phase rotator 406 of FIG. 8 further includes a series of 16 identical voltage controlled current source transistors T9 to T24 (again shown in NMOS form but which may be implemented in other forms). Each of transistor switches SWl to SWl 6 is connected at its source electrode to the drain electrode of a corresponding one of the voltage controlled current source transistors T9 to T24. Each of the current source transistors T9 to T24 has its gate electrode connected to a common analog bias line 670 at a bias potential V_BIA_S and has its source electrode connected to ground. Since the transistors T9 to T24 are identical they carry the same current. The series connection of each of the transistor switches and its corresponding current source transistor provided in this manner, for example the transistor switch SWl and the current source transistor T9, or the transistor switch SW2 and the current source transistor TlO, provides a switchable current source. Each of transistor switches SWl to SW16 is controlled by a signal delivered along the digital bus line 650 and directed to that particular switch. These signals are received from a digital encoder in the control loop 230 such as the digital encoder 404 of FIG. 5 or the digital encoder 508 of FIG. 6. Each such signal for each of the switches SWl to SWl 6 is either 'high' (for example 5 V) or low (for example OV). For example, when the signal directed to the transistor switch SW7 via the line 650 is high the transistor switch SW7 will conduct an electric current. When the signal directed to the transistor SW7 via the line 650 is low the transistor switch SW7 will not conduct electric current. The transistor switches SWl to SWl 6 are identical and each operates in a similar manner either to conduct or not conduct according to the corresponding signal received via the digital bus line 650. By switching a selected combination of the transistor switches SWl to SWl 6 to be conducting as required according to the signals received via the digital bus line 650, each of the four phases being input (in differential form) to the phase rotator 406 at the transistors Tl to T8 may be modified as required to produce an output having a desired phase. The output is taken as a pair of differential signals on the conductors 658 and 660 indicated in FIG. 8 as a signal φOUT and its inverse φOXJTmv-

The phases of the signals φO, φ90, φl80 and φ270 can be considered as vectors which can be added in different amounts according to the combination of the transistor switches SWl to SWl 6 selected to be conducting. For example suppose that the desired output phase of the signal φOUTis 225 degrees. This is obtained by switching transistor switches SW9 and SWlO and also transistor switches SWl 3 and SWl 4 to conduct. All of the other transistor switches are off (non-conducting). The transistor switches which are conducting, namely SW9 and SWlO and SWl 3 and SWl 4, provide equal "amounts" of the phase vectors at 180 degrees and at 270 degrees to obtain the required weighted mean or vector sum at 225 degrees. The particular form of phase rotator 406 described with reference to FIG. 8 has four current sources available to modify the phase at each input stage of the phase rotator 406 in quantized steps. In practice, a number much greater than four may be used to obtain quantization steps of suitable small size. For example, 16 current sources per stage (input phase) provided by a total of 64 transistor switches gives suitable phase quantization steps.

It will be apparent to those skilled in the art that an arrangement similar to that of the digital arrangement 600 (including an Up/Down counter and a digital encoder) or the semi-analog arrangement 700 (including an analog to digital converter and a digital encoder) may be used in a feedback loop analogous to the feedback loop 230 of FIGS. 1 or 3 to produce a digital control signal for control of the VCO 130.

The synthesizers 200 and 300 in the various embodiments of the invention described above (including the analogous forms described) are suitable for use in RF transceivers, e.g. to provide carrier frequency signals for transmission or to provide local oscillator signals for use in receiver processing. The synthesizers 200 and 300 are particularly suitable for use in transceivers transmitting at a high power level or receiving a high sensitivity level. An example of a high power transmitter level is an output RF power of at least 10 Watts as measured at the radiator (antenna) of the transmitter. An example of a high sensitivity receiver is a receiver having a sensitivity better than -118 dBm at 3% static BER (Bit Error rate) for a π/4 Differential Quadrature Phase Shift Keyed (DQPSK) modulated signal. Such a transceiver may be suitable for use in a base transceiver station of a mobile wireless communication system, e.g. in particular one for use in accordance with TETRA standards.

Claims

1. An RF (radio frequency) synthesizer including a VCO (voltage controlled oscillator) operable to provide an output signal at a desired frequency, a phase locked loop including (i) the VCO; (ii) a frequency divider operable to receive an output signal of the VCO and to provide a feedback signal which is divided in frequency relative to the output signal of the VCO; and (iii) a phase frequency detector operable to receive the feedback signal produced by the further frequency divider and to compare a phase and frequency of the feedback signal with the phase and frequency of a reference signal; and characterised by (iv) a further control loop inside the phase locked loop; and (v) a phase rotator connected to an output of the VCO and operable to equalize a phase error of an output signal produced by the VCO, the further control loop being connected to the phase rotator to provide a control signal to the phase rotator.

2. An RF synthesizer according to claim 1 wherein the frequency divider is a variable divider.

3. An RF synthesizer according to claim 2 wherein the frequency divider is a fractional-N divider.

4. An RF synthesizer according to any one of the preceding claims wherein the phase rotator is an analog or digital phase rotator.

5. An RF synthesizer according to claim 4 including a phase splitter for producing from the output signal produced by the VCO four component signals having relative phases differing by ninety degrees, wherein the phase rotator is a digital phase rotator and is operable to select and shift the phase of one or more of the component signals and to combine the selected component signals including any applied phase shift to produce a phase which equalizes said phase error.

6. An RP synthesizer according to claim 5 wherein the phase rotator includes four stages for application respectively of the four component signals and, operably connected to each stage, a plurality of electric current sources each of which is selectively operable by a signal from the further control loop to inject current into the stage to shift a phase of the component signal applied at that stage.

7. An RF synthesizer according to claim 6 wherein each stage comprises a transistor connected to the plurality of current sources.

8. An RF synthesizer according to claim 6 or claim 7 wherein each of the current sources comprises a transistor switch.

9. An RF synthesizer according to claim 8 wherein each of the current sources comprises a transistor switch connected in series with a current source transistor.

10. An RF synthesizer according to any one of the preceding claims wherein the further control loop includes a phase detector operable to receive the feedback signal produced by the frequency divider and to compare the phase of the feedback signal with the phase of a reference signal and a loop filter operable to receive a signal produced by the phase detector.

11. An RF synthesizer according to claim 10 wherein the further control loop includes an analog to digital converter operable to receive a signal produced by the loop filter and a digital encoder operable to convert a signal produced by the analog to digital converter into a digital control signal for application to the phase rotator.

12. An RF synthesizer according to any one of claims 1 to 9 wherein the further control loop includes a phase frequency detector operable to produce an output in the form of pulses, a counter operable to count pulses produced by the phase frequency detector and to produce an output signal indicating a sum of pulses counted and a digital encoder operable to convert an output signal produced by the counter into a digital control signal for application to the phase rotator.

13. An RF synthesizer according to any one of the preceding claims wherein the further control loop has a bandwidth which is greater than the bandwidth of the phase locked loop.

14. An RF synthesizer according to claim 13 wherein the bandwidth of the phase locked loop is not greater than 10 MHz and the bandwidth of the further control loop is not less than 10 MHz.

15. An RF synthesizer according to claim 14 wherein the bandwidth of the phase locked loop is in the range of from 2 kHz to 5 MHz and the bandwidth of the further control loop is in the range of from 10 MHz to 100 MHz.

16. An RF synthesizer according to any one claims 12 to 15 including a reference oscillator operable to deliver to the phase detector and the further phase a reference signal having a frequency of at least 100 MHz.

17. An RF synthesizer according to any one of the preceding claims wherein the VCO is operable to oscillate at a frequency of at least 6 GHz.

18 An RF synthesizer according to claim 17 which is operable to produce an output signal at one or more frequencies greater than 100 MHz.

19. An RF synthesizer according to any one of the preceding claims including an integrated circuit which includes at least part of the VCO.

20. An RF synthesizer according to claim 19 wherein the integrated circuit also includes at least part of a phase locked loop.

21. An RF synthesizer according to claim 19 or claim 20 wherein the integrated circuit includes at least part of the further control loop.

22. An RF transmitter for wireless communications including a RF synthesizer according to any one of the preceding claims.

23. An RF receiver for wireless communications including a RF synthesizer according to any one of the preceding claims 1 to 21.

24. An RF transmitter according to claim 22 or an RF receiver according to claim 23 adapted for use in a base transceiver station for mobile wireless communications.

25. An RF synthesizer according to any one of claims 1 to 21 and substantially as described herein with reference to any one or more of FIGS. 2 to 9 of the accompanying drawings.