WO2001011779A2

WO2001011779A2 - Fast acquisition phase locked loop using a current dac

Info

Publication number: WO2001011779A2
Application number: PCT/US2000/021799
Authority: WO
Inventors: Afshin Momtaz
Original assignee: Newport Communications, Inc.
Priority date: 1999-08-11
Filing date: 2000-08-09
Publication date: 2001-02-15

Abstract

In a phase locked loop in which a phase detector compares an input signal to a reference signal and provides a difference signal to a charge pump or to a transconductance amplifier, a digital to analog converter is provided for connecting the output of the charge pump or transconductance amplifier to a voltage controlled oscillator whereby loop bandwidth can be increased from an operating value to an acquisition value for loop phase acquisition by changing the input to the DAC, thereby changing the amplification of the DAC.

Description

FAST ACQUISITION PHASE LOCKED LOOP USING A CURRENT DAC

CROSS-REFERENCES TO RELATED APPLICATIONS This application claims benefit of Provisional Application No. 60/148,418, filed 08/11/99 and is related to co-pending Application Serial No. 19717-000510, filed 03/31/00, which is incorporated herein by reference for all purposes. Both applications are assigned to the Assignee of the present application, NewPort Communications, Inc. of Irvine, California.

BACKGROUND OF THE INVENTION This invention relates generally to electronic circuits, and more particularly the invention relates to phase locked loops which employ transconductance amplifiers and charge pumps. A phase locked loop (PLL) is commonly used in many electronics applications to maintain a fixed phase relationship between an input (e.g., clock) signal and a reference signal. A phase locked loop designed for a digital application typically includes a phase and/or frequency detector, a charge pump, a loop filter, a VCO, and an (optional) divider. The phase detector determines the phase differences between an input signal (i.e., an input data stream or an input clock) and a reference signal derived from the VCO, and generates a detector output signal indicative of the detected phase differences. The charge pump receives the detector output signal and generates a set of phase error signals (e.g., UP and DOWN). The loop filter filters the phase error signals to generate a control signal that is then used to adjust the frequency of the VCO such that the frequencies of the two signals provided to the phase detector are locked.

Fig. 1 is a block diagram of a conventional phase locked loop 100. An input signal is provided to a phase detector 110 that also receives a reference signal from a divider 123. The input signal can be a clock signal, a data stream, or some other types of signal having phase and/or frequency information to which the phase locked loop can locked. The reference signal is typically a clock signal used to trigger the phase detector. Phase detector 110 generates an output signal PDOUT indicative of the timing differences (i.e., the phase differences) between the input signal and the reference signal. The PDOUT signal is provided to a charge pump 114 that generates an output signal CPOUT indicative of the detected phase error between the input and reference signals. In some designs, the PDOUT signal is logic high if the phase of the input signal is early (or late) relative to that of the reference signal, logic low if the phase of the input signal is late (or early) relative to that of the reference signal, and tri-stated for a period of time between clock edges.

The CPOUT signal is provided to a loop filter 120 that filters the signal with a particular transfer characteristic to generate a control signal. The control signal is then provided to, and used to control the frequency of, a voltage-controlled oscillator (VCO) 122. VCO 122 generates an output clock CLK_OUT having a frequency that is locked to that of the input signal (when the phase locked loop is locked). The output clock is provided to divider 123 that divides the frequency of the output clock by a factor of N to generate the reference signal. Divider 123 is optional and not used when the frequency of the output clock is the same as that of the input signal (i.e., N = 1). The control signal adjusts the frequency of VCO 122 such that the frequencies of the two signals provided to phase detector 110 are locked.

The charge pump typically requires an input signal having rail-to-rail signal swing and sharp edges. Signals meeting these requirements can be readily provided by a phase detector at (relatively) low operating frequencies. However, at higher frequencies (e.g., 2.488 GHz for a SONET OC-48 transceiver), it is difficult to design a phase detector having rail-to-rail signal swing and sharp edges. To provide the required signal characteristics, the phase detector would typically need to be designed using a combination of large die area and large amounts of bias current. Besides the design challenge for such phase detector, the rail-to-rail signal swing and sharp edges generate large amounts of noise that can degrade the performance of the phase locked loop and other nearby circuits.

Disclosed in co-pending Application Serial No. 19717, supra, is a locked loop for use in a high frequency application such as an optical transceiver. As shown in Fig. 2, the locked loop includes a detector 110, a transconductance (gm) amplifier 124, a loop filter 120, and an oscillator 122. The detector (which can be a phase detector or a frequency detector, or combination of both) receives an input signal and a reference signal and provides a detector output signal indicative of the difference between the input and reference signals. The difference can be phase or frequency, etc., depending on the application. The gm amplifier receives and converts the detector output signal to a current signal. The loop filter receives and filters the current signal with a particular transfer function to provide a control signal. The oscillator receives the control signal and provides an oscillator signal (e.g., a clock) having a property (e.g., frequency) that is adjusted by the control signal. Resistor 132 and shunt capacitor 134 represent a second loop pole at a high frequency which is normally overlooked in circuit analysis. Acquisition time (or settling time) of a PLL is inversely proportional to its bandwidth. In general, for a PLL with passive filter, the bandwidth, WO, can be expressed in terms of VCO gain, Kvco, the filter primary resistor, Rl, and the gain of phase detector/charge pump block, Kl (Fig. 1). W0 = Kl*Rl*Kvco In the case of gm based PLL (Fig. 2), this equation still applies where Kl represents the product of phase detector gain, Kpd, and gm cell's, gm. Kl = Kpd*gm. Hence: W0=Kpd*gm*Rl*Kvco.

Heretofore, to change the bandwidth, WO, switches have been needed to connect and disconnect appropriate resistors in order to change resistance Rl in the loop filter 120, as shown in Fig. 3 with switches 128 for fast lock and switches 130 for normal operation. However, these switches are connected to the most sensitive part of the phase lock loop, namely the VCO control voltage terminal. Any noise on this node translates directly to jitter at the output of the PLL. Each time these switches are turned on and off, charge is injected on this sensitive node. Further, since the resistance Rl depends on the resistivity parameter and Ron depends on MOSFET switch parameters, and since these parameters can vary from one wafer to another wafer independently, the worst case variation on the effective Rl is increased.

The present invention is directed to avoiding these limitations of the prior art phase lock loops.

SUMMARY OF THE INVENTION In accordance with the present invention, a digital to analog converter, DAC, is used in a phase locked loop with either a charge pump or a transconductance amplifier whereby bandwidth of the loop can be readily changed without changing resistance in the loop filter. The digital input to the DAC can be increased to increase the bandwidth and shorten settling times. As soon as the acquisition is completed, a new set of digital inputs is provided to the DAC, so that the PLL is back to its original bandwidth, which is required for jitter characteristics. A digital signal, "fast lock," is provided at the input of the chip for instruction when the PLL should be in the fast acquisition mode, and when the PLL should switch back to its normal operating mode.

Accordingly, the need for switches in the loop filter is eliminated, thus reducing a source of noise and jitter. Further, the zero and pole of the phase lock loop is not varied since the filter resistance is not varied. Additionally, variations and resistances due to changing parameters from one semiconductor wafer to another is eliminated with the elimination of the switches.

The invention and objects and features thereof will be more readily apparent from the following detailed description and dependent claims when taken with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a functional block diagram of a phase lock loop using a charge pump in accordance with the prior art. Fig. 2 is a functional block diagram of a phase lock loop using a transconductance amplifier as disclosed in co-pending Application Serial No. 19717- 000510.

Fig. 3 is a functional block diagram of the phase lock loop circuit of Fig. 1 showing more details of the loop filter and switches used therein in accordance with the prior art.

Fig. 4 is a functional block diagram of a phase lock loop using a DAC in accordance with one embodiment of the invention.

Fig. 5 is a functional block diagram of a phase lock loop filter using a DAC in accordance with another embodiment of the invention. Fig. 6 is a schematic of a DAC as used in the PLLs of Figs. 4 and 5.

Like elements in the several figures have the same reference numerals.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Fig. 4 is a functional block diagram of a phase lock loop in accordance with one embodiment of the invention which is similar to the phase lock loop of Fig. 2, but with the addition of a DAC 138 between the transconductance amplifier 124 and the loop filter 120. Similarly, Fig. 5 is a functional block diagram of another embodiment of the invention similar to the phase lock loop of Fig. 1 with the addition of a DAC 138 between charge pump 114 and loop filter 120. As noted above, in order to change the bandwidth WO, and consequently the acquisition time of the PLL, one can change the gain of the transconductance cell 124. This is easily implemented using a current DAC at the output of the transconductance cell as shown in Fig. 4. If N represents the current gain of the DAC, then WO=Kpd*gm*N*Rl*Kvco.

Accordingly, during the fast acquisition period, the digital input of DAC 138 is increased (e.g., quadruple) and hence the bandwidth is increased and the settling time is shortened. A digital signal, "fast lock" is provided as an input to the PLL which will provide a new set of digital input to the DAC, so that PLL is reverted to its operating bandwidth. Utilization of DAC 138 is applicable with the charge pump 114, as shown in Fig. 5, as well as with the transconductance amplifier 124 shown in Fig. 4. Dividers 123 are shown in both circuits but are optional.

In Fig. 4 a pole and zero can be provided before the transconductance amplifier 124 with series resistor 132' and shunt capacitor 134' as described in co- pending Application Serial No. 19717-000810. By providing a new pole Wpl before the transconductance amplifier 124, the stability of the phase lock loop during bandwidth adjustment is improved.

Fig. 6 is a schematic of a 2-bit single-ended binary DAC which can be used in the PLL circuits of Figs. 4 and 5. The invention is not limited to the DAC of Fig. 6 and can be used in conjunction with any curent DAC with any number of bits and with any decoding scheme (binary, thermometer, etc.). For simplicity a single-ended DAC is described, but a differential DAC can be used.

Two sets of 2-bit digital data (An, Ai; B₀, Bi) are provided to MUX 150 along with a fast lock signal, one of which is selected and connected to current DAC. These two bits will allow the PLL to have four different bandwidth values during normal and acquisition mode, so that the user can adjust the bandwidth not only for normal mode but also the acquisition mode.

The current I₀ is provided to transistor 151 and if switch 160 is closed (SI

= high), transistor 152 will provide 2I₀ since its size (iwΛ is twice as large as transistor

V L ) 151. Similarly, if switch 161 is closed (S0 = high), transistor 153 will provide I₀ since its

size is equal to transistor 151. Transistor 154 always provides I₀ out. The truth

table below describes the DAC function: SI S0 Transistor 2 Transistor 3 lout current current

Low Low 0 0 Io

Low High 0 Ic 2Io

High Low 2Io 0 3Io

High High 2Io Io 4Io

Use of the DAC in the phase lock loop in accordance with the invention has a number of advantages over the prior art.

1. The PLL loop has a zero, Wzl , and a pole, Wp 1 , due to the loop filter. These pole and zero are given by the following first order equations:

Wzl = 1(R1*C1), Wpl = 1(R1*C2). As it can be seen from these equations, both Wzl and Wpl are inversely proportional to Rl, whereas the bandwidth is directly proportional. On the other hand, the stability of the PLL loop depends on the ratio of Wpl and WO. Hence, in the traditional implementation where Rl is increased to shorten the settling time, this ratio is changed in square law fashion (Wpl/WO = l/(Kl*Kvco*C2*Rl^"2)). In accordance with the invention, however, Rl is kept constant, and N is varied, therefore, Wpl/WO does not change as much and the PLL does not become unstable.

2. In the traditional case, switches are needed to connect and disconnect appropriate resistors, These switches are connected to most sensitive part of the PLL, namely the VCO control voltage. Any noise on this node translates directly to jitter at the output of the PLL. Each time these switches are turned on and off, charge is injected on this sensitive node. In accordance with the invention, these switches are in the DAC and away from this node.

3. By putting a switch in series with Rl , the effective resistance is increased by the Ron of the switch. (Rleff=Rl + Ron). In some applications, Rl can be a small resistor in the same order of magnitude as Ron. The value of Rl is basically determined from the required WO, Kvco, and Kl . Since Rl depends on the resistivity parameter and Ron on the MOSFET parameters, and since these parameters can vary from one wafer to another independently, the worst case variation of the effective Rl is increased. With the invention, there are no switches in series with Rl, and hence this above problem is also alleviated.

While the invention has been described with reference to specific embodiments, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications and applications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A phase locked loop comprising: a) a phase detector coupled to receive an input signal and a reference signal and to provide an output signal indicative of a difference between the input signal and the reference signal, b) a circuit configured to receive the output signal and to generate a conditioned signal output, c) a digital to analog converter for receiving the conditioned signal output and providing an analog output signal, d) a voltage controlled oscillator coupled to receive the analog output signal and provide an oscillator signal in response to the analog output signal, and e) a feedback circuit for providing the reference signal based on the oscillator signal.

2. The phase locked loop as defined by claim 1 wherein the circuit configured to receive the output signal from the phase detector comprises a charge pump.

3. The phase locked loop as defined by claim 2 and further including a loop filter coupling the charge pump output to the voltage controlled oscillator.

4. The phase locked loop as defined by claim 3 wherein the loop filter comprises a serial resistor and capacitor connected to a circuit ground and a second capacitor in parallel with the serial resistor and capacitor and connected to ground.

5. The phase lock loop as defined by claim 4 wherein the loop filter defines a zero and a pole for the loop.

6. The phase locked loop as defined by claim 1 wherein the means for receiving the output signal from the phase detector comprises a transconductance amplifier.

7. The phase locked loop as defined by claim 6 wherein the means for receiving further includes a low pass filter coupling the phase detector output to an input of the transconductance amplifier and defining a loop pole.

8. The phase locked loop as defined by claim 6 and further including a loop filter coupling the transconductance amplifier to the voltage control oscillator.

9. The phase locked loop as defined by claim 8 wherein the loop filter comprises a serial resistor and capacitor connected to a circuit ground and the second capacitor in parallel with the serial resistor and capacitor and connected to ground.

10. The phase locked loop as defined by claim 9 wherein the loop filter defines a zero and a pole for the loop.

11. The phase locked loop as defined by claim 1 wherein the feedback circuit includes a divider.

12. In a phase locked loop in which loop bandwidth, Wo, is increased from an operating value to an acquisition value for loop phase acquisition, a method of changing bandwidth including providing a digital to analog converter (DAC) in the loop whereby loop bandwidth is changed by changing current gain of the digital to analog converter.

13. The method as defined by claim 12 wherein current gain is changed by changing a digital input to the digital to analog converter.

14. The method as defined by claim 13 wherein the digital to analog converter is provided between a charge pump and a voltage controlled oscillator.

15. The method as defined by claim 14 wherein the digital to analog converter is coupled to the voltage controlled oscillator through a loop filter.

16. The method as defined by claim 13 wherein the digital to analog converter is provided between a transconductance amplifier and a voltage controlled oscillator.

17. The method as defined by claim 16 wherein the digital to analog converter is coupled to the voltage controlled oscillator through a loop filter.