CN101124722A - Sigma-delta based phase lock loop - Google Patents

Abstract

A sigma-delta based phase lock loop device is provided that includes a phase frequency detector (PFD), a charge pump and a voltage controlled oscillator. The PFD to receive a reference signal and a feedback signal and to output signals based on a comparison of the reference signal and the feedback signal. The charge pump to output a charge based on the output signals from the PFD. The charge pump including a first current source to apply a fixed amount of current and a second current source to apply a variable amount of current. The voltage controlled oscillator to output a clock signal based on the received charge from the charge pump.

Description

Phase-locked loop based on sigma-delta

This application claims priority from U.S. provisional application No. 60/614402 filed on 9, 30 of 2004. The entire contents of the prior application, which is incorporated by reference, is considered part of the disclosure of this application and is incorporated herein by reference.

Technical Field

Embodiments of the invention may relate to a phase-locked loop circuit.

Background

Modern communication devices, such as cellular telephones, may utilize phase-locked loop devices to frequency synthesize a communication carrier signal modulated with transmit data. The phase-locked loop means allow for precise control of the carrier signal frequency and therefore enable reliable transmission of data on which the carrier signal modulation depends at a stable, known frequency. In such a Phase Locked Loop (PLL) frequency synthesizer, a Voltage Controlled Oscillator (VCO) generates an output carrier signal at a desired frequency in accordance with a VCO frequency control signal. In a simplified PLL structure, this control is achieved by a feedback loop through which the VCO output signal is coupled to a phase-frequency detector that compares the VCO signal phase or frequency with the phase or frequency of a fixed frequency reference signal and generates a frequency control signal corresponding to the phase difference between the VCO signal and the fixed frequency signal. The frequency control signal is smoothed by a low-pass loop filter and then applied to the VCO such that, in its steady state, the VCO output signal frequency matches the frequency of the fixed frequency reference signal.

A frequency divider may be included in the PLL feedback loop to enable the frequency of the VCO output signal to be divided into frequencies that are multiples of the frequency of the fixed frequency reference source. The phase-frequency detector compares the output of the frequency divider with a fixed frequency source to control the VCO phase. In this way, the frequency of the carrier signal generated by the VCO is constantly controlled such that it is "phase locked" to a multiple of the frequency of the fixed frequency reference.

Disclosure of Invention

Embodiments of the present invention may provide a sigma-delta based phase-locked loop device that includes a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, and a divider (divider) circuit. The phase frequency detector may receive a reference signal and a feedback signal and output an UP/DOWN signal based on a comparison of the reference signal and the feedback signal. The charge pump may output a charge based on an output signal from the phase frequency detector. The charge pump may include a first current source to apply a fixed amount of current and a second current source to apply a variable amount of current. The voltage controlled oscillator may output a clock signal based on the charge received from the charge pump. The divider circuit may receive a clock signal output from the voltage controlled oscillator and output a feedback signal to the phase frequency detector. The sigma-delta modulator may be coupled to a divider circuit.

The variable amount of current of the second current source may be based on a phase error of the reference signal and the feedback signal at the phase frequency detector. In addition, the amount of charge output by the charge pump may be linearly proportional to the phase difference between the reference signal and the feedback signal at the phase frequency detector.

Furthermore, the magnitude of the first current source may be greater than the magnitude of the second current source. The different magnitudes may provide a phase offset in a locked state of the phase-locked loop device.

Additional advantages, objects, features and embodiments of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.

Drawings

The foregoing description and a better understanding of the present invention will become apparent from the following detailed description of the configurations and example embodiments and the claims when read in connection with the accompanying drawings, all forming a part of the disclosure of the invention. While the foregoing and following written and illustrated disclosure focuses on disclosing arrangements and example embodiments of the invention, it should be readily understood that the same is by way of illustration and example only and the invention is not limited thereto.

The following is a brief description of the drawings in which like reference numerals refer to like elements and in which:

fig. 1 is a block diagram of a PLL-based frequency synthesizer according to an example configuration;

FIG. 2 is a partial view of a sigma-delta based PLL according to an example configuration;

FIG. 3 is a diagram of a phase frequency detector and charge pump according to an example configuration;

FIG. 4 is a graph representing transfer characteristics of a charge pump based on phase differences without charge pump mismatch according to an example configuration;

FIG. 5 is a graph representing transfer characteristics of a charge pump based on phase difference in the presence of charge pump mismatch according to an example configuration;

FIG. 6 is a timing diagram of signals associated with the charge pump and PFD of FIG. 3 according to an example configuration;

fig. 7 is a graph illustrating transfer characteristics of a phase difference-based charge pump according to an exemplary embodiment of the present invention;

FIG. 8 is a phase frequency detector and charge pump according to an example embodiment of the invention;

FIG. 9 is a timing diagram of signals associated with the charge pump and PFD of FIG. 8, according to an example embodiment of the present invention;

FIG. 10 illustrates a phase frequency detector and charge pump according to an example embodiment of the invention;

fig. 11 is a graph illustrating transfer characteristics of a phase difference-based charge pump according to an exemplary embodiment of the present invention;

fig. 12 is a timing diagram of signals associated with the charge pump and PFD of fig. 10, according to an example embodiment of the present invention.

Detailed Description

In the following detailed description, like numerals and symbols may be used throughout the different drawings to refer to the same, corresponding or similar parts. In addition, in the following detailed description, example sizes/models/values/ranges may be given, but embodiments of the present invention are not limited thereto. Additionally, configurations and embodiments may be shown in block diagram form in order to avoid obscuring the invention, and also because it is contemplated that details regarding implementation of such block diagram configurations may depend on the platform on which the present invention is to be implemented. That is, the details may be well within the scope of one skilled in the art. While specific details are set forth in order to describe example embodiments of the invention, it should be apparent to one skilled in the art that embodiments of the invention can be practiced without these specific details.

The following discussion may use terms that are interchangeable with respect to these figures: signal and signal lines. That is, the term signal may correspond to a signal line shown in the drawings. Configurations and embodiments may also be described with respect to signals as inputs or outputs from different circuit components. Although the discussion refers to a signal, the signal may be conveyed via a signal line or other type of mechanism. Additionally, values or signals may be illustrated as HIGH or LOW and/or up or DOWN, but these illustrations are intended to be related to the configurations and/or embodiments discussed. For example, a value or signal may be described as HIGH in one configuration and LOW (e.g., by a logic change) if provided in another configuration. The terms HIGH and LOW may be used in the general sense desired. Embodiments and configurations may be implemented by logic changes to invert high and low signals in whole/in part.

Phase-locked loops (PLLs) may be used in wired and wireless applications to generate a carrier frequency or timing reference (e.g., a clock signal). Fig. 1 is a block diagram of a PLL-based frequency synthesizer according to an example configuration. Other configurations are also possible. More specifically, fig. 1 shows a PLL including a Phase Frequency Detector (PFD) 10, a Low Pass Filter (LPF) 20 (or loop filter), a Voltage Controlled Oscillator (VCO) 30, and a feedback divider circuit 40. The PFD10 receives a reference signal f _ref And also receives a feedback signal f from divider circuit 40 _fdb . PFD10 vs. reference signal f _ref And a feedback signal f _fdb Compares and outputs the signal to the VCO30 through the low pass filter 20. The filtered signal is essentially a slowly varying or changing DC signal applied to VCO30. VCO30 outputs a VCO signal (f) that can be used as a timing signal _out ). The VCO output signal f may also be used _out Is input to a feedback divider 40, and the feedback divider 40 divides the feedback signal f _fdb Output to the PFD10 for comparison with a reference signal f _ref A comparison is made.

There may be a trade-off between loop bandwidth and channel spacing. That is, when an integer N PLL is used, the channel spacing may be the same as the comparison frequency. The loop bandwidth may be tens of times smaller than the comparison frequency. Since the lock time is inversely proportional to the loop bandwidth, the loop bandwidth can be made smaller to reduce the lock time. In addition to this trade-off, phase noise can also be affected by the loop bandwidth. Since the in-band phase noise can be reduced by increasing the loop bandwidth, the phase noise can also be improved by the same factor. However, the limitation of channel spacing or the frequency resolution of the synthesized output limits the use of PLLs with wide loop bandwidths.

Fig. 2 is a partial view of a sigma-delta based PLL according to an example configuration. Other configurations are also possible. For ease of illustration, fig. 2 shows only a portion of a sigma-delta based PLL. Fig. 2 does not show the PFD10, the low pass filter 20 and the VCO30, which also constitute a PLL. Sigma-delta based PLLs can have fast switching times and arbitrarily small frequency resolution. More specifically, in a sigma-delta based PLL, the divider 40 in the feedback path may be controlled by a sigma-delta modulator 45 for precise frequency resolution. Equation (1) represents a frequency generation equation for a sigma-delta based PLL as shown in fig. 2.

The first two values in parentheses (i.e., the P and K values) are the integer part of the synthesized frequency, while the last values in parentheses (i.e., the S, N and the D value) are the fractional part of the synthesized frequency. In the sigma-delta based PLL, the value of the denominator in the fractional part is very large, whereby the frequency resolution can be improved. Table 1 shows an example for generating frequencies using a sigma-delta based PLL.

Table 1: example of frequency generation using sigma-delta PLL

f VCO	f ref	R	K	P	S	N	D
								915.15MHz	19.68MHz	1	4	11	2	987	1968

One problem with sigma-delta based PLLs is the spurious frequencies (spurious tones) associated with mismatch in the PLL. For example, mismatches in the charge pump and PFD may produce spur values (spurvalues) that are similar to spurs (spurs) produced from fractional-N synthesizers.

The randomized nature of the sigma-delta modulator 45 may become ineffective when there is too much mismatch in the charge pump. In this case, a fractional spur may occur in the output of the VCO, and the offset frequency with respect to the carrier frequency may become equal to the fractional part. To avoid or minimize charge pump mismatch, the configuration can match the UP and DOWN currents of the charge pump (based on the UP/DOWN signals output from the PFD). However, the accuracy of such compensation may be insufficient due to the measurement accuracy. Simulations show that the worst-case mismatch (taking into account process and environmental variations) can exceed a few percent.

FIG. 3 is a Phase Frequency Detector (PFD) and Charge Pump (CP) configured according to an exampleIs shown in the drawing. FIG. 4 is a block diagram illustrating a configuration according to an example without charge pump mismatch (i.e., I) _norm ＝I＊ _norm ) Graph of transfer characteristics of a charge pump based on phase difference. FIG. 5 is a block diagram illustrating a charge pump mismatch condition (i.e., I) according to an example configuration _norm ≠I＊ _norm ) Graph of transfer characteristics of a charge pump based on phase difference. Other configurations, graphs, and data are also possible.

More specifically, fig. 3 shows the reception of the reference signal f _ref And a feedback signal (f) from the VCO (and through the frequency divider circuit 40) _fdb ) A Phase Frequency Divider (PFD) 110.PFD110 compares reference signal f _ref And a feedback signal f _fdb And outputs an UP signal or a DOWN signal to control the oscillation of the VCO. The UP signal and the DOWN signal may also be referred to as an UP pulse and a DOWN pulse, respectively. Fig. 3 also shows an AND gate 130 AND a buffer circuit 120 coupled to the RESET input of the PFD 110. The AND gate 130 outputs a signal based on the signals on the UP signal line AND the DOWN signal line. The buffer circuit 120 provides a delay to prevent any dead zone.

The charge pump may include a current source 140, a current source 150, a capacitor 160, and switches 145 and 155. The output 165 of the charge pump may be coupled to the loop filter to provide a charge (or signal) to the VCO through the loop filter. The current source 140 may apply the current I based on the UP signal applied to the switch 145 _up In which I _up ＝I _norm . Based on the DOWN signal applied to the switch 155, the current source 150 may apply a current I _down In which I _down ＝I＊ _norm . The capacitor 160 is used to store the charge injected from the current sources 140 and 150, which can then be dumped (dump) to the VCO through a low pass filter. Thus, from electricityThe current injected by the current sources 140 and 150 may depend on the respective UP and DOWN signals output from the PFD 110.

Fig. 4 shows the situation where no charge mismatch occurs. This situation represents when I from current source 140 _up Equal to I from current source 150 _down . When this occurs, no phase error occurs in the locked state and no spurious signals can be generated. Since the static charge transferred to the loop filter should be zero in the locked state, any phase shift may occur in the opposite direction to counteract the charge pump mismatch, as shown in fig. 5.

FIG. 5 shows the case where a charge pump mismatch occurs, e.g., I from current source 140 _up Is not equal to I from current source 150 _down . Unlike integer-N synthesizers, sigma-delta based PLLs can change the division factor of the feedback divider 40, and the output of the PFD110The instantaneous phase of the incoming signal can be based on the feedback signal f from the divider 40 _fdb And (6) changing. Thus, the phase offset may be the average phase of the sigma-delta based PLL. In the transfer curve of the PFD110, the average phase may be the crossover point at which there is a net charge transfer (or Q) _up -Q _down ) Becomes zero. The Q value can be defined as Q _(Charge) ＝I _{(electric current)} ·I _(time) . The instantaneous phase from the feedback divider 40 may be shifted back and forth with respect to the centered value.

The PFD having the reset function based on the UP and DOWN signals may be referred to as a 3-state PFD. In addition to the state of input equality, other states may include f _ref Before f _fdb And f _ref Behind f _fdb . When using a 3-state PFD, the PFD and charge pump operation may be significantly different from zero phase error. For example if the phase error is negative or the reference signal f _ref Ahead of the feedback signal f _fdb Then the DOWN pulse can be fixed in time by a reset delay in the PFD 110. Instead, the UP pulse may have pulse difference information. Accordingly, the charge extracted from the loop filter can be fixed every comparison periodAnd the source charge to the loop filter may vary according to the phase difference of the two input signals. On the other hand, if the phase error is positive or the feedback signal f _fdb Ahead of the reference signal f _ref Then the UP pulse may be fixed in time by the reset delay in the PFD 110. Instead, the DOWN pulse may have phase difference information. Thus, the charge extracted from the loop filter may vary according to the phase difference, while the source charge to the loop filter may have a fixed amount for each comparison.

Each UP and DOWN pulse can be made fully linear according to the phase difference determined by the PFD. However, it may be difficult to absolutely match the UP and DOWN currents to maintain the same slope of the transfer characteristic around zero phase error. Thus, if the phase offset caused by the charge pump mismatch is within the variable operating range of the PFD, the linearity of the charge pump may be severely degraded.

Fig. 6 is a timing diagram of signals associated with the charge pump and PFD of fig. 5 according to an example configuration. Fig. 6 shows an example of the non-linear effect of the charge pump (fig. 5). Other configurations, diagrams, and data are also possible. Because the UP and DOWN currents have different slopes, the amount of charge provided to the loop filter may depend on a characterization of the difference between the two current sources 140, 150. Sigma-delta based PLLs generate a random distribution of phase errors centered around the locked state. In the above example, the locked state may have a non-zero phase error due to imbalance of the charge pump, which may have some offset as shown in fig. 5. The difference in slope of the transfer characteristics of fig. 5 may result in non-linear operation of the charge pump from the breakpoint.

The magnitude of the undesired spurs in a sigma-delta based PLL may be inversely proportional to the linearity of the loop for the entire operating range of the PFD. This may mean that in embodiments of the invention, it is not necessary to match the UP and DOWN currents of the current pump in order to obtain linearity of the PFD. Fig. 5 shows that the slope or linearity of the transfer curve changes at (or in) the operating region of the PFD in a sigma-delta based PLL. In this operating region, the stray performance can become very poor and therefore unacceptable for some high-end cellular applications.

Embodiments of the present invention may provide a linearization technique to reduce aliasing in sigma-delta based PLLs. Parameters such as the ratio of the two charge pump current sources and the reset delay of the PFD may be changed (i.e., increased) to provide better spurious rejection. A zero phase error may be desirable in integer N based PLLs without any mismatch to provide low spur levels. However, in a sigma-delta based PLL, the linearity of the charge pump and PFD may be a factor in determining the alias rather than the zero phase offset in the locked state. Intentional ratio mismatch of the two current sources can improve linearity and reduce aliasing.

Fig. 7 is a graph illustrating transfer characteristics of a phase difference-based charge pump according to an exemplary embodiment of the present invention. Other embodiments, graphs, and data are also within the scope of the invention. The operating range (or phase offset range) of the PFD may depend on the particular implementation of the sigma-delta modulator (e.g., sigma-delta modulator 45 shown in fig. 2) and the loop parameters, such as the loop bandwidth. If the amount of charge dumped to the loop filter is equal to the two PFD input signals (i.e., the reference signal f) _ref And a feedback signal f _fdb ) The phase difference therebetween is linear, the desired aliasing may not be present. If the charge pump mismatch becomes too large, the operating region of the PFD may change as shown in fig. 7. Unlike the configuration of fig. 5, there is no change in slope and thus the linearity of the loop is maintained for all operating regions of the PFD. Thus, the magnitude of the aliasing can be very small. In this case, the charge dumped to the loop filter may be proportional to the phase difference. When UP and DOWN current drain occurs in fig. 7, the phase offset between the two inputs of the PFD may be zero in the locked state. However, this may not cause any problems in synthesizer applications, since frequency information may be the only critical factor to be compared to the reference signalNumber f _ref Is not.

Fig. 8 is a diagram of a Phase Frequency Detector (PFD) and charge pump circuit according to an example embodiment of the invention. Fig. 9 is a timing diagram of signals associated with the charge pump and PFD of fig. 8, according to an example embodiment of the present invention. Other embodiments, configurations, and views are also within the scope of the invention. Figure 8 shows a PFD and a charge pump. For ease of illustration, other elements (e.g., VCO, feedback divider, and sigma-delta modulator) are not shown in fig. 8.

Embodiments of the present invention can linearize the operation of a sigma-delta based PLL. The UP and DOWN currents of the charge pump may have different magnitudes (as shown in fig. 8) to provide sufficient phase shift in the locked state (as shown in fig. 7). For example, a constant multiplication factor of K (in fig. 8) may be used as a design parameter for either the UP current source or the DOWN current source. The multiplication factor may be large enough to provide linear operation of the PFD (as shown in fig. 7). The value of K may have been established earlier (or initially) in the PLL or the value of K may be controlled by the control means.

More specifically, fig. 8 shows a Phase Frequency Divider (PFD) 110 that receives a reference signal f from the VCO (and through divider circuit 40) _ref And a feedback signal f _fdb . Similar to the above description, the PFD110 compares the reference signal f _ref And a feedback signal f _fdb And outputs an UP signal and/or a DOWN signal to control oscillation of the VCO. Figure 8 also shows the AND gate 130 AND the buffer circuit 120 coupled to the reset input of the PFD110 in a similar manner as described above with reference to figure 3. The charge pump may include a current source 170, a current source 150, a capacitor 160, and switches 175 and 155. Output terminal 165 may be coupled with a loop filter to provide charge (or signal) to the VCO through the loop filter. Based on the UP signal provided to switch 175, current source 170 may apply a current I _up In which I _up ＝K·I _norm . Based on the DOWN signal applied to the switch 155, the current source 150 may apply a current I _down In which I _down ＝I＊ _norm . The capacitor 160 is used to store the charge injected from the current sources 170 and 150, which can then be dumped to the VCO through the low pass filter. Thus, the current injected from the current sources 170 and 150 may depend on the respective UP and DOWN signals output from the PFD 110.

In other words, in fig. 8, the UP current may be increased to offset the crossover point from zero phase error, as can be seen by comparing fig. 3 and 7. In an embodiment of the present invention, the phase error during PLL operation may be negative and thus the DOWN current may have phase error information. The UP current may be fixed in time by the reset delay in the PFD110, and thus the amount of charge provided to the loop filter from the charge pump may also be fixed for each comparison.

The spurious characteristics resulting from this embodiment are superior to the disadvantageous configuration because the PFD110 and portions of the charge pump current can be made to operate fully linearly. In other words, one of the UP and DOWN current sources may provide a fixed amount of charge for each comparison period, while the other current source may provide a variable amount of charge proportional to the phase error. Due to the switching action of the charge pump circuit, there may be additional sources of error caused by glitches (glitches) and some transients. And, the number of glitches may be significantly different for the switching of the UP and DOWN current sources. The phase offset may also contribute to non-linearity caused by such glitches because one of the two current sources has constant operating conditions.

Fig. 9 is a timing diagram illustrating an operation based on the PFD of fig. 7 and 8. Due to the large intentional mismatch in the UP and DOWN current sources 170 and 150, the DOWN current source 150 may provide a variable amount of charge to the loop filter, while the pulse width of the UP current source 170 may be fixed in time. Thus, linearity of the net charge to the loop filter can be guaranteed.

Fig. 10 illustrates a phase frequency detector and charge pump according to an example embodiment of the invention. Fig. 11 is a graph illustrating transfer characteristics of a charge pump based on a phase difference according to an exemplary embodiment of the present invention. Fig. 12 is a timing diagram of signals associated with the charge pump and PFD of fig. 10, according to an example embodiment of the present invention. Other embodiments, configurations, and diagrams are also within the scope of the invention.

More specifically, fig. 10 shows a Phase Frequency Divider (PFD) 110, which receives a feedback signal f _fdb And a reference frequency signal f from the VCO _ref . Similar to the discussion above, the PFD110 compares the reference frequency signal f _ref And a feedback signal f _fdb And outputs an UP signal and/or a DOWN signal to control oscillation of the VCO. Fig. 10 also shows an AND gate 130 AND a buffer circuit 120 coupled to the RESET input of the PFD110 in a similar manner as described above with reference to fig. 3. The charge pump may include a current source 140, a current source 180, a capacitor 160, and switches 145 and 185. The output 165 of the charge pump may be coupled to the loop filter to provide a charge (or signal) to the VCO through the loop filter. The current source 140 may apply a current I based on the UP signal applied to the switch 145 _up In which I _up ＝K·I _norm . Based on the DOWN signal provided to the switch 185, the current source 180 may apply a current I _down In which I _down ＝K·I＊ _norm . The capacitor 160 is used to store the charge injected from the current sources 140 and 180,the charge may then be dumped to the VCO through a low pass filter. As such, the current injected from the current sources 140 and 180 may depend on the respective UP and DOWN signals output from the PFD 110.

In other words, fig. 10 represents an embodiment that changes the UP current and the DOWN current as compared to an unfavorable configuration, so that linearization may be provided. Fig. 10 shows a larger DOWN current source 180 associated with a constant multiplication factor K. Fig. 11 shows the transfer characteristics when the DOWN current increases. In this embodiment, the operating range of the sigma-delta based PLL is shifted to positive phase errors. Therefore, the phase error is positive and only the UP current has phase error information. The DOWN current may be fixed by the reset delay and the amount of drain current may be fixed in each comparison as shown in fig. 12.

Embodiments of the invention may provide a sigma-delta based PLL comprising a PFD, a charge pump, and a VCO. The charge pump may output charge based on the UP and DOWN signals output from the PFD. The charge pump may include a first current source that applies a fixed amount of current and a second current source that applies a variable amount of current. The variable amount of current may be based on a phase error (or phase difference) between input signals of the PFD. The amount of charge output by the charge pump may be linearly proportional to the phase difference of the two input signals of the PFD. Additionally, the magnitude of the first current source may be greater than the magnitude of the second current source.

Any reference in this specification to "one embodiment," "an embodiment," "example embodiment," etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is submitted that it is within the purview of one skilled in the art to effect such feature, structure, or characteristic in connection with other ones of the embodiments.

Although embodiments of the present invention have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this invention. More particularly, reasonable variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the foregoing disclosure. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.

Claims (25)

1. A phase-locked loop device comprising:

a phase frequency detector to receive a reference signal and a feedback signal, the phase frequency detector to output a signal based on a comparison of the reference signal and the feedback signal;

a charge pump for outputting charges based on an output signal from the phase frequency detector, the charge pump including a first current source for applying a fixed current amount and a second current source for applying a variable current amount; and

a voltage controlled oscillator to output a clock signal based on the charge received from the charge pump.

2. The phase-locked loop device of claim 1, wherein the variable amount of current is based on a phase error of the reference signal and the feedback signal at the phase frequency detector.

3. The phase-locked loop device of claim 1, further comprising a divider circuit for receiving the clock signal output from the voltage-controlled oscillator and outputting a feedback signal to the phase frequency detector.

4. The phase-locked loop device of claim 3, further comprising a sigma-delta modulator coupled to the divider circuit.

5. The phase-locked loop device of claim 1, wherein an amount of charge output by the charge pump is linearly proportional to a phase difference between the reference signal and the feedback signal at the phase frequency detector.

6. The phase-locked loop device of claim 1, wherein the phase-locked loop device comprises a sigma-delta based phase-locked loop device.

7. The phase locked loop device of claim 1, wherein the magnitude of the first current source is greater than the magnitude of the second current source.

8. The phase locked loop device of claim 7, wherein the different magnitudes provide a phase offset in a locked state of the phase locked loop device.

9. The phase-locked loop apparatus of claim 1, further comprising a loop filter for receiving the charge output from the charge pump, the loop filter being disposed between the charge pump and the voltage controlled oscillator.

10. A sigma-delta based phase locked loop device comprising:

a phase frequency detector to receive a reference signal and a feedback signal, the phase frequency detector to output a signal based on a comparison of the reference signal and the feedback signal;

a charge pump having a first current source and a second current source, an amount of charge output by the charge pump being linear in ratio to a phase difference between a reference signal and a feedback signal at a phase frequency detector; and

a voltage controlled oscillator to output a clock signal based on the charge received from the charge pump.

11. The sigma-delta based phase locked loop device of claim 10, wherein the first current source applies a fixed amount of current and the second current source applies a variable amount of current.

12. The sigma-delta phase locked loop device of claim 11, wherein the variable amount of current is based on a phase difference of a reference signal and a feedback signal at the phase frequency detector.

13. The sigma-delta phase locked loop device of claim 11, further comprising a divider circuit for receiving the clock signal output from the voltage controlled oscillator and outputting a feedback signal to the phase frequency detector.

14. The sigma-delta phase locked loop device of claim 13, further comprising a sigma-delta modulator coupled to the divider circuit.

15. The sigma-delta phase locked loop device of claim 11, wherein the magnitude of the first current source is greater than the magnitude of the second current source.

16. The sigma-delta phase lock loop device of claim 15, wherein the different magnitudes provide a phase offset in a locked state of the phase lock loop device.

17. The sigma-delta phase locked loop device of claim 11, further comprising a loop filter for receiving charge output from the charge pump, the loop filter disposed between the charge pump and the voltage controlled oscillator.

18. A semiconductor having a sigma-delta based phase-locked loop device, the phase-locked loop device comprising:

a phase frequency detector to receive a reference signal and a feedback signal, the phase frequency detector to output UP and DOWN signals based on a comparison of the reference signal and the feedback signal;

a charge pump for receiving the UP and DOWN signals from the phase frequency detector, the charge pump having a first current source for providing current based on the UP signal and a second current source for providing current based on the DOWN signal, the first current source having a magnitude greater than the magnitude of the second current source; and

a voltage controlled oscillator to output a clock signal based on the charge received from the charge pump.

19. The semiconductor of claim 18, wherein the first current source applies a fixed amount of current and the second current source applies a variable amount of current.

20. The semiconductor of claim 19, wherein the variable amount of current is based on a phase error of the reference signal and the feedback signal at the phase frequency detector.

21. The semiconductor of claim 18, further comprising a divider circuit for receiving the clock signal output from the voltage controlled oscillator and outputting a feedback signal to the phase frequency detector.

22. The semiconductor of claim 21, further comprising a sigma-delta modulator coupled to the divider circuit.

23. The semiconductor of claim 18, wherein an amount of charge provided by the charge pump is linearly proportional to a phase difference between the reference signal and the feedback signal at the phase frequency detector.

24. The semiconductor of claim 18, wherein the different magnitudes provide a phase offset in a locked state of the phase-locked loop device.

25. The semiconductor of claim 18, the phase-locked loop device further comprising a loop filter for receiving charge from the charge pump, the loop filter disposed between the charge pump and the voltage controlled oscillator.

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