CN116781067A - Dual-linearization frequency and phase discrimination circuit and fractional frequency charge pump phase-locked loop - Google Patents

Dual-linearization frequency and phase discrimination circuit and fractional frequency charge pump phase-locked loop Download PDF

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Publication number
CN116781067A
CN116781067A CN202310802816.5A CN202310802816A CN116781067A CN 116781067 A CN116781067 A CN 116781067A CN 202310802816 A CN202310802816 A CN 202310802816A CN 116781067 A CN116781067 A CN 116781067A
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China
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phase
signal
delay
frequency
charge pump
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Chinese (zh)
Inventor
吴炎辉
李琼
王兰
张陶
李�杰
邱建波
刘永光
李明剑
李家祎
李耕
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Chongqing Southwest Integrated Circuit Design Co ltd
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Chongqing Southwest Integrated Circuit Design Co ltd
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Priority to CN202310802816.5A priority Critical patent/CN116781067A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range

Abstract

The invention provides a bilinear frequency discrimination phase discrimination circuit and a fractional frequency division charge pump phase-locked loop, wherein the bilinear frequency discrimination phase discrimination circuit comprises a first frequency discrimination phase discrimination sub-circuit, a second frequency discrimination phase discrimination sub-circuit and a delay adjustment sub-circuit, a preset phase difference is arranged between a feedback frequency division output signal and a feedback frequency division output delay signal based on delay treatment of the delay adjustment sub-circuit, a preset phase difference is arranged between a rising edge of a first control signal and a rising edge of a second control signal, a preset phase difference is also arranged between a falling edge of a charge pump discharge current and a falling edge of a charge pump charge current, so that the charge pump discharge current and the charge pump charge current synchronously change, and linearization of the charge pump charge discharge current is realized; meanwhile, the charge current of the charge pump is equal to the discharge current of the charge pump, and the effect of double charge and discharge current is achieved in one period, so that the output noise of the charge pump and the closed-loop noise of the phase-locked loop can be effectively reduced.

Description

Dual-linearization frequency and phase discrimination circuit and fractional frequency charge pump phase-locked loop
Technical Field
The invention relates to the technical field of phase-locked loops, in particular to a bilinear frequency discrimination phase-discrimination circuit and a fractional frequency division charge pump phase-locked loop.
Background
Phase locked loops are widely used in the fields of clock synchronization, frequency synthesis, wireless systems, digital circuits, high performance microprocessors, etc. for providing clock frequencies or local oscillator frequencies. Among various phase-locked loop structures, the charge pump phase-locked loop is most widely applied, the capturing range of the charge pump phase-locked loop is large, the working frequency range is only determined by the frequency range of the voltage-controlled oscillator, and the static phase difference is zero when the phase-locked loop is locked, namely, the output signal can track the input signal without phase difference. The phase-locked loop is classified according to the coverage of the frequency division ratio, and has two types, namely an integer frequency-division phase-locked loop and a fractional frequency-division phase-locked loop, the fractional frequency-division phase-locked loop has the characteristics of high frequency resolution, high phase discrimination frequency and the like, and the fractional frequency-division charge pump phase-locked loop is the key development direction of the current phase-locked loop product.
The decimal frequency-division charge pump phase-locked loop comprises a frequency-division phase detector, a charge pump, a loop filter, a voltage-controlled oscillator, a feedback frequency divider and a Sigma-delta modulator, wherein the frequency-division phase detector compares the frequency and the phase between a reference input signal and a feedback frequency-division output signal, the charge pump converts the output signal of the frequency-division phase detector into charging current or discharging current, the loop filter converts the output current of the charge pump into a voltage signal to control the voltage-controlled oscillator, and the voltage-controlled oscillator generates a voltage-controlled oscillation signal with the required frequency. In this process, due to the Sigma-delta modulator, at the rising edge time of different periods, the phase of the feedback frequency-divided output signal may lead or lag from the phase of the reference input signal, and the delay range is: -3 Tvco-4 Tvco (if the interpolation range of the Sigma-delta modulator is-3- +4). Noise at the high frequency of Sigma-delta modulators can fold into the loop bandwidth, exacerbating phase noise in the closed loop of the phase locked loop, especially at wide loop bandwidths.
To solve this problem, a fixed phase offset may be added between the feedback divided output signal and the reference input signal, avoiding the nonlinear region of the charge-discharge current. The traditional technical scheme solves the problem of nonlinearity by adding constant deviation current to the output end of the charge pump, but the scheme needs larger charge pump current for realizing low phase noise, and the larger charge pump current can introduce reference spurious.
Therefore, a technical scheme of a charge pump phase-locked loop capable of realizing linearization of charge-discharge current of the charge pump and reducing fractional frequency division of closed-loop phase noise is needed.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention aims to provide a fractional frequency-division charge pump phase-locked loop technical scheme, which designs a double-linearization frequency-discrimination phase-discrimination circuit, and based on the double-linearization frequency-discrimination phase-discrimination circuit, not only can linearization of charge pump charge-discharge current be realized, but also double charge-discharge current effect of the charge pump can be realized, so as to reduce phase noise of a phase-locked loop closed loop.
In order to achieve the above object and other related objects, the present invention provides the following technical solutions.
A bilinear frequency and phase discrimination circuit for a fractional frequency charge pump phase locked loop, comprising:
the first frequency and phase discrimination sub-circuit receives a reference input signal, a feedback frequency division output signal and a frequency and phase discrimination enabling signal, and performs frequency and phase discrimination processing on the reference input signal and the feedback frequency division output signal under the control of the frequency and phase discrimination enabling signal to obtain a first control signal, wherein the first control signal is used as a discharge control signal of the charge pump;
the second frequency and phase discrimination sub-circuit receives the reference input signal, the feedback frequency division output delay signal and the frequency and phase discrimination enabling signal, and performs frequency and phase discrimination processing on the reference input signal and the feedback frequency division output delay signal under the control of the frequency and phase discrimination enabling signal to obtain a second control signal, wherein the second control signal is used as a charging control signal of the charge pump;
the delay adjusting sub-circuit is used for receiving the feedback frequency division output signal, the clock signal and the delay adjusting control signal, and carrying out delay processing on the feedback frequency division output signal under the control of the delay adjusting control signal to obtain the feedback frequency division output delay signal;
the delay processing of the delay adjusting sub-circuit is based on the fact that a preset phase difference exists between the feedback frequency division output signal and the feedback frequency division output delay signal, the preset phase difference exists between the rising edge of the first control signal and the rising edge of the second control signal, and the preset phase difference also exists between the falling edge of the discharging current of the charge pump and the falling edge of the charging current of the charge pump, so that the discharging current of the charge pump and the charging current of the charge pump synchronously change.
Optionally, the structure of the first frequency-discrimination phase-discrimination sub-circuit is the same as the structure of the second frequency-discrimination phase-discrimination sub-circuit.
Optionally, the delay adjustment sub-circuit includes a first delay control unit, a second delay control unit, a third delay control unit, a first or gate, a second or gate, a third or gate, a fourth or gate, a first D flip-flop, a second D flip-flop, and a third D flip-flop, where an input end of the first delay control unit is used as an input end of the delay adjustment sub-circuit, an input end of the first delay control unit is connected to the feedback frequency division output signal, an output end of the first delay control unit is connected to an input end of the second delay control unit, an output end of the first delay control unit is further connected to a first input end of the second or gate, a delay control end of the first delay control unit is connected to a first input end of the first or gate, an output end of the second delay control unit is connected to a delay control signal, an output end of the second delay control unit is connected to a first input end of the third or gate, an output end of the second delay control unit is connected to a first input end of the delay adjustment control unit, an output end of the second delay control unit is connected to a first input end of the third or gate, an output end of the second delay control unit is connected to a first output end of the third or gate, an output end of the third delay control unit is connected to a first output end of the delay control unit is connected to the first output end of the delay control unit, a third D flip-flop, the clock input end of the first D trigger is connected with the clock signal, the data output positive end of the first D trigger is also connected with the data input end of the second D trigger, the clock input end of the second D trigger is connected with the clock signal, the data output positive end of the second D trigger is connected with the data input end of the third D trigger, the data output positive end of the second D trigger is also connected with the first input end of the fourth OR gate, the clock input end of the third D trigger is connected with the clock signal, the data output positive end of the third D trigger is connected with the second input end of the fourth OR gate, the output end of the fourth OR gate is used as the output end of the delay regulator circuit, and the output end of the fourth OR gate outputs the feedback frequency division output delay signal.
The fractional frequency division charge pump phase-locked loop comprises any one of the bilinear frequency discrimination phase-discrimination circuits, a charge pump, a loop filter, a voltage-controlled oscillator, a feedback frequency divider and a Sigma-delta modulator, wherein the bilinear frequency discrimination phase-discrimination circuits receive the reference input signal, the feedback frequency division output signal, the frequency discrimination phase-discrimination enabling signal, the clock signal and the delay adjustment control signal, the first control signal and the second control signal are obtained after the processing of the bilinear frequency discrimination phase-discrimination circuits, the control end of the charge pump is respectively connected with the first control signal and the second control signal, the first control signal is used as a discharge control signal of the charge pump, the second control signal is used as a charge control signal of the charge pump, the output end of the charge pump is connected with the input end of the loop filter, the output end of the loop filter is connected with the input end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator outputs the voltage-controlled oscillator output end, the feedback end of the feedback frequency divider is connected with the feedback frequency divider output end of the Sigma-delta modulator, and the feedback frequency divider output end of the feedback frequency divider is connected with the input end of the Sigma-delta modulator.
Optionally, a ratio of a period of the clock signal to a period of the voltage controlled oscillation output signal is 4/1.
Optionally, the charging current is equal to the discharging current.
As described above, the bilinear frequency and phase discrimination circuit and the fractional frequency charge pump phase-locked loop of the present invention at least have the following
The beneficial effects are that:
the first frequency discrimination phase discrimination sub-circuit, the second frequency discrimination phase discrimination sub-circuit and the delay adjusting sub-circuit are combined to design a double-linearization frequency discrimination phase discrimination circuit, a preset phase difference is formed between a feedback frequency division output signal and a feedback frequency division output delay signal based on delay processing of the delay sub-circuit, a preset phase difference is formed between the rising edge of a first control signal and the rising edge of a second control signal, a preset phase difference is also formed between the falling edge of discharge current of the charge pump and the falling edge of charge current of the charge pump, and the discharge current of the charge pump and the charge current of the charge pump are synchronously changed, so that linearization of charge-discharge current of the charge pump is realized; meanwhile, the charge current of the charge pump is equal to the discharge current of the charge pump, and the effect of double charge and discharge current is achieved in one period, so that the output noise of the charge pump and the closed-loop noise of the phase-locked loop can be effectively reduced.
Drawings
Fig. 1 shows a block diagram of a charge pump phase-locked loop with fractional frequency division in the prior art.
Fig. 2 is a block diagram of a dual-linearization phase-frequency discrimination circuit according to the present invention.
Fig. 3 shows a circuit diagram of the delay adjuster circuit 3 in fig. 2.
Fig. 4 shows a schematic diagram of the delay output of the delay adjuster circuit 3 in fig. 3.
Fig. 5 shows a block diagram of a fractional-n charge pump phase-locked loop based on a double-linearization phase-demodulation circuit in the present invention.
Fig. 6 is a schematic diagram of a partial circuit configuration of a charge pump phase locked loop based on fractional division of a conventional linearization phase frequency detector.
Fig. 7 is a diagram showing waveforms of input and output of the charge pump in the fractional-n charge pump pll of fig. 6 based on a conventional linearization phase frequency detector.
Fig. 8 is a schematic diagram of a partial circuit structure of a fractional-n charge pump pll based on a dual-linearization phase-demodulation circuit according to the present invention.
Fig. 9 shows waveforms of input and output of the charge pump in the fractional-n charge pump pll of fig. 8 based on the double linearization phase and frequency discrimination circuit.
Fig. 10 shows a graph comparing output noise of a charge pump under the same charge-discharge current condition of a fractional-n charge pump phase-locked loop based on a conventional linearization phase-frequency discriminator and a fractional-n charge pump phase-locked loop based on a double linearization phase-frequency discriminator.
Fig. 11 is a graph of closed-loop phase noise of a conventional linear phase frequency detector based fractional frequency charge pump phase locked loop based on the charge pump output noise index simulation of fig. 10.
Fig. 12 is a graph of closed-loop phase noise of a fractional-division charge pump phase-locked loop based on a double-linearization phase-discriminating circuit based on the charge pump output noise index simulation of fig. 10.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 12. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex. The structures, proportions, sizes, etc. shown in the drawings attached hereto are for illustration purposes only and are not intended to limit the scope of the invention, which is defined by the claims, but rather by the claims.
As mentioned in the foregoing background art, the inventor has studied and found that the circuit structure of the charge pump phase-locked loop with fractional frequency division in the prior art scheme is shown in fig. 1, which includes a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a feedback frequency divider and a Sigma-delta modulator, the phase-frequency detector compares the frequency and the phase between the reference input signal clk_ref and the feedback frequency-divided output signal clk_div, the charge pump converts the output signal of the phase-frequency detector into a charging current or a discharging current, the loop filter converts the output current of the charge pump into a voltage signal to control the voltage-controlled oscillator, and the voltage-controlled oscillator generates the voltage-controlled oscillation signal clk_vco with the required frequency. In this process, due to the Sigma-delta modulator, at the rising edge time of different periods, the phase of the feedback frequency division output signal clk_div may lead or lag from the phase of the reference input signal clk_ref, and the delay range is: 3Tvco to 4Tvco (as shown in FIG. 7, if the interpolation range of the Sigma-delta modulator is-3 to +4). Noise at the high frequency of Sigma-delta modulators can fold into the loop bandwidth, exacerbating phase noise in the closed loop of the phase locked loop, especially at wide loop bandwidths.
To solve this problem, a fixed phase offset may be added between the feedback divided output signal clk_div and the reference input signal clk_ref, avoiding the nonlinear region of the charge-discharge current. The prior art scheme is to add constant deviation current I at the output end of the charge pump bleed The non-linearity problem is solved (as shown in fig. 6), but this solution requires a larger charge pump current to achieve low phase noise, which in turn introduces reference spurs.
Based on this, as shown in fig. 2, the present invention provides a bilinear frequency and phase discrimination circuit, which is applied to a fractional-frequency charge pump phase-locked loop, and comprises:
the first frequency and phase discrimination sub-circuit 1 receives a reference input signal clk_ref, a feedback frequency division output signal clk_div and a frequency and phase discrimination enabling signal pfd_en, performs frequency and phase discrimination processing on the reference input signal clk_ref and the feedback frequency division output signal clk_div under the control of the frequency and phase discrimination enabling signal pfd_en to obtain a first control signal cp_dn, wherein the first control signal cp_dn is used as a discharge control signal of the charge pump;
the second frequency and phase discrimination sub-circuit 2 receives a reference input signal clk_ref, a feedback frequency division output delay signal clk_div1 and a frequency and phase discrimination enabling signal pfd_en, and performs frequency and phase discrimination processing on the reference input signal clk_ref and the feedback frequency division output delay signal clk_div1 under the control of the frequency and phase discrimination enabling signal pfd_en to obtain a second control signal cp_up, wherein the second control signal cp_up is used as a charge control signal of the charge pump;
the delay adjusting sub-circuit 3 receives the feedback frequency division output signal clk_div, the clock signal clk_vco/4 and the delay adjusting control signal delay <2:0>, and performs delay processing on the feedback frequency division output signal clk_div under the control of the delay adjusting control signal delay <2:0> to obtain a feedback frequency division output delay signal clk_div1;
based on the delay processing of the delay adjustment sub-circuit 3, a preset phase difference is formed between the feedback frequency division output signal number clk_div and the feedback frequency division output delay signal number clk_div1, a preset phase difference is formed between the rising edge of the first control signal cp_dn and the rising edge of the second control signal cp_up, and a preset phase difference is formed between the falling edge of the discharging current of the charge pump and the falling edge of the charging current of the charge pump, so that the discharging current of the charge pump and the charging current of the charge pump synchronously change.
In detail, as shown in fig. 2, a reference terminal Fr of the first phase and frequency discriminator circuit 1 receives clk_ref, a feedback frequency dividing terminal Fv of the first phase and frequency discriminator circuit 1 receives a feedback frequency dividing output signal clk_div, an enable terminal EN of the first phase and frequency discriminator circuit 1 receives a phase and frequency discriminator enable signal pfd_en, under the control of the phase and frequency discriminator enable signal pfd_en, the first phase and frequency discriminator circuit 1 performs phase and frequency discriminator processing on the reference input signal clk_ref and the feedback frequency dividing output signal clk_div, a first control signal cp_dn is obtained at an output positive terminal DN of the first phase and frequency discriminator circuit 1, an output negative terminal UP of the first phase and frequency discriminator circuit 1 does not output, and the first control signal cp_dn is used as a discharge control signal of a charge pump in a post-stage circuit; the reference end Fr of the second phase and frequency discrimination sub-circuit 2 receives clk_ref, the feedback frequency dividing end Fv of the second phase and frequency discrimination sub-circuit 2 receives a feedback frequency division output delay signal clk_div1, the enable end EN of the second phase and frequency discrimination sub-circuit 2 receives a phase and frequency discrimination enable signal pfd_en, the second phase and frequency discrimination sub-circuit 2 performs phase and frequency discrimination processing on the reference input signal clk_ref and the feedback frequency division output delay signal clk_div1 under the control of the phase and frequency discrimination enable signal pfd_en, the output negative end UP of the second phase and frequency discrimination sub-circuit 2 obtains a second control signal cp_up, the output positive end DN of the second phase and frequency discrimination sub-circuit 2 does not output, and the second control signal cp_up is used as a discharge control signal of a charge pump in a post-stage circuit.
The structure of the first phase-frequency-discrimination sub-circuit 1 is the same as that of the second phase-frequency-discrimination sub-circuit 2, for example, the phase-frequency-discrimination sub-circuit may be a traditional phase-frequency-discrimination sub-circuit formed by an RS trigger, or may be a non-clock phase-frequency-discrimination sub-circuit, a precharge phase-frequency-discrimination sub-circuit, an edge triggering phase-frequency-discrimination sub-circuit, and the like, and details thereof may be referred to the prior art and will not be described herein.
IN detail, IN an alternative embodiment of the present invention, as shown IN fig. 3, the delay adjustment sub-circuit 3 includes a first delay control unit 31, a second delay control unit 32, a third delay control unit 33, a first or gate 34, a second or gate 35, a third or gate 36, a fourth or gate 310, a first D trigger 37, a second D trigger 38, and a third D trigger 39, the input terminal IN of the first delay control unit 31 is used as the input terminal Fin of the delay adjustment sub-circuit 3, the input terminal IN of the first delay control unit 31 is connected to the input terminal IN of the feedback frequency division output signal clk_div, the output terminal OUT of the first delay control unit 31 is connected to the first input terminal IN of the second delay control unit 32, the output terminal OUT of the first delay control unit 31 is also connected to the first input terminal of the second or gate 35, the delay control terminal OUT of the first delay control unit 31 (as the first delay control terminal d_sel 0 of the delay adjustment sub-circuit 3) is connected to the first delay adjustment control signal delay <0>, the output terminal OUT of the second delay control unit 32 is connected to the first delay control unit 2 as the input terminal of the delay control unit 2, the output terminal OUT of the second delay control unit 2 is connected to the first delay control unit 3, the output terminal OUT of the second delay control unit 2 is connected to the first input terminal of the delay control unit 2 of the delay control unit 3, the output terminal OUT of the second delay control unit is connected to the first delay control unit 2 of the delay control unit 3, the output of the delay control unit is connected to the first input terminal of the delay control unit 3 of the delay control unit is connected to the second delay control unit is connected to the first input terminal of the delay control unit 3, the output end of the second or gate 35 is connected with the second input end of the third or gate 36, the output end of the third or gate 36 is connected with the data input end D of the first D flip-flop 37, the data output positive end Q of the first D flip-flop 37 is connected with the first input end D of the third or gate 36, the clock input end CP of the first D flip-flop 37 is used as the clock end clk of the delay adjustment sub-circuit 3, the clock input end Q of the first D flip-flop 37 is also connected with the data input end D of the second D flip-flop 38, the clock input end CP of the second D flip-flop 38 is connected with the clock signal clk_vco/4, the data output positive end Q of the second D flip-flop 38 is connected with the data input end D of the third or gate 39, the clock input end CP of the third D flip-flop 39 is connected with the clock signal clk_vco/4, the data output end Q of the third D flip-flop 39 is connected with the first input end clk of the fourth or gate 310, and the data output end of the fourth or gate 310 is used as the delay adjustment sub-circuit output end of the fourth or gate 310.
In more detail, as shown in fig. 3, in an alternative embodiment of the present invention, the clock signal clk_vco/4 of the delay adjustment sub-circuit 3 is related to the voltage-controlled oscillation output signal clk_vco of the voltage-controlled oscillator in the subsequent circuit, the ratio of the period of the clock signal clk_vco/4 to the period of the voltage-controlled oscillation output signal clk_vco is 4/1, that is, the period of the clock signal clk_vco/4 is four times the period (Tvco) of the control oscillation output signal clk_vco, the first delay control unit 31, the second delay control unit 32 and the third delay control unit 33 have the same structure, the delay of each delay control unit (the first delay control unit 31, the second delay control unit 32 or the third delay control unit 33) is Δt0, and as shown in fig. 4, the input range of the delay adjustment control signal delay 2:0> input to the delay control terminal (d_sel <2:0 >) is the logic level "001" 111", and the delay of the delay adjustment control signal delay1+fjv 1 input to the delay control signal input to the delay control terminal font_div (delay 1+1+fj) of the output terminal font output signal is the delay signal input to the delay control terminal font_div.
Based on the bilinear phase-discriminating circuit shown in fig. 2-4, the invention also provides a fractional frequency-divided charge pump phase-locked loop, which comprises the bilinear phase-discriminating circuit, a charge pump, a loop filter, a voltage-controlled oscillator, a feedback frequency divider and a Sigma-delta modulator, wherein the bilinear phase-discriminating circuit receives a reference input signal clk_ref, a feedback frequency-divided output signal clk_div, a phase-discriminating enabling signal pfd_en, a clock signal clk_vco/4 and a delay adjustment control signal delay <2:0>, after being processed by the bilinear phase-discriminating circuit, a first control signal cp_dn and a second control signal cp_up are obtained, the control end of the charge pump is respectively connected with the first control signal cp_dn and the second control signal cp_up, the first control signal cp_dn is used as a discharging control signal of the charge pump, the second control signal cp_up is used as a charging control signal of the charge pump, the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected with the output end of the voltage-controlled oscillator, and the output end of the voltage-controlled oscillator is connected with the feedback frequency divider is connected with the input end of the voltage-controlled oscillator.
In detail, as shown in fig. 6 to 9, the specific process of comparing and analyzing the principle that the bilinear phase discriminator in the present invention is applied to the fractional-frequency charge pump phase-locked loop with the principle that the traditional linearization phase discriminator is applied to the fractional-frequency charge pump phase-locked loop is as follows:
1) As shown in fig. 6, in a fractional-frequency charge pump phase-locked loop based on a conventional linearization phase-frequency detector, two control signals of the phase-frequency detector respectively control the charge current I of the charge pump up Discharge current I of charge pump dn At the same time, a constant deviation current I is added to the output end of the charge pump bleed To avoid the nonlinear region of charge-discharge current, the output current I of the charge pump cpout By charging current I up Discharge current I dn And constant deviation current I bleed The loop filter outputs the output current I of the charge pump cpout Converted into a voltage signal V tune Voltage signal V tune The charge current I of the charge pump PLL based on decimal frequency division of the conventional linear phase frequency detector during PLL lock is shown in FIG. 7 up Discharge current I dn Output current I of charge pump cpout Is at the rising edge time of different periods due to the Sigma-delta modulator in the phase-locked loopOutput current I cpout The falling edge Ta of (a) fluctuates within a range of-3 Tvco to 4Tvco (assuming that the interpolation range of the Sigma-delta modulator is-3 to +4), and the charge on the loop filter changes to (-3 Tvco to 4 Tvco) I up ；
2) As shown in fig. 8, in the fractional-division charge pump phase-locked loop based on the double-linearization phase-demodulation circuit, two control signals (i.e., a first control signal cp_dn and a second control signal cp_up) of the phase-demodulation circuit respectively control the charge current I of the charge pump up Discharge current I of charge pump dn The first control signal cp_dn is used as a discharge control signal of the charge pump, and the first control signal cp_dn is used for discharging current I of the charge pump dn Performing switch control, wherein the second control signal cp_up is used as a charge control signal of the charge pump, and the second control signal cp_up charges the charge current I of the charge pump up Switch control is performed to output current I of the charge pump cpout By charging current I up And discharge current I dn The loop filter outputs the output current I of the charge pump cpout Converted into a voltage signal V tune Voltage signal V tune In one period, as shown in fig. 9, the charge current I of the charge pump phase-locked loop based on fractional frequency division of the double-linearization phase-demodulation circuit during phase-locked loop locking is shown up Discharge current I dn Output current I of charge pump cpout Based on the delay processing of the delay adjustment sub-circuit 3, the feedback frequency division output signal clk_div and the feedback frequency division output delay signal clk_div1 have a preset phase difference, so that the rising edge of the first control signal cp_dn and the rising edge of the second control signal cp_up also have a preset phase difference, and further, the falling edge of the discharging current of the charge pump and the falling edge of the charging current of the charge pump also have a preset phase difference, when the delay adjustment control signal (delay in the invention<2:0>After the logic level value of the charge pump is determined, the output current I of the charge pump cpout The delay delta t between the falling edges Tb and Tc is fixed, and the output current I is outputted due to the function of the Sigma-delta modulator in the phase-locked loop cpout Both the falling edges Tb and Tc of (a)Simultaneously fluctuates within the range of-3 Tvco to 4Tvco and ensures the output current I of the charge pump cpout For charging currents I alternately staggered in turn up And discharge current I dn Realizes the linearization of charge and discharge current, changes the charge of the loop filter into (-3 Tvco-4 Tvco) (I up +I dn ) (again assuming an interpolation range of-3 to +4 for Sigma-delta modulator), i.e. the charge-discharge current to the loop filter is twice that of the conventional linearized charge pump scheme (in this case, the charge current I is defined) up And discharge current I dn Equal), double charge-discharge current effect exists in one period, and output noise of the charge pump and closed loop noise of the phase-locked loop can be effectively reduced.
In more detail, in an alternative embodiment of the present invention, in order to verify the technical effect of the present invention, a comparison experiment is performed on a fractional-division charge pump phase-locked loop based on a conventional linearization phase-frequency discriminator and a fractional-division charge pump phase-locked loop based on a dual linearization phase-frequency discriminator, respectively, so as to obtain a comparison curve of output noise of a corresponding charge pump under the condition of the same charge-discharge current, as shown in fig. 10; as can be seen from fig. 10, at the frequency offset of 10kHz, the output noise of the charge pump in the fractional-frequency-divided charge pump phase-locked loop based on the conventional linearization phase-frequency discriminator is-213.752 dbV/Hz, the output noise of the charge pump in the fractional-frequency-divided charge pump phase-locked loop based on the dual linearization phase-frequency discriminator is-217.773 dbV/Hz, and at the frequency offset of 10kHz, the output noise of the charge pump in the fractional-frequency-divided charge pump phase-locked loop based on the dual linearization phase-frequency discriminator is reduced by about 4dB compared with the output noise of the charge pump in the fractional-frequency-divided charge pump phase-locked loop based on the conventional linearization phase-frequency discriminator.
In more detail, in another alternative embodiment of the present invention, in order to further verify the technical effects of the present invention, a comparison experiment is performed on a fractional-division charge pump phase-locked loop based on a conventional linearization phase-frequency discriminator and a fractional-division charge pump phase-locked loop based on a dual linearization phase-frequency discriminator, respectively, and the charge pump output noise index of fig. 10 is substituted into Mathcad software to simulate the closed loop output noise of the phase-locked loop, so as to obtain a closed loop phase noise curve of the fractional-division charge pump phase-locked loop based on the conventional linearization phase-frequency discriminator, as shown in fig. 11, where the phase noise at 100kHz frequency offset in the closed loop band of the phase-locked loop is-112.557 dBc/Hz as can be seen from fig. 11; the closed-loop phase noise curve of the charge pump phase-locked loop based on the fractional frequency division of the double-linearization frequency discrimination phase-discrimination circuit is shown in fig. 12, and as can be seen from fig. 12, the phase noise at the 100kHz frequency offset in the closed-loop band of the phase-locked loop is-115.808 dBc/Hz, so that compared with the charge pump phase-locked loop based on the fractional frequency division of the traditional linearization frequency discrimination phase-discrimination circuit, the closed-loop phase noise of the charge pump phase-locked loop based on the fractional frequency division of the double-linearization frequency discrimination phase-discrimination circuit is improved by about 3dB.
The implementation results show that: compared with the traditional linearization charge pump circuit, the bilinear frequency discrimination phase discrimination circuit can realize linearization of charge and discharge current, has the same charge and discharge current, has the double charge and discharge current effect, reduces the output noise by about 4dB, and is simultaneously applied to a closed-loop phase-locked loop, and the closed-loop phase noise of the phase-locked loop is reduced by about 3dB. The low phase noise characteristic of the bilinear frequency discrimination phase discrimination circuit can be widely applied to a radio frequency phase-locked loop system.
In summary, in the bilinear frequency-discrimination phase-discrimination circuit and fractional frequency-division charge pump phase-locked loop provided by the invention, the bilinear frequency-discrimination phase-discrimination circuit is designed by combining the first frequency-discrimination phase-discrimination sub-circuit, the second frequency-discrimination phase-discrimination sub-circuit and the delay adjustment sub-circuit, and based on the delay processing of the delay sub-circuit, a preset phase difference is formed between the feedback frequency-division output signal and the feedback frequency-division output delay signal, a preset phase difference is formed between the rising edge of the first control signal and the rising edge of the second control signal, a preset phase difference is also formed between the falling edge of the discharge current of the charge pump and the falling edge of the charge current of the charge pump, so that the discharge current of the charge pump and the charge current of the charge pump are synchronously changed, and further, the delay (or phase difference) between a plurality of falling edges of the output current of the charge pump is fixed, and linearization of the charge discharge current of the charge pump is realized; meanwhile, the charge current of the charge pump is equal to the discharge current of the charge pump, and the effect of double charge and discharge current is achieved in one period, so that the output noise of the charge pump and the closed-loop noise of the phase-locked loop can be effectively reduced.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (6)

1. A bilinear frequency and phase discrimination circuit, characterized by being applied to a fractional frequency charge pump phase-locked loop, comprising:
the first frequency and phase discrimination sub-circuit receives a reference input signal, a feedback frequency division output signal and a frequency and phase discrimination enabling signal, and performs frequency and phase discrimination processing on the reference input signal and the feedback frequency division output signal under the control of the frequency and phase discrimination enabling signal to obtain a first control signal, wherein the first control signal is used as a discharge control signal of the charge pump;
the second frequency and phase discrimination sub-circuit receives the reference input signal, the feedback frequency division output delay signal and the frequency and phase discrimination enabling signal, and performs frequency and phase discrimination processing on the reference input signal and the feedback frequency division output delay signal under the control of the frequency and phase discrimination enabling signal to obtain a second control signal, wherein the second control signal is used as a charging control signal of the charge pump;
the delay adjusting sub-circuit is used for receiving the feedback frequency division output signal, the clock signal and the delay adjusting control signal, and carrying out delay processing on the feedback frequency division output signal under the control of the delay adjusting control signal to obtain the feedback frequency division output delay signal;
the delay processing of the delay adjusting sub-circuit is based on the fact that a preset phase difference exists between the feedback frequency division output signal and the feedback frequency division output delay signal, the preset phase difference exists between the rising edge of the first control signal and the rising edge of the second control signal, and the preset phase difference also exists between the falling edge of the discharging current of the charge pump and the falling edge of the charging current of the charge pump, so that the discharging current of the charge pump and the charging current of the charge pump synchronously change.
2. The bilinear phase frequency and phase detection circuit of claim 1, wherein the first phase frequency and phase detection sub-circuit has a structure identical to a structure of the second phase frequency and phase detection sub-circuit.
3. The bilinear phase-frequency discrimination circuit according to claim 1, wherein the delay adjustment sub-circuit includes a first delay control unit, a second delay control unit, a third delay control unit, a first or gate, a second or gate, a third or gate, a fourth or gate, a first D trigger, a second D trigger, and a third D trigger, the input end of the first delay control unit is used as the input end of the delay adjustment sub-circuit, the input end of the first delay control unit is connected with the feedback frequency division output signal, the output end of the first delay control unit is connected with the input end of the second delay control unit, the delay control end of the first delay control unit is connected with a first delay adjustment control signal, the output end of the second delay control unit is connected with the input end of the third delay control unit, the output end of the second delay control unit is also connected with the first input end of the first or gate, the input end of the second delay control unit is connected with the second delay control unit, the output end of the second delay control unit is connected with the first delay adjustment signal, the output end of the third delay control unit is connected with the third or gate, the output end of the third delay control unit is connected with the data of the third or gate, the clock input end of the first D trigger is used as the clock end of the delay adjusting sub-circuit, the clock input end of the first D trigger is connected with the clock signal, the data output positive end of the first D trigger is also connected with the data input end of the second D trigger, the clock input end of the second D trigger is connected with the clock signal, the data output positive end of the second D trigger is connected with the data input end of the third D trigger, the data output positive end of the second D trigger is also connected with the first input end of the fourth OR gate, the clock input end of the third D trigger is connected with the clock signal, the data output positive end of the third D trigger is connected with the second input end of the fourth OR gate, the output end of the fourth OR gate is used as the output end of the delay adjusting sub-circuit, and the output end of the fourth OR gate outputs the feedback frequency division output delay signal.
4. The fractional frequency division charge pump phase-locked loop is characterized by comprising the bilinear frequency discrimination phase-discriminating circuit, the charge pump, a loop filter, a voltage-controlled oscillator, a feedback frequency divider and a Sigma-delta modulator according to any one of claims 1-3, wherein the bilinear frequency discrimination phase-discriminating circuit receives the reference input signal, the feedback frequency division output signal, the frequency discrimination enabling signal, the clock signal and the delay adjustment control signal, the first control signal and the second control signal are obtained after the processing of the bilinear frequency discrimination phase-discriminating circuit, the control end of the charge pump is respectively connected with the first control signal and the second control signal, the first control signal is used as a discharge control signal of the charge pump, the output end of the charge pump is connected with the input end of the loop filter, the output end of the voltage-controlled loop filter is connected with the input end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected with the output end of the feedback frequency divider, the feedback end of the feedback frequency divider is connected with the output end of the Sigma-delta modulator, and the output end of the feedback frequency divider is connected with the input end of the Sigma-delta modulator.
5. The fractional-n charge pump phase locked loop of claim 4 wherein the ratio of the period of the clock signal to the period of the voltage controlled oscillating output signal is 4/1.
6. The fractional-n charge pump phase locked loop of claim 5, wherein the charge current is equal to the discharge current.
CN202310802816.5A 2023-06-30 2023-06-30 Dual-linearization frequency and phase discrimination circuit and fractional frequency charge pump phase-locked loop Pending CN116781067A (en)

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