WO2018224144A1

WO2018224144A1 - Phase control of phase locked loop

Info

Publication number: WO2018224144A1
Application number: PCT/EP2017/063861
Authority: WO
Inventors: Henrik Sjöland; Staffan Ek; Tony Påhlsson
Original assignee: Telefonaktiebolaget Lm Ericsson (Publ)
Priority date: 2017-06-07
Filing date: 2017-06-07
Publication date: 2018-12-13

Abstract

A phase controllable Phase Locked Loop, PLL (100) for generating an output signal is disclosed. The PLL comprises a phase frequency detector (200) comprising two latches (210, 220). Each latch comprises a clock input (Clk), a reset input (Formula (I)) and an output (Q). The phase frequency detector (200) further comprises adjustable delay units (231, 232, 241,242, 251, 252) placed at either one or a combination of the clock inputs, the reset inputs and the outputs of the two latches. The adjustable delay units are configured to control a phase of the PLL output signal by receiving a second control signal (261) from a control circuitry (260) to adjust their delay times.

Description

PHASE CONTROL OF PHASE LOCKED LOOP

TECHNICAL FIELD

Embodiments herein relate to phase control of a Phase Locked Loop, PLL. In particular, they relate to phase control and correction of the PLL comprised in an electronic circuit or device, a wireless communication device such as a mobile terminal, a base station in a wireless communication system.

BACKGROUND

Wireless communication systems usually comprise transceivers which comprise receivers and transmitters. The transmitters typically up-convert baseband signals to Radio Frequency (RF) signals for transmission, and the receivers down-convert received RF signals to baseband signals for processing. Such frequency conversion requires producing reliable mixing frequency signals, typically referred to as local oscillator (LO) signals, for use in an RF Integrated Circuit (RFIC) in a wireless communication device. PLLs are often used to provide such mixing frequency signals.

It is foreseeable that 5G cellular systems will use millimetre waves, where the frequencies currently in discussion range between 15 GHz and 60 GHz. In order to use such 5G system outdoors, a longer cyclic prefix, which is used as a guard band between symbols, has to be used compared to newly released 60 GHz indoor systems. Such longer cyclic prefixes necessitate a closer sub-carrier spacing in the Orthogonal Frequency Division Multiplexing (OFDM) modulation. This closer sub-carrier spacing poses stringent phase noise requirements on the output of the PLLs. At the same time, beamforming should be supported to increase the range and capacity of the system, which results in a large number of antenna elements. The signal at each antenna element of a beamforming system will have an individual phase shift that controls the beam and in particular the beam direction. In some implementations, the beam controlling phase shifts are imposed on the local oscillator signal generated by the PLL. In any event, accurate phase shifts are required to provide accurate beamforming. It is also desirable to be able to program the frequency of the local oscillator signal to enable the wireless communication device to operate on different frequency channels and in different bands. Therefore, implementing local oscillator generation circuitry achieving low phase noise, individually programmable phase, programmable frequency, and distributing the local oscillator signals to all transceivers in a beamforming system, are key challenges without consuming excessive power. Some solutions for generating the local oscillator signals with phase control have been published, for example, in A. Axholt, H. Sjoland, "A PLL based 12 GHz LO generator with digital phase control in 90 nm CMOS", Analog Integrated Circuits and Signal Processing, Vol. 67, No. 3, pp. 309-318, 201 1 , and A. Axholt, H. Sjoland, "A 60 GHz receiver front-end with PLL based phase controlled LO generation for phased-arrays" , Analog Integrated Circuits and Signal Processing, Vol. 80, No. 1 , pp. 23-32, 2014. In these solutions, each antenna element is connected to a transceiver, and each transceiver receives individual LO signals from a local phase-controlled PLL. All PLLs receive a common Iower frequency reference signal in a few gigahertz range. In this way it is enough to distribute the reference signal across an integrated circuit, at much Iower power consumption than distributing the LO signal directly. The PLLs will then locally multiply the reference signal to a higher frequency and generate quadrature LO signals. By using a common reference signal, the output signals of the PLLs will be fixed in frequency and phase with respect to each other. Digitally controlled current sources are used to inject current into the loop filters of each local PLL, which will produce a very accurately controlled and linear phase shift of the output signal.

However, in these solutions, the PLL output signal phase will vary over temperature if standard charge pumps are used in the PLLs. The phase may drift about 180 degrees over 100°C temperature change. It is clear that, due to this temperature dependent phase behaviour, even a smaller temperature gradient will have severe impact on the beamforming system.

To make the frequency programmable it is an advantage to make the local high- frequency PLLs programmable. Fractional-N PLLs may be used to achieve high frequency resolution. The advantage in a multi-PLL system is that the quantization noise can then be made independent for the different LO signals. When used in the system the effective quantization noise will then be suppressed by up to 10^*log(N) dB, where N is the number of local PLLs. For N=10 the quantization noise can thus be suppressed by 10dB. By using a single delta-sigma modulator and using different delays the quantization noise gets sufficiently independent. Dependent on the delay and fractional frequency, the output signals of the PLLs will lock in different well defined phase relations. These phase differences can be compensated for by phase control signals. Some methods have been developed to provide high absolute phase accuracy necessary for beamforming.

However, for the purpose of phase error calibration using a feedback scheme, high absolute accuracy is not necessary. It is sufficient to have monotonicity and sufficient phase control range and phase resolution. Except for that, the circuitry should be as simple as possible to introduce minimum power and chip area overhead. SUMMARY

Therefore, it is an object of embodiments herein to provide an improved system for phase control of a PLL. According to one aspect of embodiments herein, the object is achieved by a phase controllable PLL for generating an output signal. The phase controllable PLL comprises an oscillator configured to generate the output signal of the PLL. The phase controllable PLL further comprises a frequency divider configured to generate a feedback signal by dividing the output signal from the oscillator, a phase frequency detector arrangement configured to output a first control signal for controlling the oscillator in response to a detection of a phase deviation between a reference signal and the feedback signal. The phase frequency detector arrangement comprises a phase frequency detector comprising two latches, each latch comprises a clock input, a reset input and an output. The phase frequency detector further comprises adjustable delay units placed at either one or a combination of the clock inputs, the reset inputs and the outputs of the two latches. The adjustable delay units are configured to control a phase of the PLL output signal by receiving a second control signal from a control circuitry to adjust their delay times.

The solution according to embodiments herein provides high resolution and monotonic phase control since it is possible to implement the adjustable delay units with such characteristics. For example, current starved inverters may be used as the adjustable delay units. The current starved inverters have inherent continuous and monotonic characteristics, and if they are connected to a monotonic high resolution digital to analog converter to adjust their delay times, the desired properties of continuous and monotonic phase adjustment may be achieved.

The adjustable delay units may be implemented in several different places, either at the two laches clock inputs, reset inputs, or the data outputs. Therefore, the phase may be controlled by a differential delay, i.e. the delay times of a pair of adjustable delay units for the two laches may be adjusted in opposite directions such that when the delay time of one delay unit is increased, the delay time of the other one is reduced, or vice versa. In such a way, it provides a potential of adjusting the phase over the zero crossing, i.e. also very small phase corrections may be achieved.

Furthermore, for maximum effectiveness it should preferably correct the phase error as early as possible after it occurs in the PLL signal chain. This means that the phase detector should be calibrated. Therefore, in an embodiment, the phase is compensated in the phase frequency detector. Thereby, most thermal errors or phase drift due to temperature may be eliminated at the source.

As the phase frequency detector according to the embodiments herein comprises only two latches, and the adjustable delay units may be implemented by current starved inverters, the circuitry is simple which introduce minimum power and chip area overhead.

Therefore, according to an embodiment, the phase of a PLL may be controlled monotonically and with high resolution, as well as with a minimum of added circuitry. The embodiment herein is well suited for use in feedback based phase calibration systems for correcting phase error due to temperature drift and any other phase errors due to other causes.

According to some embodiments herein, the phase controllable PLL may provide its output signal to a transceiver in a beamforming system. The delay times of the adjustable delay units may be adjusted by the control circuitry based on antenna beam directions of the beamforming system.

BRIEF DESCRIPTION OF THE DRAWINGS

Examples of embodiments herein are described in more detail with reference to attached drawings in which:

Figure 1 is a general block view of a PLL;

Figure 2 is a schematic block view illustrating a phase frequency detector according to

embodiments herein;

Figure 3 is a schematic block view illustrating a current starved inverter;

Figure 4 is a schematic block view illustrating an adjustable delay unit according to

embodiments herein; and

Figure 5 is a block diagram illustrating an electronic circuit or device in which embodiments herein may be implemented.

DETAILED DESCRIPTION

Figure 1 shows a general block view of a PLL 100, which is a delta-sigma controlled fractional-N PLL. As shown in Figure 1 , the PLL 100 comprises a phase frequency detector PFD 110 to receive a reference signal REF and a feedback signal FB and generate a signal indicating a phase difference between the signals REF and FB, a charge pump CHP which receives the signal from the PFD 1 10 and generates a control signal 111 , a loop filter LF to filter the control signal 1 1 1 and a voltage controlled oscillator VCO 120 to receive the filtered control signal 1 12. The PLL further comprises a divider DIV 130 to divide an output signal OUT of the VCO 120 and generate the feedback signal FB. A delta-sigma modulator DSM receives a frequency command word FCW and controls the divider DIV 130 to make sure the average frequency of the output signal OUT from the PLL is x times the frequency of the reference signal REF, typically x is in the order of 10 to100. The delta-sigma modulator DSM adds jitter to the feedback signal FB which is low-pass filtered in the PLL loop filter LF. The loop filter LF generates a control voltage 1 12 to control the frequency of the VCO, based on the phase difference between the reference signal REF and the feedback signal FB. The VCO is thus phase locked to the reference signal REF.

The PFD 1 10, CHP and LF in the PLL 100 are referred to hereafter as a phase frequency detector arrangement 140, which is configured to output a first control signal 1 12 to control the oscillator in response to a detection of a phase deviation between the reference signal REF and the feedback signal FB.

In theory when the PLL is in locked condition, it has a constant output signal phase (with respect to the reference signal, frequency multiplied by x), no matter other

circumstances. However, a typical charge pump PLL has an output signal phase which is sensitive to impairments such as loop filter leakage currents, the charge-pump CHP output impedance, varying tuning voltage and varied charge pump output current over

temperature. The VCO center frequency drifts with temperature and to maintain frequency lock, the PLL compensates this drift by varying the control voltage 1 12. The output phase difference of the PLL is equal to the input phase difference multiplied with the PLL division ratio of the divider DIV, making the system very sensitive for large division ratios.

To compensate for the impairments described above and also phase errors due to other causes, as well as provide a phase controllable PLL for a beamforming system in a wireless communication system, a phase frequency detector PFD 200 according to embodiments herein is shown in Figure 2. The PFD 200 may be implemented in the PLL 100 to replace the PFD 1 10 shown in Figure 1 .

In the embodiment shown in Figure 2, the PFD 200 comprises two latches 210, 220. Each latch comprises a clock input Clk, a reset input R and an output Q. The phase frequency detector 200 further comprises adjustable delay units 231 , 232, 241 ,242, 251 , 252 placed at either one or a combination of the clock inputs Clk, the reset inputs R and the outputs Q of the two latches 210, 220.

The adjustable delay units are configured to control a phase of the PLL output signal OUT by receiving a second control signal 261 from a control circuitry Ctrl. C 260 to adjust their delay times. According to some embodiments herein, the phase frequency detector PFD 200 may be implemented by two D-flip-flops working as the two latches 210, 220 and a feedback network with a NAND gate. The phase response may be tuned by delaying the signal differently in the two D-flip-flops. This delay difference may be introduced either at the clock input Clk, at the reset input R , or at the data output Q, as shown in Figure 2. The delays may be introduced either as separate delay blocks, or directly inside the flip-flops by current starving parts of the signal chain connected to respective input or output.

The adjustable delay units 231 , 232, 241 ,242, 251 , 252 may be implemented in different ways or with any prior art solutions, such as inverter based circuits used for fine, precise, and accurate pulse delay control in high-speed digital integrated circuits. Figure 3 shows a current starved inverter 300 as one example implementation of a variable delay or an adjustable delay unit. The control current tri can control delay time of the inverter by varying the maximum amount of current that can charge the output capacitance, where less current results in an increased time delay.

In order to achieve wide phase control range, the adjustable delay units may be realized as a chain of current starved inverters 400 with control currents trn , I_ctri2■■■ triN, as shown in Figure 4. For different current settings l_ctrii , IctrE■■■ IctriN, the current starved inverters chain 400 will provide different delays.

To investigate the performance and illustrate advantages of embodiments herein, embodiments of the adjustable PFD 200 has been simulated. Delay units at three different locations indicated in Figure 2 have been investigated. In the simulations, a pair of adjustable delay units has been placed at the clock inputs, the reset inputs or the outputs of the two latches. Results are discussed below.

According to some embodiments herein, the pair of current starved inverters in the pair of adjustable delay units may be controlled in opposite directions to introduce differential delay. That means when the delay time of one delay unit is increased, the delay time of the other one is reduced, or vice versa.

According to some embodiments herein, the control circuitry 260 may comprise digital to analogue converters to generating differential control currents for the pair of the adjustable delay units.

The inverters may be starved only on the P-type transistor side, delaying the positive output pulse transitions, as shown in Figure 3. When an adjustable delay unit is placed at inputs that are active low, such as the reset inputs R , an inverter may be used after the delay unit, to delay the negative output pulse transition rather than the positive one. An inverter may also be needed to cancel the inverting characteristic of the current starved inverter, since a cascade of two inverters will act as a delay, but not invert the signal. The inverters may alternatively be starved on the N-type transistor side, delaying the negative output pulse transitions. They can also be starved at both the N and P side.

When the delay units have been placed on the reset inputs, e.g. the delay units 251 , 252, a parametric analysis has been performed by sweeping the differential delay from negative to positive values. As a result, the length of the charge up and charge down pulses from the outputs UP/DN of the PFD 200 are changed in opposite directions by controlling the time of the negative pulse transitions, i.e. the reset inputs. In this case the control range was adapted to 30GHz operation, where the period time is 33ps. An adjustment range of +/- 17ps was thus sufficient to cover a 360 degree output phase range.

When the delay units have been placed on the clock inputs Clk, the length of the charge up pulse was in this case changing with different delay settings, whereas the length of the charge down pulse was unaffected. However, the difference in length between the charge up and charge down pulses was well controlled as the case discussed above. This means the output current of the charge pump CHP is well controlled which results in that the phase of the PLL output signal may be adjusted as desired.

When the delay units have been placed on the data outputs Q, the effect was similar to that with the delay units placed at the clock inputs Clk.

Therefore, when the PFD 200 according to the embodiments herein is implemented in a PLL, e.g. the PLL 100, the phase of the PLL may be controlled monotonically and with relatively high resolution, as well as with relatively little added circuitry. Embodiments herein are well suited for use in feedback based phase calibration systems for correcting phase error due to temperature drift and any other phase errors due to other causes. In this case, the delay times of the adjustable delay units may adjusted by the control circuitry 260 based on a detected phase error.

According to some embodiments herein, the phase controllable PLL 100 comprising the PFD 200 may provide its output signal to a transceiver in a beamforming system for a wireless communication system. The delay times of the adjustable delay units may be adjusted by the control circuitry based on antenna beam directions of the beamforming system. Although introducing delays to phase detectors have been described before in US 6985551 , "Linear dead-band-free digital phase detection" and in US 6952138, "Generation of a phase locked loop output signal having reduced spurious spectral components", they are for different purposes than phase control of the present application. In US 6985551 , a delay was introduced in the phase detector to make it operate outside its cross-over region in steady state conditions. In this way the non-linearity of the cross-over in the phase detector can be avoided. This is important in a delta-sigma based fractional-N PLL, where this non- linearity would otherwise degrade the noise performance. The mechanism is that high frequency delta-sigma noise is rectified by even-order non-linearity of the phase detector, causing low frequency noise falling in-band in the PLL. In US 6952138, two variable delays were introduced at the phase detector inputs, to reduce the effect of radio frequency (RF) signals being detected by the phase detector, causing disturbance to the PLL. Without the delays the phase detector acts as a sampler responding also to high frequency signals (RF). By introducing varying delays the high frequency response can be attenuated. The delays at both phase detector inputs should vary together, then the operation will not affect the normal PLL operation.

In contrast to the static delay used in US 6985551 and the noise-like delay sequence needed in US 6952138, the adjustable delay units according to embodiments herein are controlled to control the PLL phase, e.g. depending on the desired antenna beam direction or the detected phase error. The required control circuitry 260 may be realized for instance using current steering digital to analog converters (DACs). The differential output currents of these are then connected to the current inputs l_cwi, lcW2,■■■ of the current starved inverters, see Figure 4. The adjustable delay units in Figure 2, may operate in pairs, which may be controlled in opposite directions, i.e. to introduce differential delay. Connecting them to opposite differential outputs of the DACs will accomplish this in a very effective way. The DACs will be controlled by a central control unit, which determines and outputs the DAC input values required to achieve the desired antenna beam direction, or to eliminate a phase error.

When the phase is controlled by a differential delay, it may provide a potential of adjusting the phase over the zero crossing, i.e. also very small phase corrections may be achieved. As the phase is compensated in the PFD, phase errors due to temperature drift and any other phase errors due to other causes may be eliminated at the source.

The phase frequency detector 200 according to embodiments herein is suitable for phase control of a PLL in an electronic circuit or device. Figure 5 shows an electronic circuit or device 500 in which a phase controllable PLL 100 comprising the phase frequency detector 200 according to embodiments herein may be implemented. The electronic circuit or device 500 may be any one of an electronic circuit, such as a transceiver, a transmitter, a receiver, a frequency synthesiser etc.. The electronic circuit or device 500 may also be any one of a communication device, such as a base station or beamforming base station, a mobile terminal or a user equipment for a cellular communications system or in a wireless communication system. The electronic circuit or device 500 may comprise other units, e.g. a memory 520 and a processing unit 530 for information storage and signal processing etc.

When using the word "comprise" or "comprising" it shall be interpreted as non- limiting, i.e. meaning "consist at least of".

The disclosure is not limited to the above described preferred embodiments. Various alternatives, modifications and equivalents may be used. Therefore, the above embodiments should not be taken as limiting the scope of the disclosure.

Claims

1. A phase controllable Phase Locked Loop (100), PLL, for generating an output signal, the phase controllable PLL comprising:

an oscillator (120) configured to generate the output signal (OUT) of the PLL; a frequency divider (130) configured to generate a feedback signal (FB) by frequency dividing the output signal from the oscillator (120);

a phase frequency detector arrangement (140) configured to output a first control signal (1 12) for controlling the oscillator in response to a detection of a phase deviation between a reference signal (REF) and the feedback signal (FB); wherein the phase frequency detector arrangement (140) comprises a phase frequency detector (200) comprising two latches (210, 220), wherein each latch comprises a clock input (Clk), a reset input (ff) and an output (Q); and the phase frequency detector (200) further comprising:

adjustable delay units (231 , 232, 241 ,242, 251 , 252) placed at either one or a combination of the clock inputs, the reset inputs and the outputs of the two latches; and wherein

the adjustable delay units are configured to control a phase of the PLL output signal by receiving a second control signal (261 ) from a control circuitry (260) to adjust their delay times.

2. The phase controllable PLL (100) according to claim 1 , wherein the PLL is configured to provide an output signal to a transceiver in a beamforming system, wherein the delay times of the adjustable delay units are adjusted by the control circuitry (260) based on antenna beam directions of the beamforming system.

3. The phase controllable PLL (100) according to any one of claims 1 -2, wherein the delay times of the adjustable delay units are adjusted by the control circuitry (260) based on a detected phase error.

4. The phase controllable PLL (100) according to any one of claims 1-3, wherein the adjustable delay units comprise current starved inverters (300, 400).

5. The phase controllable PLL (100) according to any one of claims 1 -4, wherein a pair of adjustable delay units (231 , 232, 241 ,242, 251 , 252) is placed at either the pair of clock inputs, the pair of reset inputs or the pair of outputs of the two latches.

6. The phase controllable PLL (100) according to claim 5, wherein the delay times of the pair of adjustable delay units are adjusted in opposite directions such that when the delay time of one delay unit is increased, the delay time of the other one is reduced, or vice versa.

7. The phase controllable PLL (100) according to any one of claims 5-6, wherein the control circuitry (260) comprises digital to analogue converters to generating differential control signals for the pair of the adjustable delay units.

8. An electronic circuit (500) comprising one or a plurality of the PLLs (100) according to any one of claims 1 -7.

9. The electronic circuit (500) according to claim 8, being any one of a frequency

synthesiser, a transceiver, a transmitter, a receiver.

10. An electronic device (500) comprising one or a plurality of the PLLs (100) according to any one of claims 1 -7.

1 1 . The electronic device (500) according to claim 10, being a mobile terminal or a user equipment in a wireless communication system.

12. The electronic device (500) according to claim 10, being a base station or a

beamforming base station in a wireless communication system.