CN204290940U - The clock of fractional frequency division frequency synthesizer adds twitter circuit - Google Patents
The clock of fractional frequency division frequency synthesizer adds twitter circuit Download PDFInfo
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- CN204290940U CN204290940U CN201420411917.6U CN201420411917U CN204290940U CN 204290940 U CN204290940 U CN 204290940U CN 201420411917 U CN201420411917 U CN 201420411917U CN 204290940 U CN204290940 U CN 204290940U
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Abstract
A kind of clock of fractional frequency division frequency synthesizer adds twitter circuit, it is characterized in that it comprises simple and clear radio-frequency transmitter, simple and clear radio-frequency transmitter is primarily of fractional frequency division frequency synthesizer (14), low noise amplifier (15), frequency mixer (16), band pass filter (17), variable gain amplifier (18), analog to digital converter (19) and antenna (20) composition being positioned at front end.The clock of novel fractional frequency division frequency synthesizer of the present utility model adds twitter circuit by adding randomized jitter to the output clock swallowing counter, eliminates the fractional stray on fractional frequency division frequency synthesizer output clock frequency spectrum.Thus the output clock of optimization fractional frequency division frequency synthesizer is made an uproar mutually.
Description
Technical field
The utility model is that the clock be applied in fractional frequency division frequency synthesizer adds twitter circuit, specifically a kind of clock of fractional frequency division frequency synthesizer adds twitter circuit, by adding randomized jitter to the output clock swallowing counter, eliminate the fractional stray on fractional frequency division frequency synthesizer output clock frequency spectrum.
Background technology
Fractional frequency division frequency synthesizer primarily of crystal oscillator, phase frequency detector, charge pump, loop filter, voltage controlled oscillator, dual-modulus prescaler, swallow counter, triangular integration modulator, clock add tremble device, multi-channel gating device, except four-divider and automatic frequency calibrator composition.The advantage of fractional frequency division frequency synthesizer is that output frequency needs not to be the integral multiple of reference frequency, avoids the deterioration of making an uproar mutually that integral frequency divisioil frequency synthesizer causes because channel restriction causes frequency dividing ratio excessive.But the output because of triangular integration modulator has the shake of approximate period, cause very serious fractional stray problem, thus limit the use of fractional frequency division frequency synthesizer.Current way normally causes the disturbance of a randomness in the output of triangular integration modulator, make it be no longer a constant, and the fractional stray on the output spectrum of therefore fractional frequency division frequency synthesizer can by smoothly.But in actual use, effect is unsatisfactory, fractional frequency division frequency synthesizer exports and makes an uproar mutually and can therefore be a greater impact.
Summary of the invention
The utility model is that the clock of the novel fractional frequency division frequency synthesizer of proposition one adds twitter circuit, and object is the fractional stray eliminating fractional frequency division frequency synthesizer, thus the output clock of optimization fractional frequency division frequency synthesizer is made an uproar mutually.
The technical solution of the utility model is:
A kind of clock of fractional frequency division frequency synthesizer adds twitter circuit, it comprises simple and clear radio-frequency transmitter, and simple and clear radio-frequency transmitter forms primarily of fractional frequency division frequency synthesizer 14, low noise amplifier 15, frequency mixer 16, band pass filter 17, variable gain amplifier 18, analog to digital converter 19 and the antenna 20 that is positioned at front end, described fractional frequency division frequency synthesizer 14 is primarily of crystal oscillator 1, phase frequency detector 2, charge pump 3, loop filter 4, voltage controlled oscillator 5, dual-modulus prescaler 6, swallow counter 7, triangular integration modulator 8, clock adds trembles device 9, multi-channel gating device 10, except four-divider 11 and automatic frequency calibrator 12 form, radiofrequency signal is received by antenna 20, amplify through low noise amplifier 15, the local carrier produced with fractional frequency division frequency synthesizer 14 carries out mixing at frequency mixer 16, the intermediate-freuqncy signal produced is through band pass filter 17 filter out-band external noise, suitable power is amplified to again by variable gain amplifier 18, the intermediate-freuqncy signal that the intermediate-freuqncy signal of simulation just can be converted to numeral by analog to digital converter 19 is delivered to base band and is for further processing, dual-modulus prescaler 6 and swallow counter 7 under the control of triangular integration modulator 8 by the feedback clock of the high frequency output clock division tremendously low frequency of voltage controlled oscillator 5, the reference clock that itself and crystal oscillator 1 produce compares by phase frequency detector 2, control charge pump 3 with phase place and difference on the frequency to inject to loop filter 4 or to extract corresponding electric current, the output voltage control of loop filter the output clock frequency of voltage controlled oscillator 5.
The clock of described fractional frequency division frequency synthesizer adds twitter circuit and also comprises clock and add and tremble device 9, and clock adds to be trembled device 9 and comprise multi-channel gating device 10 and except four-divider 11.
Described fractional frequency division frequency synthesizer 14 is widely used in the radio frequency transceiver 21 of wireless communication field, for the frequency mixer 16 in radio frequency transceiver 21 or other circuit provide pure and stable local carrier.
The described clock clock added in twitter circuit 13 adds trembles device 9, the output clock DIVOUT of counter 7 will be swallowed, through four d type flip flop time delays that the output clock HSC of multi-channel gating device 10 drives, the four road gates that the pseudo random sequence that the pseudo-random sequence generator 15 driven by the output clock DIVOUT swallowing counter 7 generates controls select a wherein road to add the output clock FDB trembling device 9 as clock.
The purpose of this utility model is trembled device 9, multi-channel gating device 10 and the clock that forms except four-divider 11 and add twitter circuit 13 by adding to be added by clock on the basis of traditional fractional frequency division frequency synthesizer and realize.Select a road the output of the output of multi-channel gating device 10 from dual-modulus prescaler 6, the output except four-divider 11, voltage controlled oscillator 5 and logical zero and add the high frequency clock input of trembling device 9 as clock, clock adds to be trembled device 9 and carries out phase place change by the high frequency clock of input to the output clock swallowing counter 7, thus realizes clock and add and tremble function.
The beneficial effects of the utility model are:
The clock of novel fractional frequency division frequency synthesizer of the present utility model adds twitter circuit by adding randomized jitter to the output clock swallowing counter, eliminates the fractional stray on fractional frequency division frequency synthesizer output clock frequency spectrum.Thus the output clock of optimization fractional frequency division frequency synthesizer is made an uproar mutually.
The utility model obviously can eliminate the fractional stray of fractional frequency division frequency synthesizer, eliminates the restriction using fractional frequency division frequency synthesizer, and use goes for the rf chip under any frequency range.
Four, accompanying drawing explanation
Shown in Fig. 1 is a simple and clear radio-frequency transmitter block diagram.
Shown in Fig. 2 is the block diagram adopting fractional frequency division frequency synthesizer of the present utility model.
Shown in Fig. 3 is the physical circuit figure that in the utility model, clock adds twitter circuit.
Shown in Fig. 4 is the oscillogram that clock of the present utility model adds the twitter circuit course of work.
Five, specific embodiments
Below in conjunction with accompanying drawing, specific embodiments of the present utility model is further described.
Shown in Fig. 1 is the block diagram of a simple and clear radio-frequency transmitter, forms primarily of fractional frequency division frequency synthesizer 14, low noise amplifier 15, frequency mixer 16, band pass filter 17, variable gain amplifier 18, analog to digital converter 19 and the antenna 20 that is positioned at front end.Radiofrequency signal is received by antenna 20, amplify through low noise amplifier 15, the local carrier produced with fractional frequency division frequency synthesizer 14 carries out mixing at frequency mixer 16, the intermediate-freuqncy signal produced is through band pass filter 17 filter out-band external noise, be amplified to suitable power by variable gain amplifier 18 again, the intermediate-freuqncy signal that the intermediate-freuqncy signal of simulation just can be converted to numeral by analog to digital converter 19 is delivered to base band and is for further processing.
Shown in Fig. 2 is the frame diagram adopting fractional frequency division frequency synthesizer of the present utility model, and clock of the present utility model adds twitter circuit and comprises following three parts: clock adds to be trembled device 9, multi-channel gating device 10 and removes four-divider 11.Select a road the output of the output of multi-channel gating device 10 from dual-modulus prescaler 6, the output except four-divider 11, voltage controlled oscillator 5 and logical zero and add the high frequency clock input of trembling device 9 as clock, clock adds to be trembled device 9 and carries out phase place change by the high frequency clock of input to the output clock swallowing counter 7, thus realizes clock and add and tremble function.
Shown in Fig. 3 is that clock in the utility model adds the physical circuit trembling device 9, primarily of four d type flip flops under the driving of the output clock HSC of multi-channel gating device 10, an output clock DIVOUT HSC clock cycle of time delay respectively of counter 7 will be swallowed, simultaneously pseudo-random sequence generator 15 generates a pseudo random sequence under the driving of clock DIVOUT, controls four road gates and from the output of four d type flip flops, chooses one add the output clock FDB trembling device as clock.
Shown in Fig. 4 is that in the utility model, clock adds the oscillogram of trembling device 9 course of work, is the output HSC of multi-channel gating device 10 respectively, swallows the output DIVOUT of counter 7, output P0, P1, P2, P3 of four d type flip flops and clock and add the output FDB trembling device 9.Output P0, P1, P2, P3 of P tetra-d type flip flops are the output HSC clock cycle of output DIVOUT time delay 1,2,3 and 4 multi-channel gating device 10 swallowing counter 7 respectively.In the diagram, under the control of pseudo-random sequence generator 15, that what clock added that the 1st cycle of the output FDB trembling device 9 select is P0, the 2nd cycle are selected is P1, and that the 3rd cycle is selected is P0.Clock add the phase difference swallowing the output DIVOUT of counter 7 that the output FDB that trembles device 9 and dotted line indicate just in the utility model clock add the pseudo-random perturbation that twitter circuit produces, selecting to export the frequency of HSC clock by controlling multi-channel gating device 10, the target of the fractional stray suppressing fractional frequency-division phase-locked loop can be reached.
The utility model can also have other execution mode, and the technical scheme that all samplings are replaced on an equal basis or equivalent transformation is formed, all drops within the utility model scope required for protection.
Claims (3)
1. the clock of a fractional frequency division frequency synthesizer adds twitter circuit, it is characterized in that it comprises simple and clear radio-frequency transmitter, simple and clear radio-frequency transmitter is primarily of fractional frequency division frequency synthesizer (14), low noise amplifier (15), frequency mixer (16), band pass filter (17), variable gain amplifier (18), analog to digital converter (19) and antenna (20) composition being positioned at front end, described fractional frequency division frequency synthesizer (14) is primarily of crystal oscillator (1), phase frequency detector (2), charge pump (3), loop filter (4), voltage controlled oscillator (5), dual-modulus prescaler (6), swallow counter (7), triangular integration modulator (8), clock adds trembles device (9), multi-channel gating device (10), except four-divider (11) and automatic frequency calibrator (12) composition, radiofrequency signal is received by antenna (20), amplify through low noise amplifier (15), the local carrier produced with fractional frequency division frequency synthesizer (14) carries out mixing at frequency mixer (16), the intermediate-freuqncy signal produced is through band pass filter (17) filter out-band external noise, suitable power is amplified to again by variable gain amplifier (18), the intermediate-freuqncy signal that the intermediate-freuqncy signal of simulation just can be converted to numeral by analog to digital converter (19) is delivered to base band and is for further processing, dual-modulus prescaler (6) and swallow counter (7) under the control of triangular integration modulator (8) by the feedback clock of the high frequency output clock division tremendously low frequency of voltage controlled oscillator (5), the reference clock that itself and crystal oscillator (1) produce compares by phase frequency detector (2), control charge pump (3) with phase place and difference on the frequency to inject to loop filter (4) or to extract corresponding electric current, the output voltage control of loop filter the output clock frequency of voltage controlled oscillator (5).
2. the clock of fractional frequency division frequency synthesizer according to claim 1 adds twitter circuit, it is characterized in that described fractional frequency division frequency synthesizer (14) is widely used in the radio frequency transceiver (21) of wireless communication field, for the frequency mixer (16) in radio frequency transceiver (21) provides pure and stable local carrier.
3. the clock of fractional frequency division frequency synthesizer according to claim 1 adds twitter circuit, it is characterized in that the described clock clock added in twitter circuit (13) adds and tremble device (9), the output clock DIVOUT of counter (7) will be swallowed, through four d type flip flop time delays that the output clock HSC of multi-channel gating device (10) drives, the four road gates that the pseudo random sequence that the pseudo-random sequence generator (15) driven by the output clock DIVOUT swallowing counter (7) generates controls select a wherein road to add the output clock FDB trembling device (9) as clock.
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| CN201420411917.6U CN204290940U (en) | 2014-07-24 | 2014-07-24 | The clock of fractional frequency division frequency synthesizer adds twitter circuit |
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| CN201420411917.6U CN204290940U (en) | 2014-07-24 | 2014-07-24 | The clock of fractional frequency division frequency synthesizer adds twitter circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106849946A (en) * | 2016-12-13 | 2017-06-13 | 航天恒星科技有限公司 | A kind of fractional frequency division frequency synthesizer and decimal frequency dividing method |
| CN107248862A (en) * | 2017-06-09 | 2017-10-13 | 芯海科技（深圳）股份有限公司 | A kind of fractional frequency division reduction frequency jitter circuit and method |
| CN111308882A (en) * | 2019-12-04 | 2020-06-19 | 山东大学 | Circuit system for pseudo satellite clock synchronization and working method thereof |
| CN114726365A (en) * | 2022-06-06 | 2022-07-08 | 深圳市德兴达科技有限公司 | Low-noise phase-locked loop control circuit, device and method |
-
2014
- 2014-07-24 CN CN201420411917.6U patent/CN204290940U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106849946A (en) * | 2016-12-13 | 2017-06-13 | 航天恒星科技有限公司 | A kind of fractional frequency division frequency synthesizer and decimal frequency dividing method |
| CN107248862A (en) * | 2017-06-09 | 2017-10-13 | 芯海科技（深圳）股份有限公司 | A kind of fractional frequency division reduction frequency jitter circuit and method |
| CN111308882A (en) * | 2019-12-04 | 2020-06-19 | 山东大学 | Circuit system for pseudo satellite clock synchronization and working method thereof |
| CN111308882B (en) * | 2019-12-04 | 2021-07-06 | 山东大学 | Circuit system for pseudo satellite clock synchronization and working method thereof |
| CN114726365A (en) * | 2022-06-06 | 2022-07-08 | 深圳市德兴达科技有限公司 | Low-noise phase-locked loop control circuit, device and method |
| CN114726365B (en) * | 2022-06-06 | 2022-08-19 | 深圳市德兴达科技有限公司 | Low-noise phase-locked loop control circuit, device and method |
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